From nobody Wed Feb 11 02:54:42 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1508215229760414.105888722931; Mon, 16 Oct 2017 21:40:29 -0700 (PDT) Received: from localhost ([::1]:36423 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e4Jfx-0006so-5V for importer@patchew.org; Tue, 17 Oct 2017 00:40:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50838) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e4JOe-0008Ui-M9 for qemu-devel@nongnu.org; Tue, 17 Oct 2017 00:22:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e4JOb-0007D2-TU for qemu-devel@nongnu.org; Tue, 17 Oct 2017 00:22:28 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:53357) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e4JOb-00079X-Ho; Tue, 17 Oct 2017 00:22:25 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 3yGMTy3sgRz9t66; Tue, 17 Oct 2017 15:22:11 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1508214134; bh=SCGOUgEN29TTcwcqaNtQ/caQ5SdH94lOkpkBfrhaPM8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JgRMK8hknoEkqEnuCKg9+jpBbQTc2xHAdOzpmHyk+wJYAbSEbSrvjGyaMsP1abrJ4 /McIcX5KO5/qEGk/5HzQuZ6pY4PU5ZqcCzfRg6AexC8IFtRzgdgJIG4Yp9m4t1M0k7 7ct5vXPbsjKo1TWe5Uy2gwjcNO4oXyiK5IHpBuUk= From: David Gibson To: peter.maydell@linaro.org Date: Tue, 17 Oct 2017 15:21:44 +1100 Message-Id: <20171017042152.29443-27-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171017042152.29443-1-david@gibson.dropbear.id.au> References: <20171017042152.29443-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 26/34] ppc: pnv: use generic cpu_model parsing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: agraf@suse.de, ehabkost@redhat.com, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, imammedo@redhat.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Igor Mammedov use common cpu_model prasing in vl.c and set default cpu_model using generic MachineClass::default_cpu_type. Beside of switching to generic infrastructure it solves several issues. * ppc_cpu_class_by_name() is used to deal with lower/upper case and alias translations into actual cpu type, which fixes '-M powernv -cpu power8' and '-M powernv -cpu power9_v1.0' usecases which error out with: 'invalid CPU model 'FOO' for powernv machine' * allows to switch to lower-case typenames in pnv chip/core name (by convention typnames should be lower-case) * replace aliased names /power8, power9, .../ with exact cpu model names (i.e. typenames should be stable but aliases might decide to point to other cpu model withi family or changed by kvm). It will also help to simplify pnv_chip/core code and get rid of dependency on cpu_model parsing. Signed-off-by: Igor Mammedov Reviewed-by: C=C3=A9dric Le Goater [dwg: Updated to make DD2.0 as default POWER9 chip] Signed-off-by: David Gibson --- hw/ppc/pnv.c | 22 ++++++++++------------ hw/ppc/pnv_core.c | 2 +- include/hw/ppc/pnv.h | 8 ++++---- 3 files changed, 15 insertions(+), 17 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 84b2389ea6..a2cb4a40ff 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -606,16 +606,13 @@ static void ppc_powernv_init(MachineState *machine) } } =20 - /* We need some cpu model to instantiate the PnvChip class */ - if (machine->cpu_model =3D=3D NULL) { - machine->cpu_model =3D "POWER8"; - } - /* Create the processor chips */ - chip_typename =3D g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_mo= del); + i =3D strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); + chip_typename =3D g_strdup_printf(TYPE_PNV_CHIP "-%.*s", + i, machine->cpu_type); if (!object_class_by_name(chip_typename)) { - error_report("invalid CPU model '%s' for %s machine", - machine->cpu_model, MACHINE_GET_CLASS(machine)->name); + error_report("invalid CPU model '%.*s' for %s machine", + i, machine->cpu_type, MACHINE_GET_CLASS(machine)->nam= e); exit(1); } =20 @@ -715,7 +712,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *kl= ass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->cpu_model =3D "POWER8E"; + k->cpu_model =3D "power8e_v2.1"; k->chip_type =3D PNV_CHIP_POWER8E; k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask =3D POWER8E_CORE_MASK; @@ -737,7 +734,7 @@ static void pnv_chip_power8_class_init(ObjectClass *kla= ss, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->cpu_model =3D "POWER8"; + k->cpu_model =3D "power8_v2.0"; k->chip_type =3D PNV_CHIP_POWER8; k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask =3D POWER8_CORE_MASK; @@ -759,7 +756,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *= klass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->cpu_model =3D "POWER8NVL"; + k->cpu_model =3D "power8nvl_v1.0"; k->chip_type =3D PNV_CHIP_POWER8NVL; k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask =3D POWER8_CORE_MASK; @@ -781,7 +778,7 @@ static void pnv_chip_power9_class_init(ObjectClass *kla= ss, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->cpu_model =3D "POWER9"; + k->cpu_model =3D "power9_v2.0"; k->chip_type =3D PNV_CHIP_POWER9; k->chip_cfam_id =3D 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ k->cores_mask =3D POWER9_CORE_MASK; @@ -1132,6 +1129,7 @@ static void powernv_machine_class_init(ObjectClass *o= c, void *data) mc->init =3D ppc_powernv_init; mc->reset =3D ppc_powernv_reset; mc->max_cpus =3D MAX_CPUS; + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power8_v2.0"); mc->block_default_type =3D IF_IDE; /* Pnv provides a AHCI device for * storage */ mc->no_parallel =3D 1; diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 67264830db..91f02cb324 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -227,7 +227,7 @@ static const TypeInfo pnv_core_info =3D { }; =20 static const char *pnv_core_models[] =3D { - "POWER8E", "POWER8", "POWER8NVL", "POWER9" + "power8e_v2.1", "power8_v2.0", "power8nvl_v1.0", "power9_v2.0" }; =20 static void pnv_core_register_types(void) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 9c5437dabc..d80fa44bf0 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -80,19 +80,19 @@ typedef struct PnvChipClass { uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); } PnvChipClass; =20 -#define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E" +#define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-power8e_v2.1" #define PNV_CHIP_POWER8E(obj) \ OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) =20 -#define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-POWER8" +#define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-power8_v2.0" #define PNV_CHIP_POWER8(obj) \ OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) =20 -#define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-POWER8NVL" +#define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-power8nvl_v1.0" #define PNV_CHIP_POWER8NVL(obj) \ OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) =20 -#define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-POWER9" +#define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-power9_v2.0" #define PNV_CHIP_POWER9(obj) \ OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) =20 --=20 2.13.6