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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id i187sm5594249pfc.96.2017.10.16.10.26.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Oct 2017 10:26:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mupzlOYUAuyNywOnggVbrrdzIC7T3+eQFkWsnwKDReo=; b=fykog55GnhboxY86I2Djd7qEQCM+I3+yIMD6ahDlWHuID0zEP1fBZmgZAH8Qe8P1qr p0OEfJIPCKRsgUZ5X5AI0rj6DtoUNUU3zisiMm6co/yB6ZZTKXIJNUpsCvrifFLRzHbV 7iZFQYzN7Fm09Uk64b0OnZzMO+7D/CICA/kGE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mupzlOYUAuyNywOnggVbrrdzIC7T3+eQFkWsnwKDReo=; b=AqbiQYV4ziGJW3cxEmlEBTm8t1XJ0YtlFRnF6IOx76A58C/ori2A35EYEvg63OSRN1 TnGDJQ8EWxkhW9yHY82Yw9KGqLCf+6M37Dp0NQa0VtRG4mRJ0FtpB0wW/0yabk57DSBz oODcPNlu4G7e0r7bhcioXdRZ+JRyBju9Ybbd5oDBqF1+oAUh4YYwebWJJofFmKNcbabR G5BbH/rMmeHnsPQ52gpKEAKreEklL4829o/2xp/iHas5Rd/VhKQp1NfneevHwUMHs3Dd D8MyncM2XifJIJX0hzdjY2WlB2hAteknklvtG91vZUTdAWvMbkYgcTqhJ6gFWiouM5Fb 3Tbg== X-Gm-Message-State: AMCzsaUbQGMkWcw0gXyk874ih+qH9mEriLQeXuPXS7+n8rrc5ZvhJtSA fMN34SPxWcYGeXjH2PXav95qN4gY4DY= X-Google-Smtp-Source: AOwi7QAOMAxG3MRSzlAmWD+gqflHr+touUIKHNhDtT1OcwgVdXKIRrnmNzodxLYqSb/k8uIE+vtL1g== X-Received: by 10.159.208.5 with SMTP id a5mr9744896plp.436.1508174778543; Mon, 16 Oct 2017 10:26:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 16 Oct 2017 10:25:23 -0700 Message-Id: <20171016172609.23422-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org> References: <20171016172609.23422-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PATCH v6 04/50] tcg: Propagate TCGOp down to allocators X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota --- tcg/tcg.c | 78 ++++++++++++++++++++++++++++++++---------------------------= ---- 1 file changed, 40 insertions(+), 38 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 4f56077f64..147b8904d8 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2334,25 +2334,24 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TC= GTemp *ots, } } =20 -static void tcg_reg_alloc_movi(TCGContext *s, const TCGArg *args, - TCGLifeData arg_life) +static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op) { - TCGTemp *ots =3D &s->temps[args[0]]; - tcg_target_ulong val =3D args[1]; + TCGTemp *ots =3D &s->temps[op->args[0]]; + tcg_target_ulong val =3D op->args[1]; =20 - tcg_reg_alloc_do_movi(s, ots, val, arg_life); + tcg_reg_alloc_do_movi(s, ots, val, op->life); } =20 -static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def, - const TCGArg *args, TCGLifeData arg_life) +static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) { + const TCGLifeData arg_life =3D op->life; TCGRegSet allocated_regs; TCGTemp *ts, *ots; TCGType otype, itype; =20 allocated_regs =3D s->reserved_regs; - ots =3D &s->temps[args[0]]; - ts =3D &s->temps[args[1]]; + ots =3D &s->temps[op->args[0]]; + ts =3D &s->temps[op->args[1]]; =20 /* Note that otype !=3D itype for no-op truncation. */ otype =3D ots->type; @@ -2382,7 +2381,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOpDef *def, liveness analysis disabled). */ tcg_debug_assert(NEED_SYNC_ARG(0)); if (!ots->mem_allocated) { - temp_allocate_frame(s, args[0]); + temp_allocate_frame(s, op->args[0]); } tcg_out_st(s, otype, ts->reg, ots->mem_base->reg, ots->mem_offset); if (IS_DEAD_ARG(1)) { @@ -2416,10 +2415,10 @@ static void tcg_reg_alloc_mov(TCGContext *s, const = TCGOpDef *def, } } =20 -static void tcg_reg_alloc_op(TCGContext *s,=20 - const TCGOpDef *def, TCGOpcode opc, - const TCGArg *args, TCGLifeData arg_life) +static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) { + const TCGLifeData arg_life =3D op->life; + const TCGOpDef * const def =3D &tcg_op_defs[op->opc]; TCGRegSet i_allocated_regs; TCGRegSet o_allocated_regs; int i, k, nb_iargs, nb_oargs; @@ -2430,21 +2429,24 @@ static void tcg_reg_alloc_op(TCGContext *s, TCGArg new_args[TCG_MAX_OP_ARGS]; int const_args[TCG_MAX_OP_ARGS]; =20 + /* Sanity check that we've not introduced any unhandled opcodes. */ + tcg_debug_assert(!(def->flags & TCG_OPF_NOT_PRESENT)); + nb_oargs =3D def->nb_oargs; nb_iargs =3D def->nb_iargs; =20 /* copy constants */ memcpy(new_args + nb_oargs + nb_iargs,=20 - args + nb_oargs + nb_iargs,=20 + op->args + nb_oargs + nb_iargs, sizeof(TCGArg) * def->nb_cargs); =20 i_allocated_regs =3D s->reserved_regs; o_allocated_regs =3D s->reserved_regs; =20 /* satisfy input constraints */=20 - for(k =3D 0; k < nb_iargs; k++) { + for (k =3D 0; k < nb_iargs; k++) { i =3D def->sorted_args[nb_oargs + k]; - arg =3D args[i]; + arg =3D op->args[i]; arg_ct =3D &def->args_ct[i]; ts =3D &s->temps[arg]; =20 @@ -2462,7 +2464,7 @@ static void tcg_reg_alloc_op(TCGContext *s, if (ts->fixed_reg) { /* if fixed register, we must allocate a new register if the alias is not the same register */ - if (arg !=3D args[arg_ct->alias_index]) + if (arg !=3D op->args[arg_ct->alias_index]) goto allocate_in_reg; } else { /* if the input is aliased to an output and if it is @@ -2503,7 +2505,7 @@ static void tcg_reg_alloc_op(TCGContext *s, /* mark dead temporaries and free the associated registers */ for (i =3D nb_oargs; i < nb_oargs + nb_iargs; i++) { if (IS_DEAD_ARG(i)) { - temp_dead(s, &s->temps[args[i]]); + temp_dead(s, &s->temps[op->args[i]]); } } =20 @@ -2527,7 +2529,7 @@ static void tcg_reg_alloc_op(TCGContext *s, /* satisfy the output constraints */ for(k =3D 0; k < nb_oargs; k++) { i =3D def->sorted_args[k]; - arg =3D args[i]; + arg =3D op->args[i]; arg_ct =3D &def->args_ct[i]; ts =3D &s->temps[arg]; if ((arg_ct->ct & TCG_CT_ALIAS) @@ -2566,11 +2568,11 @@ static void tcg_reg_alloc_op(TCGContext *s, } =20 /* emit instruction */ - tcg_out_op(s, opc, new_args, const_args); + tcg_out_op(s, op->opc, new_args, const_args); =20 /* move the outputs in the correct register if needed */ for(i =3D 0; i < nb_oargs; i++) { - ts =3D &s->temps[args[i]]; + ts =3D &s->temps[op->args[i]]; reg =3D new_args[i]; if (ts->fixed_reg && ts->reg !=3D reg) { tcg_out_mov(s, ts->type, ts->reg, reg); @@ -2589,9 +2591,11 @@ static void tcg_reg_alloc_op(TCGContext *s, #define STACK_DIR(x) (x) #endif =20 -static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs, - const TCGArg * const args, TCGLifeData arg_= life) +static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) { + const int nb_oargs =3D op->callo; + const int nb_iargs =3D op->calli; + const TCGLifeData arg_life =3D op->life; int flags, nb_regs, i; TCGReg reg; TCGArg arg; @@ -2602,8 +2606,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, int allocate_args; TCGRegSet allocated_regs; =20 - func_addr =3D (tcg_insn_unit *)(intptr_t)args[nb_oargs + nb_iargs]; - flags =3D args[nb_oargs + nb_iargs + 1]; + func_addr =3D (tcg_insn_unit *)(intptr_t)op->args[nb_oargs + nb_iargs]; + flags =3D op->args[nb_oargs + nb_iargs + 1]; =20 nb_regs =3D ARRAY_SIZE(tcg_target_call_iarg_regs); if (nb_regs > nb_iargs) { @@ -2622,8 +2626,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, } =20 stack_offset =3D TCG_TARGET_CALL_STACK_OFFSET; - for(i =3D nb_regs; i < nb_iargs; i++) { - arg =3D args[nb_oargs + i]; + for (i =3D nb_regs; i < nb_iargs; i++) { + arg =3D op->args[nb_oargs + i]; #ifdef TCG_TARGET_STACK_GROWSUP stack_offset -=3D sizeof(tcg_target_long); #endif @@ -2640,8 +2644,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, =20 /* assign input registers */ allocated_regs =3D s->reserved_regs; - for(i =3D 0; i < nb_regs; i++) { - arg =3D args[nb_oargs + i]; + for (i =3D 0; i < nb_regs; i++) { + arg =3D op->args[nb_oargs + i]; if (arg !=3D TCG_CALL_DUMMY_ARG) { ts =3D &s->temps[arg]; reg =3D tcg_target_call_iarg_regs[i]; @@ -2663,9 +2667,9 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, } =20 /* mark dead temporaries and free the associated registers */ - for(i =3D nb_oargs; i < nb_iargs + nb_oargs; i++) { + for (i =3D nb_oargs; i < nb_iargs + nb_oargs; i++) { if (IS_DEAD_ARG(i)) { - temp_dead(s, &s->temps[args[i]]); + temp_dead(s, &s->temps[op->args[i]]); } } =20 @@ -2690,7 +2694,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, =20 /* assign output registers and emit moves if needed */ for(i =3D 0; i < nb_oargs; i++) { - arg =3D args[i]; + arg =3D op->args[i]; ts =3D &s->temps[arg]; reg =3D tcg_target_call_oarg_regs[i]; tcg_debug_assert(s->reg_to_temp[reg] =3D=3D NULL); @@ -2838,8 +2842,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { TCGOp * const op =3D &s->gen_op_buf[oi]; TCGOpcode opc =3D op->opc; - const TCGOpDef *def =3D &tcg_op_defs[opc]; - TCGLifeData arg_life =3D op->life; =20 oi_next =3D op->next; #ifdef CONFIG_PROFILER @@ -2849,11 +2851,11 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *t= b) switch (opc) { case INDEX_op_mov_i32: case INDEX_op_mov_i64: - tcg_reg_alloc_mov(s, def, op->args, arg_life); + tcg_reg_alloc_mov(s, op); break; case INDEX_op_movi_i32: case INDEX_op_movi_i64: - tcg_reg_alloc_movi(s, op->args, arg_life); + tcg_reg_alloc_movi(s, op); break; case INDEX_op_insn_start: if (num_insns >=3D 0) { @@ -2878,7 +2880,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) tcg_out_label(s, arg_label(op->args[0]), s->code_ptr); break; case INDEX_op_call: - tcg_reg_alloc_call(s, op->callo, op->calli, op->args, arg_life= ); + tcg_reg_alloc_call(s, op); break; default: /* Sanity check that we've not introduced any unhandled opcode= s. */ @@ -2886,7 +2888,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) /* Note: in order to speed up the code, it would be much faster to have specialized register allocator functions for some common argument patterns */ - tcg_reg_alloc_op(s, def, opc, op->args, arg_life); + tcg_reg_alloc_op(s, op); break; } #ifdef CONFIG_DEBUG_TCG --=20 2.13.6