From nobody Tue Feb 10 22:17:36 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507913183798775.7603044831711; Fri, 13 Oct 2017 09:46:23 -0700 (PDT) Received: from localhost ([::1]:51143 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e336I-0003Zj-2c for importer@patchew.org; Fri, 13 Oct 2017 12:46:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44100) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32se-0000e6-4e for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e32sa-0002JA-H9 for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:12 -0400 Received: from mail-wr0-x236.google.com ([2a00:1450:400c:c0c::236]:46156) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e32sa-0002II-6p for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:08 -0400 Received: by mail-wr0-x236.google.com with SMTP id l1so1446091wrc.3 for ; Fri, 13 Oct 2017 09:32:08 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id b11sm2508099wrd.91.2017.10.13.09.32.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:32:03 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 311863E103D; Fri, 13 Oct 2017 17:24:40 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eDKJf8QoZFlvtHit/EDPGrTfxs9RO/NiARjDvgLSZdE=; b=EemdC4eIlKD+6KHgvzwaXiLCzXqL1GZz2zmKR93jFffTBYbUN29ycJuHBz/APy5NhZ cYPbSjK/WU2byPsXNSfHMWaWCY7bZWpsIOgKUdn5+xqtzzvnQsdgsfMR7zT+WHe+QyFN 4kWlf9ehCry12IoNajRpWVWNMf8534Fj2llG8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eDKJf8QoZFlvtHit/EDPGrTfxs9RO/NiARjDvgLSZdE=; b=CkxrO+ocpQbV8HwXm04pJrIaKDQiJAToZmCvl8Ux/7NDfvsPblnLsDLeJFFveXiQcf eu+wU+fe17KsJ69gGaVr2mQFS2p6MPubMhlmZGG/XJyWDsUFaIem3kH7hCpclO3LG+LC LdMFZg8fhWKqcECOPVU7XQBRIwEchoVX1WFrhixSS4mjle09SS4m7HDp2/ABJYQgY7k3 jYYLtKejQU6WBcVn0kIx68M+hGwtPc5asK1gQupydXhExkeHq2VbKMk9pphD51CoGcRZ 5yOXAcLfUnbR6r0pv2TmQ5gpFiBTyME+8PslIIu8XUHhSwkjjnnWHNrzu9Bl+87IdM7B h3TQ== X-Gm-Message-State: AMCzsaXRzWYWelIJhhrMSijOmf/6DYIsCN7liXWCVSnVTDzFhnFq+P/s SS97iewLr4zgaUQHDMO16s3YEA== X-Google-Smtp-Source: AOwi7QCQCZO9DxeV9RPuJKZoGePElDfk5SZCXqPu1keiS5qC6MkWT/7GkOsz967weafGgbHqiTdPPg== X-Received: by 10.223.186.20 with SMTP id o20mr2221573wrg.3.1507912327116; Fri, 13 Oct 2017 09:32:07 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:32 +0100 Message-Id: <20171013162438.32458-25-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::236 Subject: [Qemu-devel] [RFC PATCH 24/30] disas_simd_indexed: support half-precision operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 A mild re-factoring of the !is_double leg to gracefully handle both single and half-precision operations. Signed-off-by: Alex Benn=C3=A9e --- target/arm/helper-a64.c | 6 ++++++ target/arm/helper-a64.h | 1 + target/arm/translate-a64.c | 19 +++++++++++++------ 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 137866732d..241fee9d93 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -578,6 +578,12 @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, vo= id *fpstp) return float16_mul(a, b, fpst); } =20 +/* fused multiply-accumulate */ +float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fps= tp) +{ + float_status *fpst =3D fpstp; + return float16_muladd(a, b, c, 0, fpst); +} =20 /* * Floating point comparisons produce an integer result. diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 66c4062ea5..444d046500 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -53,6 +53,7 @@ DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) +DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4ad470d9e8..142b23abb5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10757,7 +10757,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) TCGV_UNUSED_PTR(fpst); } =20 - if (size =3D=3D 3) { + if (size =3D=3D MO_64) { TCGv_i64 tcg_idx =3D tcg_temp_new_i64(); int pass; =20 @@ -10802,11 +10802,12 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) =20 tcg_temp_free_i64(tcg_idx); } else if (!is_long) { - /* 32 bit floating point, or 16 or 32 bit integer. + /* 16 or 32 bit floating point, or 16 or 32 bit integer. * For the 16 bit scalar case we use the usual Neon helpers and * rely on the fact that 0 op 0 =3D=3D 0 with no side effects. */ TCGv_i32 tcg_idx =3D tcg_temp_new_i32(); + bool hp =3D (size =3D=3D MO_16 ? true : false); int pass, maxpasses; =20 if (is_scalar) { @@ -10829,7 +10830,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) TCGv_i32 tcg_op =3D tcg_temp_new_i32(); TCGv_i32 tcg_res =3D tcg_temp_new_i32(); =20 - read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : M= O_32); + read_vec_element_i32(s, tcg_op, rn, pass, size); =20 switch (opcode) { case 0x0: /* MLA */ @@ -10861,8 +10862,14 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) gen_helper_vfp_negs(tcg_op, tcg_op); /* fall through */ case 0x1: /* FMLA */ - read_vec_element_i32(s, tcg_res, rd, pass, MO_32); - gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, = fpst); + read_vec_element_i32(s, tcg_res, rd, pass, size); + if (hp) { + gen_helper_advsimd_muladdh(tcg_res, tcg_op, + tcg_idx, tcg_res, fpst); + } else { + gen_helper_vfp_muladds(tcg_res, tcg_op, + tcg_idx, tcg_res, fpst); + } break; case 0x9: /* FMUL, FMULX */ switch (size) { @@ -10909,7 +10916,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) if (is_scalar) { write_fp_sreg(s, rd, tcg_res); } else { - write_vec_element_i32(s, tcg_res, rd, pass, MO_32); + write_vec_element_i32(s, tcg_res, rd, pass, size); } =20 tcg_temp_free_i32(tcg_op); --=20 2.14.1