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X-Received-From: 2a00:1450:400c:c0c::236 Subject: [Qemu-devel] [RFC PATCH 20/30] softfloat: half-precision compare functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This is mostly a mechanical conversion of the float32 variants of the same name with some judicious search/replace and some constants changed. Signed-off-by: Alex Benn=C3=A9e --- fpu/softfloat.c | 216 ++++++++++++++++++++++++++++++++++++++++++++= ++++ include/fpu/softfloat.h | 8 ++ 2 files changed, 224 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ff967f5525..fdb2999c41 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3884,6 +3884,222 @@ float16 float16_div(float16 a, float16 b, float_sta= tus *status) =20 } =20 +/*------------------------------------------------------------------------= ---- +| Returns 1 if the half-precision floating-point value `a' is equal to +| the corresponding value `b', and 0 otherwise. The invalid exception is +| raised if either operand is a NaN. Otherwise, the comparison is perform= ed +| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*-------------------------------------------------------------------------= ---*/ + +int float16_eq(float16 a, float16 b, float_status *status) +{ + uint32_t av, bv; + a =3D float16_squash_input_denormal(a, status); + b =3D float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) =3D=3D 0x1F ) && extractFloat16Frac= ( a ) ) + || ( ( extractFloat16Exp( b ) =3D=3D 0x1F ) && extractFloat16Frac= ( b ) ) + ) { + float_raise(float_flag_invalid, status); + return 0; + } + av =3D float16_val(a); + bv =3D float16_val(b); + return ( av =3D=3D bv ) || ( (uint32_t) ( ( av | bv )<<1 ) =3D=3D 0 ); +} + +/*------------------------------------------------------------------------= ---- +| Returns 1 if the half-precision floating-point value `a' is less than +| or equal to the corresponding value `b', and 0 otherwise. The invalid +| exception is raised if either operand is a NaN. The comparison is perfo= rmed +| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*-------------------------------------------------------------------------= ---*/ + +int float16_le(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + uint32_t av, bv; + a =3D float16_squash_input_denormal(a, status); + b =3D float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) =3D=3D 0x1F ) && extractFloat16Frac= ( a ) ) + || ( ( extractFloat16Exp( b ) =3D=3D 0x1F ) && extractFloat16Frac= ( b ) ) + ) { + float_raise(float_flag_invalid, status); + return 0; + } + aSign =3D extractFloat16Sign( a ); + bSign =3D extractFloat16Sign( b ); + av =3D float16_val(a); + bv =3D float16_val(b); + if ( aSign !=3D bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 = ) =3D=3D 0 ); + return ( av =3D=3D bv ) || ( aSign ^ ( av < bv ) ); + +} + +/*------------------------------------------------------------------------= ---- +| Returns 1 if the half-precision floating-point value `a' is less than +| the corresponding value `b', and 0 otherwise. The invalid exception is +| raised if either operand is a NaN. The comparison is performed according +| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*-------------------------------------------------------------------------= ---*/ + +int float16_lt(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + uint32_t av, bv; + a =3D float16_squash_input_denormal(a, status); + b =3D float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) =3D=3D 0x1F ) && extractFloat16Frac= ( a ) ) + || ( ( extractFloat16Exp( b ) =3D=3D 0x1F ) && extractFloat16Frac= ( b ) ) + ) { + float_raise(float_flag_invalid, status); + return 0; + } + aSign =3D extractFloat16Sign( a ); + bSign =3D extractFloat16Sign( b ); + av =3D float16_val(a); + bv =3D float16_val(b); + if ( aSign !=3D bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 = ) !=3D 0 ); + return ( av !=3D bv ) && ( aSign ^ ( av < bv ) ); + +} + +/*------------------------------------------------------------------------= ---- +| Returns 1 if the half-precision floating-point values `a' and `b' cannot +| be compared, and 0 otherwise. The invalid exception is raised if either +| operand is a NaN. The comparison is performed according to the IEC/IEEE +| Standard for Binary Floating-Point Arithmetic. +*-------------------------------------------------------------------------= ---*/ + +int float16_unordered(float16 a, float16 b, float_status *status) +{ + a =3D float16_squash_input_denormal(a, status); + b =3D float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) =3D=3D 0x1F ) && extractFloat16Frac= ( a ) ) + || ( ( extractFloat16Exp( b ) =3D=3D 0x1F ) && extractFloat16Frac= ( b ) ) + ) { + float_raise(float_flag_invalid, status); + return 1; + } + return 0; +} + +/*------------------------------------------------------------------------= ---- +| Returns 1 if the half-precision floating-point value `a' is equal to +| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an +| exception. The comparison is performed according to the IEC/IEEE Standa= rd +| for Binary Floating-Point Arithmetic. +*-------------------------------------------------------------------------= ---*/ + +int float16_eq_quiet(float16 a, float16 b, float_status *status) +{ + a =3D float16_squash_input_denormal(a, status); + b =3D float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) =3D=3D 0x1F ) && extractFloat16Frac= ( a ) ) + || ( ( extractFloat16Exp( b ) =3D=3D 0x1F ) && extractFloat16Frac= ( b ) ) + ) { + if (float16_is_signaling_nan(a, status) + || float16_is_signaling_nan(b, status)) { + float_raise(float_flag_invalid, status); + } + return 0; + } + return ( float16_val(a) =3D=3D float16_val(b) ) || + ( (uint32_t) ( ( float16_val(a) | float16_val(b) )<<1 ) =3D=3D= 0 ); +} + +/*------------------------------------------------------------------------= ---- +| Returns 1 if the half-precision floating-point value `a' is less than or +| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not +| cause an exception. Otherwise, the comparison is performed according to= the +| IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*-------------------------------------------------------------------------= ---*/ + +int float16_le_quiet(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + uint32_t av, bv; + a =3D float16_squash_input_denormal(a, status); + b =3D float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) =3D=3D 0x1F ) && extractFloat16Frac= ( a ) ) + || ( ( extractFloat16Exp( b ) =3D=3D 0x1F ) && extractFloat16Frac= ( b ) ) + ) { + if (float16_is_signaling_nan(a, status) + || float16_is_signaling_nan(b, status)) { + float_raise(float_flag_invalid, status); + } + return 0; + } + aSign =3D extractFloat16Sign( a ); + bSign =3D extractFloat16Sign( b ); + av =3D float16_val(a); + bv =3D float16_val(b); + if ( aSign !=3D bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 = ) =3D=3D 0 ); + return ( av =3D=3D bv ) || ( aSign ^ ( av < bv ) ); + +} + +/*------------------------------------------------------------------------= ---- +| Returns 1 if the half-precision floating-point value `a' is less than +| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an +| exception. Otherwise, the comparison is performed according to the IEC/= IEEE +| Standard for Binary Floating-Point Arithmetic. +*-------------------------------------------------------------------------= ---*/ + +int float16_lt_quiet(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + uint32_t av, bv; + a =3D float16_squash_input_denormal(a, status); + b =3D float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) =3D=3D 0x1F ) && extractFloat16Frac= ( a ) ) + || ( ( extractFloat16Exp( b ) =3D=3D 0x1F ) && extractFloat16Frac= ( b ) ) + ) { + if (float16_is_signaling_nan(a, status) + || float16_is_signaling_nan(b, status)) { + float_raise(float_flag_invalid, status); + } + return 0; + } + aSign =3D extractFloat16Sign( a ); + bSign =3D extractFloat16Sign( b ); + av =3D float16_val(a); + bv =3D float16_val(b); + if ( aSign !=3D bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 = ) !=3D 0 ); + return ( av !=3D bv ) && ( aSign ^ ( av < bv ) ); + +} + +/*------------------------------------------------------------------------= ---- +| Returns 1 if the half-precision floating-point values `a' and `b' cannot +| be compared, and 0 otherwise. Quiet NaNs do not cause an exception. The +| comparison is performed according to the IEC/IEEE Standard for Binary +| Floating-Point Arithmetic. +*-------------------------------------------------------------------------= ---*/ + +int float16_unordered_quiet(float16 a, float16 b, float_status *status) +{ + a =3D float16_squash_input_denormal(a, status); + b =3D float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) =3D=3D 0x1F ) && extractFloat16Frac= ( a ) ) + || ( ( extractFloat16Exp( b ) =3D=3D 0x1F ) && extractFloat16Frac= ( b ) ) + ) { + if (float16_is_signaling_nan(a, status) + || float16_is_signaling_nan(b, status)) { + float_raise(float_flag_invalid, status); + } + return 1; + } + return 0; +} + /* Half precision floats come in two formats: standard IEEE and "ARM" form= at. The latter gains extra exponent range by omitting the NaN/Inf encodings= . */ =20 diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index f1d79b6d03..76a8310780 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -350,6 +350,14 @@ float16 float16_add(float16, float16, float_status *st= atus); float16 float16_sub(float16, float16, float_status *status); float16 float16_mul(float16, float16, float_status *status); float16 float16_div(float16, float16, float_status *status); +int float16_eq(float16, float16, float_status *status); +int float16_le(float16, float16, float_status *status); +int float16_lt(float16, float16, float_status *status); +int float16_unordered(float16, float16, float_status *status); +int float16_eq_quiet(float16, float16, float_status *status); +int float16_le_quiet(float16, float16, float_status *status); +int float16_lt_quiet(float16, float16, float_status *status); +int float16_unordered_quiet(float16, float16, float_status *status); =20 int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); --=20 2.14.1