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X-Received-From: 2a00:1450:400c:c09::236 Subject: [Qemu-devel] [RFC PATCH 14/30] softfloat: 16 bit helpers for shr, clz and rounding and packing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Half-precision helpers for float16 maths. I didn't bother hand-coding the count leading zeros as we could always fall-back to host-utils if we needed to. Signed-off-by: Alex Benn=C3=A9e --- fpu/softfloat-macros.h | 39 +++++++++++++++++++++++++++++++++++++++ fpu/softfloat.c | 21 +++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/fpu/softfloat-macros.h b/fpu/softfloat-macros.h index 9cc6158cb4..73091a88a8 100644 --- a/fpu/softfloat-macros.h +++ b/fpu/softfloat-macros.h @@ -89,6 +89,31 @@ this code that are retained. # define SOFTFLOAT_GNUC_PREREQ(maj, min) 0 #endif =20 +/*------------------------------------------------------------------------= ---- +| Shifts `a' right by the number of bits given in `count'. If any nonzero +| bits are shifted off, they are ``jammed'' into the least significant bit= of +| the result by setting the least significant bit to 1. The value of `cou= nt' +| can be arbitrarily large; in particular, if `count' is greater than 16, = the +| result will be either 0 or 1, depending on whether `a' is zero or nonzer= o. +| The result is stored in the location pointed to by `zPtr'. +*-------------------------------------------------------------------------= ---*/ + +static inline void shift16RightJamming(uint16_t a, int count, uint16_t *zP= tr) +{ + uint16_t z; + + if ( count =3D=3D 0 ) { + z =3D a; + } + else if ( count < 16 ) { + z =3D ( a>>count ) | ( ( a<<( ( - count ) & 16 ) ) !=3D 0 ); + } + else { + z =3D ( a !=3D 0 ); + } + *zPtr =3D z; + +} =20 /*------------------------------------------------------------------------= ---- | Shifts `a' right by the number of bits given in `count'. If any nonzero @@ -664,6 +689,20 @@ static uint32_t estimateSqrt32(int aExp, uint32_t a) =20 } =20 +/*------------------------------------------------------------------------= ---- +| Returns the number of leading 0 bits before the most-significant 1 bit of +| `a'. If `a' is zero, 16 is returned. +*-------------------------------------------------------------------------= ---*/ + +static int8_t countLeadingZeros16( uint16_t a ) +{ + if (a) { + return __builtin_clz(a); + } else { + return 16; + } +} + /*------------------------------------------------------------------------= ---- | Returns the number of leading 0 bits before the most-significant 1 bit of | `a'. If `a' is zero, 32 is returned. diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6ab4b39c09..cf7bf6d4f4 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3488,6 +3488,27 @@ static float16 roundAndPackFloat16(flag zSign, int z= Exp, return packFloat16(zSign, zExp, zSig >> 13); } =20 +/*------------------------------------------------------------------------= ---- +| Takes an abstract floating-point value having sign `zSign', exponent `zE= xp', +| and significand `zSig', and returns the proper single-precision floating- +| point value corresponding to the abstract input. This routine is just l= ike +| `roundAndPackFloat32' except that `zSig' does not have to be normalized. +| Bit 15 of `zSig' must be zero, and `zExp' must be 1 less than the ``true= '' +| floating-point exponent. +*-------------------------------------------------------------------------= ---*/ + +static float16 + normalizeRoundAndPackFloat16(flag zSign, int zExp, uint16_t zSig, + float_status *status) +{ + int8_t shiftCount; + + shiftCount =3D countLeadingZeros16( zSig ) - 1; + return roundAndPackFloat16(zSign, zExp - shiftCount, zSig<