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[61.45.56.248]) by smtp.gmail.com with ESMTPSA id w10sm2593183pfg.40.2017.10.13.06.49.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 13 Oct 2017 06:49:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kQUr+jn02nx+3PZWPpNj/Rt3hCdwvT79bQYlRXSXpjk=; b=WKJxisSBAkQMHVePD8ilPvf0jqD8ieZppKLkvBPxGAgRJBxjW34GnOz37Fng1uBhAg dK5j3N7iz7BnWBwl0NVAcxCGAg96Yzg8gxPXDneLgJagMOh7ubuJnSXOFyGdPw+FwsvB 27KJJvLAEnFB/kcVA+MjC1QgzN/rfU/KiZJ/tCjewElRIysqUcCwjpjdBZG/6zUXqsLC tt5oGmsHClfCYLSRdfNF1ir4WCokN669YzDLcJWjst/OL15IrxhwdlyAbVSHyjUbXrDq lsQTa+wtnWcYqtlAesHsmMopJcthn61Xqz98TmwX3shK+FLoyFzQbgO8xzjjKZsB/WO5 fJAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kQUr+jn02nx+3PZWPpNj/Rt3hCdwvT79bQYlRXSXpjk=; b=tg754NuApf1WZ2ZI+mkatpWDNVOCRLPa1yDeOoMf6Ney96yeplXAMOfUkVs/UT+oir HFA2/65xRulknvi/RMjAWqL5eZ64UTCSmSJY7HxIDXFuOf5bXcxXHehJAqaCn0qep9Zo uHkoM+yJfVcnro1/ySNaQWD4eQrqNql7hImnZEi6jDRtnJMm6vXusRrfAxP/aj8jEG0N ViiJJ57c7RJ8tx49lKDV85wkePY64XbqND1EwjNFP4c1VtrSOM8i2miNpSm+PyUSbFfh YsLKX9DLXXIiotUuC1UgIIufO96ELZjjUgJGHds4A36GkbLFyaWf99kjKFXQCzqd8+43 cpfQ== X-Gm-Message-State: AMCzsaUEOvUzEp7DXRWX4kow0llwa3HE4evwFOz0K93YZz0jq8gh9wgW OqPiAYk1F47dXkjOv2nMMRaZXJ4v X-Google-Smtp-Source: AOwi7QBaCgtaG0q8nnVPzoFOilIYSiR34lsAgDMjtLjt+nhfQouUZFaO6/GgTO1bzOV6HIHhZdu4uQ== X-Received: by 10.99.182.66 with SMTP id v2mr1397345pgt.325.1507902599571; Fri, 13 Oct 2017 06:49:59 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Fri, 13 Oct 2017 22:49:29 +0900 Message-Id: <20171013134930.32547-5-shorne@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171013134930.32547-1-shorne@gmail.com> References: <20171013134930.32547-1-shorne@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH v2 4/5] openrisc: Initial SMP support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , Richard Henderson , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Wire in ompic and add basic support for SMP. The OpenRISC is special in that interrupts for devices are routed to each core's PIC. This is achieved using the qemu_irq_split utility, but this currently limits OpenRISC to 2 cores. This models the reference architecture described in the OpenRISC spec 1.2 proposal. https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-= rev0.pdf The changes to the intialization of the sim include: CPU Reset o Reset each cpu to the bootstrap PC rather than only a single cpu as done before. o During Kernel loading the bootstrap PC is saved in a static global. Network Initialization o Connect the interrupt to each CPU o Use more simple sysbus_mmio_map() rather than memory_region_add_subregio= n() Sim Initialization o Initialize the pic and tick timer per cpu o Wire in the OMPIC if SMP is enabled o Wire the serial irq to each CPU using qemu_irq_split() Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- hw/openrisc/openrisc_sim.c | 84 +++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 61 insertions(+), 23 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index e1eeffc490..1794c39005 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -35,36 +35,60 @@ =20 #define KERNEL_LOAD_ADDR 0x100 =20 +static struct openrisc_boot_info { + uint32_t bootstrap_pc; +} boot_info; + static void main_cpu_reset(void *opaque) { OpenRISCCPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); =20 cpu_reset(CPU(cpu)); + + cpu_set_pc(cs, boot_info.bootstrap_pc); } =20 -static void openrisc_sim_net_init(MemoryRegion *address_space, - hwaddr base, - hwaddr descriptors, - qemu_irq irq, NICInfo *nd) +static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, + int num_cpus, qemu_irq **cpu_irqs, + int irq_pin, NICInfo *nd) { DeviceState *dev; SysBusDevice *s; + int i; =20 dev =3D qdev_create(NULL, "open_eth"); qdev_set_nic_properties(dev, nd); qdev_init_nofail(dev); =20 s =3D SYS_BUS_DEVICE(dev); - sysbus_connect_irq(s, 0, irq); - memory_region_add_subregion(address_space, base, - sysbus_mmio_get_region(s, 0)); - memory_region_add_subregion(address_space, descriptors, - sysbus_mmio_get_region(s, 1)); + for (i =3D 0; i < num_cpus; i++) { + sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]); + } + sysbus_mmio_map(s, 0, base); + sysbus_mmio_map(s, 1, descriptors); } =20 -static void cpu_openrisc_load_kernel(ram_addr_t ram_size, - const char *kernel_filename, - OpenRISCCPU *cpu) +static void openrisc_sim_ompic_init(hwaddr base, int num_cpus, + qemu_irq **cpu_irqs, int irq_pin) +{ + DeviceState *dev; + SysBusDevice *s; + int i; + + dev =3D qdev_create(NULL, "or1k-ompic"); + qdev_prop_set_uint32(dev, "num-cpus", num_cpus); + qdev_init_nofail(dev); + + s =3D SYS_BUS_DEVICE(dev); + for (i =3D 0; i < num_cpus; i++) { + sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]); + } + sysbus_mmio_map(s, 0, base); +} + +static void openrisc_load_kernel(ram_addr_t ram_size, + const char *kernel_filename) { long kernel_size; uint64_t elf_entry; @@ -83,6 +107,9 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size, kernel_size =3D load_image_targphys(kernel_filename, KERNEL_LOAD_ADDR, ram_size - KERNEL_LOAD_ADDR); + } + + if (entry <=3D 0) { entry =3D KERNEL_LOAD_ADDR; } =20 @@ -91,7 +118,7 @@ static void cpu_openrisc_load_kernel(ram_addr_t ram_size, kernel_filename); exit(1); } - cpu->env.pc =3D entry; + boot_info.bootstrap_pc =3D entry; } } =20 @@ -102,6 +129,8 @@ static void openrisc_sim_init(MachineState *machine) const char *kernel_filename =3D machine->kernel_filename; OpenRISCCPU *cpu =3D NULL; MemoryRegion *ram; + qemu_irq *cpu_irqs[2]; + qemu_irq serial_irq; int n; =20 if (!cpu_model) { @@ -114,33 +143,42 @@ static void openrisc_sim_init(MachineState *machine) fprintf(stderr, "Unable to find CPU definition!\n"); exit(1); } + cpu_openrisc_pic_init(cpu); + cpu_irqs[n] =3D (qemu_irq *) cpu->env.irq; + + cpu_openrisc_clock_init(cpu); + qemu_register_reset(main_cpu_reset, cpu); - main_cpu_reset(cpu); } =20 ram =3D g_malloc(sizeof(*ram)); memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fat= al); memory_region_add_subregion(get_system_memory(), 0, ram); =20 - cpu_openrisc_pic_init(cpu); - cpu_openrisc_clock_init(cpu); + if (nd_table[0].used) { + openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus, + cpu_irqs, 4, nd_table); + } =20 - serial_mm_init(get_system_memory(), 0x90000000, 0, cpu->env.irq[2], - 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); + if (smp_cpus > 1) { + openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1); =20 - if (nd_table[0].used) { - openrisc_sim_net_init(get_system_memory(), 0x92000000, - 0x92000400, cpu->env.irq[4], nd_table); + serial_irq =3D qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]); + } else { + serial_irq =3D cpu_irqs[0][2]; } =20 - cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu); + serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq, + 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); + + openrisc_load_kernel(ram_size, kernel_filename); } =20 static void openrisc_sim_machine_init(MachineClass *mc) { mc->desc =3D "or1k simulation"; mc->init =3D openrisc_sim_init; - mc->max_cpus =3D 1; + mc->max_cpus =3D 2; mc->is_default =3D 1; } =20 --=20 2.13.6