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[61.45.56.248]) by smtp.gmail.com with ESMTPSA id b23sm4818320pfm.148.2017.10.13.06.49.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 13 Oct 2017 06:49:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BJOdWCY/Yh6knPz1kisg20o/ROj7u9D1prc6ivvtUB4=; b=jYphYcCwg6qlLmNrirmH3G8H4Bo+wRiFSjL2ZsZ0aeNASeuSVKBvP6plHVUHG5DJM5 L9bC3lQmqgdjzBO2b7BNUbrz4eOwMMU096YBqKXZH3oBscRLANVDAoyCVlyCV7Nf3CmD mca+neTAaSK1tlx2UZGTRL6K0OprRl/r77ZdqWxFqG6j1wwlKIiwwkp4hzlhYTnbZ6Y4 LQMa3I3fga/DMwh53rRTLrmWJkByiZNTJf4PACSUXg1Ih0hlQu7/62zKCDpx2Xe01lsZ 2FD3Y5jw/bZT24NqTvrZlDleJDcTER7G7fIqdgKVLl7lXCiL5f6/uU3kX3VVbhT3OWKH FU+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BJOdWCY/Yh6knPz1kisg20o/ROj7u9D1prc6ivvtUB4=; b=Q/8XDbHpCFtSMZoYAFK3OkJb2hD292b5ap0hCYcdNPjwskngaQhlEMV0tWtAs9m2jQ a+wsyhSMCL+nN/vgwfYgMMjreQ+nciedKaJAcox+4hKuFqiSqFZ2GcCiV3jVc+FlGLBF ipLkV6jT9S+0+6BUl8VzKKXdUi1pbQ8dEfL995T4+z8TlBNaNcS6mmSluRApKEdRh/Bg GBIRkGa4+ZmECE2pV3j5CGCXG4Xs8Qm2BmQRibpAluzFp052/hXm0ECMEPAEY8Q4P81X 2Cf8tMx0EWJpRxBVsrqtU3DFTCSa1AjjA/rqVprr+eBWRr6rnL9dWxwSIUNuXfr2y6E+ SOaw== X-Gm-Message-State: AMCzsaXokU3U0mDdx01nhA30u+DUyByeqCStagVjQZE14d/9OcJBzgbo Lw3USxipLvC+VSAgjVYQXZkTcIyQ X-Google-Smtp-Source: AOwi7QAcPIx+1U1+HJpXjn2yVHmzYyBvyLIYMMqZW/CU5OJ3xGuv0g4PtRHi+Ob4t5u9K+/Ogu7ZeQ== X-Received: by 10.99.64.1 with SMTP id n1mr1380892pga.185.1507902596687; Fri, 13 Oct 2017 06:49:56 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Fri, 13 Oct 2017 22:49:28 +0900 Message-Id: <20171013134930.32547-4-shorne@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171013134930.32547-1-shorne@gmail.com> References: <20171013134930.32547-1-shorne@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH v2 3/5] openrisc/cputimer: Perparation for Multicore X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , Openrisc , Richard Henderson , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In order to support multicore system we move some of the previously static state variables into the state of each core. On the other hand in order to allow timers to be synced between each code the ttcr (tick timer count register) is moved out of the core. This is not as per real hardware spec which has a separate timer counter per core, but it seems the most simple way to keep each clock in sync. Reviewed-by: Richard Henderson Signed-off-by: Stafford Horne --- hw/openrisc/cputimer.c | 62 +++++++++++++++++++++++++++++++++-------= ---- target/openrisc/cpu.c | 1 - target/openrisc/cpu.h | 4 ++- target/openrisc/machine.c | 1 - target/openrisc/sys_helper.c | 4 +-- 5 files changed, 52 insertions(+), 20 deletions(-) diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c index febc469170..4c5415ff75 100644 --- a/hw/openrisc/cputimer.c +++ b/hw/openrisc/cputimer.c @@ -25,39 +25,56 @@ =20 #define TIMER_PERIOD 50 /* 50 ns period for 20 MHz timer */ =20 -/* The time when TTCR changes */ -static uint64_t last_clk; -static int is_counting; +/* Tick Timer global state to allow all cores to be in sync */ +typedef struct OR1KTimerState { + uint32_t ttcr; + uint64_t last_clk; +} OR1KTimerState; =20 +static OR1KTimerState *or1k_timer; + +void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val) +{ + or1k_timer->ttcr =3D val; +} + +uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu) +{ + return or1k_timer->ttcr; +} + +/* Add elapsed ticks to ttcr */ void cpu_openrisc_count_update(OpenRISCCPU *cpu) { uint64_t now; =20 - if (!is_counting) { + if (!cpu->env.is_counting) { return; } now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - cpu->env.ttcr +=3D (uint32_t)((now - last_clk) / TIMER_PERIOD); - last_clk =3D now; + or1k_timer->ttcr +=3D (uint32_t)((now - or1k_timer->last_clk) + / TIMER_PERIOD); + or1k_timer->last_clk =3D now; } =20 +/* Update the next timeout time as difference between ttmr and ttcr */ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) { uint32_t wait; uint64_t now, next; =20 - if (!is_counting) { + if (!cpu->env.is_counting) { return; } =20 cpu_openrisc_count_update(cpu); - now =3D last_clk; + now =3D or1k_timer->last_clk; =20 - if ((cpu->env.ttmr & TTMR_TP) <=3D (cpu->env.ttcr & TTMR_TP)) { - wait =3D TTMR_TP - (cpu->env.ttcr & TTMR_TP) + 1; + if ((cpu->env.ttmr & TTMR_TP) <=3D (or1k_timer->ttcr & TTMR_TP)) { + wait =3D TTMR_TP - (or1k_timer->ttcr & TTMR_TP) + 1; wait +=3D cpu->env.ttmr & TTMR_TP; } else { - wait =3D (cpu->env.ttmr & TTMR_TP) - (cpu->env.ttcr & TTMR_TP); + wait =3D (cpu->env.ttmr & TTMR_TP) - (or1k_timer->ttcr & TTMR_TP); } next =3D now + (uint64_t)wait * TIMER_PERIOD; timer_mod(cpu->env.timer, next); @@ -66,7 +83,7 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu) =20 void cpu_openrisc_count_start(OpenRISCCPU *cpu) { - is_counting =3D 1; + cpu->env.is_counting =3D 1; cpu_openrisc_count_update(cpu); } =20 @@ -74,7 +91,7 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu) { timer_del(cpu->env.timer); cpu_openrisc_count_update(cpu); - is_counting =3D 0; + cpu->env.is_counting =3D 0; } =20 static void openrisc_timer_cb(void *opaque) @@ -93,7 +110,7 @@ static void openrisc_timer_cb(void *opaque) case TIMER_NONE: break; case TIMER_INTR: - cpu->env.ttcr =3D 0; + or1k_timer->ttcr =3D 0; break; case TIMER_SHOT: cpu_openrisc_count_stop(cpu); @@ -105,9 +122,24 @@ static void openrisc_timer_cb(void *opaque) cpu_openrisc_timer_update(cpu); } =20 +static const VMStateDescription vmstate_or1k_timer =3D { + .name =3D "or1k_timer", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(ttcr, OR1KTimerState), + VMSTATE_UINT64(last_clk, OR1KTimerState), + VMSTATE_END_OF_LIST() + } +}; + void cpu_openrisc_clock_init(OpenRISCCPU *cpu) { cpu->env.timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb= , cpu); cpu->env.ttmr =3D 0x00000000; - cpu->env.ttcr =3D 0x00000000; + + if (or1k_timer =3D=3D NULL) { + or1k_timer =3D g_new0(OR1KTimerState, 1); + vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer); + } } diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 1d6330cbcc..0a46684987 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -61,7 +61,6 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.picsr =3D 0x00000000; =20 cpu->env.ttmr =3D 0x00000000; - cpu->env.ttcr =3D 0x00000000; #endif } =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 2721432c4f..3608cbad69 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -315,7 +315,7 @@ typedef struct CPUOpenRISCState { =20 QEMUTimer *timer; uint32_t ttmr; /* Timer tick mode register */ - uint32_t ttcr; /* Timer tick count register */ + int is_counting; =20 uint32_t picmr; /* Interrupt mask register */ uint32_t picsr; /* Interrupt contrl register*/ @@ -373,6 +373,8 @@ void cpu_openrisc_pic_init(OpenRISCCPU *cpu); =20 /* hw/openrisc_timer.c */ void cpu_openrisc_clock_init(OpenRISCCPU *cpu); +uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu); +void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val); void cpu_openrisc_count_update(OpenRISCCPU *cpu); void cpu_openrisc_timer_update(OpenRISCCPU *cpu); void cpu_openrisc_count_start(OpenRISCCPU *cpu); diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c index a20cce705d..0a793eb14d 100644 --- a/target/openrisc/machine.c +++ b/target/openrisc/machine.c @@ -147,7 +147,6 @@ static const VMStateDescription vmstate_env =3D { =20 VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), VMSTATE_UINT32(ttmr, CPUOpenRISCState), - VMSTATE_UINT32(ttcr, CPUOpenRISCState), =20 VMSTATE_UINT32(picmr, CPUOpenRISCState), VMSTATE_UINT32(picsr, CPUOpenRISCState), diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index dc6e5cc7f2..9fb7d86b4b 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -189,7 +189,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, break; =20 case TO_SPR(10, 1): /* TTCR */ - env->ttcr =3D rb; + cpu_openrisc_count_set(cpu, rb); if (env->ttmr & TIMER_NONE) { return; } @@ -312,7 +312,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, =20 case TO_SPR(10, 1): /* TTCR */ cpu_openrisc_count_update(cpu); - return env->ttcr; + return cpu_openrisc_count_get(cpu); =20 default: break; --=20 2.13.6