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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qsfB70w9CzKDOcAWwewK8f/2coAK2gFW2Q5mox1wx5o=; b=A9Kdb1Yf+xTa2xJ+b/cGi51WEEpMQLNOtvQSHdbEujCwm+cwQTDSTaz/ehyVAsvi3O d9j9HeSUuwT84Wkxveesaoe5K2nG4y9hiAHYB/m21c4RkTA/Sy0QAZWGtfoRWOJfNUTW 4PzCq3RHNeroxFU36TuZSY6pJri2Jg8D6UZhc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qsfB70w9CzKDOcAWwewK8f/2coAK2gFW2Q5mox1wx5o=; b=NHviW/DhpJtGufOyF2Vg/s0gTDLRk0GuYIjrXkuA/9AEu86BuAcokAgGdOJBog0QMi xtALrAnFBHYx2f8BVWLscfmOMVOWPiV6Ej1cCNoDhmOly2k9lib780FGDBhHc72FZ99S veoV+HyV3sAP4lugbgXXnphVcLlJgbean7mdKzJB/F0LmB4JiWVrz0a2KzRED6/1fNgS mlUhzCz9OSSgHomYd8oVXYyy5OHxepyehETitS5mb4m9AOLjQbV8Td78+jQJqZiRqwsL oqbDk4c6FSoL/inlFHx/TDu0+Y4LcZiHvbnmNnTHw4p2KvallwYCf8VFjmgTaCdhjnlO Uz6w== X-Gm-Message-State: AMCzsaVuiDadqjvKqr/iHDDY/88dYHAbvxNdVUPyiX3Y/za/kEgRfy0Q cPVp+WsjyZelw62m7UF4RRdy++RGm+s= X-Google-Smtp-Source: AOwi7QAbnHRyDKxhOXy/xy/VqeiCoK1I2ylNaQ7MZhCunFB7Pu7Z8YFZKaKWe4Ms7OdGpH4bk8vLWg== X-Received: by 10.98.54.194 with SMTP id d185mr14645738pfa.70.1507663807413; Tue, 10 Oct 2017 12:30:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:29:44 -0700 Message-Id: <20171010193003.28857-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::231 Subject: [Qemu-devel] [PULL v2 01/20] cputlb: bring back tlb_flush_count under !TLB_DEBUG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Commit f0aff0f124 ("cputlb: add assert_cpu_is_self checks") buried the increment of tlb_flush_count under TLB_DEBUG. This results in "info jit" always (mis)reporting 0 TLB flushes when !TLB_DEBUG. Besides, under MTTCG tlb_flush_count is updated by several threads, so in order not to lose counts we'd either have to use atomic ops or distribute the counter, which is more scalable. This patch does the latter by embedding tlb_flush_count in CPUArchState. The global count is then easily obtained by iterating over the CPU list. Note that this change also requires updating the accessors to tlb_flush_count to use atomic_read/set whenever there may be conflicting accesses (as defined in C11) to it. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 1 + include/exec/cputlb.h | 3 +-- accel/tcg/cputlb.c | 17 ++++++++++++++--- accel/tcg/translate-all.c | 2 +- 4 files changed, 17 insertions(+), 6 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bc8e7f848d..e43ff8346b 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -137,6 +137,7 @@ typedef struct CPUIOTLBEntry { CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ + size_t tlb_flush_count; \ target_ulong tlb_flush_addr; \ target_ulong tlb_flush_mask; \ target_ulong vtlb_index; \ diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 3f941783c5..c91db211bc 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -23,7 +23,6 @@ /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); -extern int tlb_flush_count; - +size_t tlb_flush_count(void); #endif #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index bcbcc4db6c..5b1ef1442c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -92,8 +92,18 @@ static void flush_all_helper(CPUState *src, run_on_cpu_f= unc fn, } } =20 -/* statistics */ -int tlb_flush_count; +size_t tlb_flush_count(void) +{ + CPUState *cpu; + size_t count =3D 0; + + CPU_FOREACH(cpu) { + CPUArchState *env =3D cpu->env_ptr; + + count +=3D atomic_read(&env->tlb_flush_count); + } + return count; +} =20 /* This is OK because CPU architectures generally permit an * implementation to drop entries from the TLB at any time, so @@ -112,7 +122,8 @@ static void tlb_flush_nocheck(CPUState *cpu) } =20 assert_cpu_is_self(cpu); - tlb_debug("(count: %d)\n", tlb_flush_count++); + atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); + tlb_debug("(count: %zu)\n", tlb_flush_count()); =20 tb_lock(); =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 2d1ed06065..6b5d4bece2 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1936,7 +1936,7 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) atomic_read(&tcg_ctx.tb_ctx.tb_flush_count)); cpu_fprintf(f, "TB invalidate count %d\n", tcg_ctx.tb_ctx.tb_phys_invalidate_count); - cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); + cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count()); tcg_dump_info(f, cpu_fprintf); =20 tb_unlock(); --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507663937201344.40539433935396; Tue, 10 Oct 2017 12:32:17 -0700 (PDT) Received: from localhost ([::1]:36802 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20G4-0001hO-Jl for importer@patchew.org; Tue, 10 Oct 2017 15:32:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58733) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20EG-0000V3-Ji for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20EE-0004v2-Az for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:12 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:48756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20EE-0004ui-2U for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:10 -0400 Received: by mail-pf0-x233.google.com with SMTP id b79so5987003pfk.5 for ; Tue, 10 Oct 2017 12:30:09 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uWX8ltUJ41jzpP0mhxc6dOVFBO5YtrjkEa7vnTfdaYc=; b=hNLSzppTauUp5GpmeIAY9Zpm1R1FY3n381q7DMTOKjmyiwcidcg7JSBRFIhmx3MTpy QlcUBBbrSFlJTdrJZy19Kub4TihZQQD6KGkxgTw8F8zr9QdaFIh9Q0kSsxpahQiQL1Fm M1NOhQsWMr3k4prTfDip3qNzCALJR82dwL2wE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uWX8ltUJ41jzpP0mhxc6dOVFBO5YtrjkEa7vnTfdaYc=; b=iL6dm3aIBDIEv/A89rT3IdnuaLUNmShBkmbJjQYHMkFj+eWjYUpXSO9CGd7zXu1xKL B93gcaFqevsm+jQzia/NDrq5gs5Z0IZRvVhYTJD12byGJUCcl+va/pTsOBpWCQlgR9ZK JcnnqJRRZBwTqeNLDYYSXy26+xjLhc5P59gSAsvuHYtZFQWho8t0DU0YE2Y0OSGw244S PDetkodSH4DsjeGmNAJhXC30A13sb27A06riFeMkMJYWmzpqqlfqhBKKpZysGC5dfIKj CMQjL9BM1tX70zQl7Dvh9GQq5oEOYAD9vD9hQRb6AOqSXFnGTYgqzpRdigsp8wvfQJxm wJ2A== X-Gm-Message-State: AMCzsaWaAgn0eTjOXLpXtmIXoRerK6HF0ApUIS66CnV4i43yKoAALv3M rMV7ecFiyzP/8mhC86T7MqwJLpUuEzY= X-Google-Smtp-Source: AOwi7QBDyVx3dTSEOSWrmNeczOmzRrkXM/YmiMtjYsPiYoCP7KUjOq8I0WTMY4R/jnIW2hlzG1Mu+g== X-Received: by 10.101.90.133 with SMTP id c5mr13240549pgt.441.1507663808784; Tue, 10 Oct 2017 12:30:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:29:45 -0700 Message-Id: <20171010193003.28857-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PULL v2 02/20] tcg: fix corruption of code_time profiling counter upon tb_flush X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Whenever there is an overflow in code_gen_buffer (e.g. we run out of space in it and have to flush it), the code_time profiling counter ends up with an invalid value (that is, code_time -=3D profile_getclock(), without later on getting +=3D profile_getclock() due to the goto). Fix it by using the ti variable, so that we only update code_time when there is no overflow. Note that in case there is an overflow we fail to account for the elapsed coding time, but this is quite rare so we can probably live with it. "info jit" before/after, roughly at the same time during debian-arm bootup: - before: Statistics: TB flush count 1 TB invalidate count 4665 TLB flush count 998 JIT cycles -615191529184601 (-256329.804 s at 2.4 GHz) translated TBs 302310 (aborted=3D0 0.0%) avg ops/TB 48.4 max=3D438 deleted ops/TB 8.54 avg temps/TB 32.31 max=3D38 avg host code/TB 361.5 avg search data/TB 24.5 cycles/op -42014693.0 cycles/in byte -121444900.2 cycles/out byte -5629031.1 cycles/search byte -83114481.0 gen_interm time -0.0% gen_code time 100.0% optim./code time -0.0% liveness/code time -0.0% cpu_restore count 6236 avg cycles 110.4 - after: Statistics: TB flush count 1 TB invalidate count 4665 TLB flush count 1010 JIT cycles 1996899624 (0.832 s at 2.4 GHz) translated TBs 297961 (aborted=3D0 0.0%) avg ops/TB 48.5 max=3D438 deleted ops/TB 8.56 avg temps/TB 32.31 max=3D38 avg host code/TB 361.8 avg search data/TB 24.5 cycles/op 138.2 cycles/in byte 398.4 cycles/out byte 18.5 cycles/search byte 273.1 gen_interm time 14.0% gen_code time 86.0% optim./code time 19.4% liveness/code time 10.3% cpu_restore count 6372 avg cycles 111.0 Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 6b5d4bece2..b3bfe65059 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1300,7 +1300,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, #ifdef CONFIG_PROFILER tcg_ctx.tb_count++; tcg_ctx.interm_time +=3D profile_getclock() - ti; - tcg_ctx.code_time -=3D profile_getclock(); + ti =3D profile_getclock(); #endif =20 /* ??? Overflow could be handled better here. In particular, we @@ -1318,7 +1318,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } =20 #ifdef CONFIG_PROFILER - tcg_ctx.code_time +=3D profile_getclock(); + tcg_ctx.code_time +=3D profile_getclock() - ti; tcg_ctx.code_in_len +=3D tb->size; tcg_ctx.code_out_len +=3D gen_code_size; tcg_ctx.search_out_len +=3D search_size; --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664105693208.22193246993027; Tue, 10 Oct 2017 12:35:05 -0700 (PDT) Received: from localhost ([::1]:36810 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Is-0003tk-J6 for importer@patchew.org; Tue, 10 Oct 2017 15:34:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58731) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20EG-0000V1-J3 for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20EF-0004wk-FB for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:12 -0400 Received: from mail-pf0-x231.google.com ([2607:f8b0:400e:c00::231]:47076) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20EF-0004w9-93 for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:11 -0400 Received: by mail-pf0-x231.google.com with SMTP id p87so9224354pfj.3 for ; Tue, 10 Oct 2017 12:30:11 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7R+gio33UwF3vi2Cvaa4aXxIYtef4+3eg4MJuM1tI6k=; b=fwFmK1S54g0cU5dUflWyPvxRjIxvzpDkZ6Rz/eV0bLhjzD1Qy0fSCJEjS/MAFI03sB FTiVZUkHcn8IInhnnmxdPHl57CdcJsieftAtQsHSXyTXe0jk0lqBR18VuMjLBC+93eKI VfhAQq7DxFyb8OgVRl0CXNwI/Exxug/UIWd2Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7R+gio33UwF3vi2Cvaa4aXxIYtef4+3eg4MJuM1tI6k=; b=HOpuhzuBCyiHWYWCyd65VpTIp35HYfwYCx+2m7ohqqKK8V4enX1SzHW1qPgW6NorR4 gn8RdtwlSmKlyvndy99vx7WrxF5ogdOTEXakXy6AxX2Waf8YcT5U+GmVUP9yqF4b09SN zWIsnbDlp2tX/Ck3zkXkUVMIL20pRaM52eyjVshAF/3h9NK1Z8PGMrZCUyv6IEi5ETDO 97LbucAf8KgzZ40jIqVV5TrbGQ294/p/ZI4gRYlxPuN16zcAYQhNNi5MtfxfLputZDdo lMg+vXr7z1uUEYS98veaYxlvr828NcahE4iXEMIc6XMN2vEdciUQoKvQSJRLD01tvdKY CtNQ== X-Gm-Message-State: AMCzsaUBcgzaaGEL15r68jcQEB/pMvBYFoW5d56spcuj+97GyCNgPP71 WkmC1knil6BXVvj5hZJIKWtc0Aa+AG0= X-Google-Smtp-Source: AOwi7QCuHNCrJIU+I5Vj8MKhbFRsAxRJITjSSFA2ko0Aoap4NDU/h7MOC3i22wyszGdkZp98GhPI6Q== X-Received: by 10.99.181.25 with SMTP id y25mr13104758pge.270.1507663810047; Tue, 10 Oct 2017 12:30:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:29:46 -0700 Message-Id: <20171010193003.28857-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::231 Subject: [Qemu-devel] [PULL v2 03/20] exec-all: fix typos in TranslationBlock's documentation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 673fc066d0..a9a8bb6f83 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -332,7 +332,7 @@ struct TranslationBlock { /* The following data are used to directly call another TB from * the code of this one. This can be done either by emitting direct or * indirect native jump instructions. These jumps are reset so that th= e TB - * just continue its execution. The TB can be linked to another one by + * just continues its execution. The TB can be linked to another one by * setting one of the jump targets (or patching the jump instruction).= Only * two of such jumps are supported. */ @@ -340,7 +340,7 @@ struct TranslationBlock { #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated = */ uintptr_t jmp_target_arg[2]; /* target address or offset */ =20 - /* Each TB has an assosiated circular list of TBs jumping to this one. + /* Each TB has an associated circular list of TBs jumping to this one. * jmp_list_first points to the first TB jumping to this one. * jmp_list_next is used to point to the next TB in a list. * Since each TB can have two jumps, it can participate in two lists. --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664114437143.8151900298153; Tue, 10 Oct 2017 12:35:14 -0700 (PDT) Received: from localhost ([::1]:36811 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Iu-0003vN-Ug for importer@patchew.org; Tue, 10 Oct 2017 15:35:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58759) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20EH-0000Vy-Gi for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20EG-0004xI-KB for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:13 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:50210) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20EG-0004wz-EN for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:12 -0400 Received: by mail-pf0-x233.google.com with SMTP id m63so18276906pfk.7 for ; Tue, 10 Oct 2017 12:30:12 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uG5OhsPX14oZq3VVK+Rfgxl4+EVwuLdEt9otmw2teC8=; b=I+lyCVbnDwIpunSpx8Hbq4FJ+jRI3CBiFtSWHvRyWsTD6+GzybAXYjEL5IVKe3//C3 giwcQIQBRRvhcyybvH/yo4p7oe9CoDBYe+TMcH8ERXR+mPoiHWHnALz35Qd7KU8GlPPC P5A3eKMcTyQJNV1c78Ub065ovt85nouLrpSnA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uG5OhsPX14oZq3VVK+Rfgxl4+EVwuLdEt9otmw2teC8=; b=cRybRB4OznU56tK4cweMlS5PdyUmoroji9T/6g+EbGSfAY0BAlVNGhnvzYqNJ2j0v1 JVY94kgc1qOq13jmxxoO2Fll/zByZVcwu15Fhu0khYeW9disaZTZ9f8te6tLHy2AbUkm y05h/cCG+P0tkU/2F1divaOrvxD/kLifFWXxPkUlu1dbULpzlz4rluyNhQgY0wwaumdc RLPLGLk3bFpBkiC5nrQZPe7pnEidd6yzub/bBBMI/UMZOyZUtATG0HoZez3MDAb5T/Q+ ZkSivO2SJ2vMdznmjou9euPlkOASnWEVi2LslpEpsadJg7wmviHdsnSO1bPfVBI+X6ls eLVg== X-Gm-Message-State: AMCzsaXiCZW647qJKuuyH7JpomJGFwqC5ybQT8EgQ9R37e7mDkg++Mxx emNoPzXcZmJMLpViKCPalRTvHjfmt3s= X-Google-Smtp-Source: AOwi7QAy7/vUubzPvGTgNmcSmnUHUS2lltOJtUV35utXBgTujBs6n1lwlETX28GJc2dVOSwzECA2RA== X-Received: by 10.99.47.6 with SMTP id v6mr13248614pgv.452.1507663811266; Tue, 10 Oct 2017 12:30:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:29:47 -0700 Message-Id: <20171010193003.28857-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PULL v2 04/20] translate-all: make have_tb_lock static X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 From: "Emilio G. Cota" It is only used by this object, and it's not exported to any other. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index b3bfe65059..a7c1d4e3f2 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -139,7 +139,7 @@ TCGContext tcg_ctx; bool parallel_cpus; =20 /* translation block context */ -__thread int have_tb_lock; +static __thread int have_tb_lock; =20 static void page_table_config_init(void) { --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150766429222369.26925765761371; Tue, 10 Oct 2017 12:38:12 -0700 (PDT) Received: from localhost ([::1]:36826 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Lm-0006Dj-45 for importer@patchew.org; Tue, 10 Oct 2017 15:37:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58782) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20EJ-0000X8-1s for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20EH-0004za-UA for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:14 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:45679) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20EH-0004y9-Oc for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:13 -0400 Received: by mail-pf0-x233.google.com with SMTP id d28so3568998pfe.2 for ; Tue, 10 Oct 2017 12:30:13 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Jmmg93vGlfXYGCWPpMGtBaYKMC23pLLXYbM9fkFhyDY=; b=Q17l8FHg6TMDqhzXUYHqL2gWewq96NZccc9avk5xLllHMIoPMFQN5xBClPT8e8IHgN uo/y3pBG6KjMCsMujB93QGR0wH1ir+Q6kT9FStVgScNnCnSVvllYr89S7KbJfA1FYeAc ptCBw13KT7y8SFB77yX4gCRkKGexggSYhIZJk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Jmmg93vGlfXYGCWPpMGtBaYKMC23pLLXYbM9fkFhyDY=; b=kZp4PaNhCMNDqJK0YdpCuHTm4SgVEo11+FbuN6jff/04KkG+AA1zCQysrjaNu4Gk5A VOp0YTut4i0deNuHKyP4maDu5z2r8loUVrXjFHtqnpDpLxhs7AjNTQGMj66akm8KOBkm PA/3YEPGcZv9nw5FQqyirHXgMyoK/vYgKk2XfsbQuyzOgxAQRroTVno3KxS/mhNsAbJl a3nqisAZkoUJNjRJyvmByaDwnfNAdn6owYC/CBAuWHE8TGrb5A0I9qn336JqA5PEQpaV I/sMiEbw2ig8QuELJBrx1aVm5/vOZieMJum3T0aLJYeCArEjenlz7Eiv33PLEPmiKdyV FL7A== X-Gm-Message-State: AMCzsaXJBC33CsmIga3x6bXuGMQtO+r+PeiV537zyRRQ0VCecLJwwIkt RTJxvqmrGQVgA5Szbn4/XqwyJOWt+dA= X-Google-Smtp-Source: AOwi7QBKZapCaejHVimodMtc+4FE4eatiZ+a42KvopaOLkzZZHC63mVHbVKsV8BdeR/sxSkFvTyvhA== X-Received: by 10.101.65.129 with SMTP id a1mr13373388pgq.203.1507663812550; Tue, 10 Oct 2017 12:30:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:29:48 -0700 Message-Id: <20171010193003.28857-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PULL v2 05/20] cpu-exec: rename have_tb_lock to acquired_tb_lock in tb_find X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Reusing the have_tb_lock name, which is also defined in translate-all.c, makes code reviewing unnecessarily harder. Avoid potential confusion by renaming the local have_tb_lock variable to something else. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ff6866624a..32104b8d8c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -372,7 +372,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; - bool have_tb_lock =3D false; + bool acquired_tb_lock =3D false; =20 /* we record a subset of the CPU state. It will always be the same before a given translated block @@ -391,7 +391,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, */ mmap_lock(); tb_lock(); - have_tb_lock =3D true; + acquired_tb_lock =3D true; =20 /* There's a chance that our desired tb has been translated wh= ile * taking the locks so we check again inside the lock. @@ -419,15 +419,15 @@ static inline TranslationBlock *tb_find(CPUState *cpu, #endif /* See if we can patch the calling TB. */ if (last_tb && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - if (!have_tb_lock) { + if (!acquired_tb_lock) { tb_lock(); - have_tb_lock =3D true; + acquired_tb_lock =3D true; } if (!tb->invalid) { tb_add_jump(last_tb, tb_exit, tb); } } - if (have_tb_lock) { + if (acquired_tb_lock) { tb_unlock(); } return tb; --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664115397957.7837261780339; Tue, 10 Oct 2017 12:35:15 -0700 (PDT) Received: from localhost ([::1]:36812 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Iv-0003w7-Fi for importer@patchew.org; Tue, 10 Oct 2017 15:35:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58796) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20EK-0000Xv-13 for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20EJ-00051a-AG for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:16 -0400 Received: from mail-pf0-x22e.google.com ([2607:f8b0:400e:c00::22e]:49908) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20EJ-000503-2x for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:15 -0400 Received: by mail-pf0-x22e.google.com with SMTP id l188so18271676pfc.6 for ; Tue, 10 Oct 2017 12:30:14 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ldxUa5xmFXm5OESHWBxV8Hz1PBcjUVlLDSHgmwg+rLo=; b=E/upanhwijEkOtVphtLTGQGuzkebE5bhKGNaUn14VDoy8jsy03W3CWP1CzmjQI0jia PgKkJOvgTiyBfeG1VXFUmbtvuiTWLYDNs13QrXYxCBp9E5oQaJV0Zhe4R+nFujl381tH JUQne8vALvLBb+x+75kAwA0bI4QD375EFObCc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ldxUa5xmFXm5OESHWBxV8Hz1PBcjUVlLDSHgmwg+rLo=; b=KF5hvnhBcpliUDDNYtYju1fxQHICVH7GqIVtfTI53sHvwn4teyDfDY5MSajoBXw8UJ /0J+NSyxqmz8I8YaVfG9AUlUIyi4Kx/DkLgEQ8o86S8b+pqwURwse+jJUC6tLoS6qbSj g8Ql+FASZ6VgZd8jzKXeApkTIDqTdt99JjhkEdyfVMqUDiWoy7z91a5hV064XVQRXa09 F9tkl+jqar990TRAZ9kBRwy2VJAun97GjJaAMAqLG0D743DMZS8YYH/U9ip68WiXwYRT yw9n8rL7z7ayvRaHu2JhXaBM2u9z5lRWZw/wlDBLwTeQlFh9fO1Fsl5h4TtIH5etEhid fhLA== X-Gm-Message-State: AMCzsaW5DEVubehGn2N9XmqqV7M4KExBYHSWl5M28ya8UpPTBStJ0Gl7 2YgDWe/p2MMp1YR6TX+TSXk4huXzWo4= X-Google-Smtp-Source: AOwi7QC+9+g8wpGTiu5Ar1Zp2ewYzBchIxAQW99Tm9fbkysdjNR6ofW7+oiOXkXw+oBiqEaZg3NeWw== X-Received: by 10.99.3.1 with SMTP id 1mr13467033pgd.111.1507663813866; Tue, 10 Oct 2017 12:30:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:29:49 -0700 Message-Id: <20171010193003.28857-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22e Subject: [Qemu-devel] [PULL v2 06/20] tcg/i386: constify tcg_target_callee_save_regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 69e49c9f58..63d27f10e7 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2499,7 +2499,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return NULL; } =20 -static int tcg_target_callee_save_regs[] =3D { +static const int tcg_target_callee_save_regs[] =3D { #if TCG_TARGET_REG_BITS =3D=3D 64 TCG_REG_RBP, TCG_REG_RBX, --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507663939245400.78753001606447; Tue, 10 Oct 2017 12:32:19 -0700 (PDT) Received: from localhost ([::1]:36804 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20GA-0001la-1C for importer@patchew.org; Tue, 10 Oct 2017 15:32:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58811) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20EL-0000ZR-II for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20EK-00052Y-Nt for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:17 -0400 Received: from mail-pf0-x22c.google.com ([2607:f8b0:400e:c00::22c]:51205) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20EK-000520-Hd for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:16 -0400 Received: by mail-pf0-x22c.google.com with SMTP id n14so16372264pfh.8 for ; Tue, 10 Oct 2017 12:30:16 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8GK3TdJPE5M/4MhRTJRRgyiuGlONH/hqYkF1/ZHU9HY=; b=iQk8gTV3JTlBCh9BDmnPjcZRa+mhkLCTcN+DzQfXu9qQfGgqYt+DoktQRsfXMfsbBD 96jCMW+5rDjZsB7HEciz98andRuraEX048SIcD7IKBGmzA9dffing5j3+CZkDUmlPdFh qD63lKKpDSmu78SgpfMlw+0QOx8/bbz+qD2XM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8GK3TdJPE5M/4MhRTJRRgyiuGlONH/hqYkF1/ZHU9HY=; b=pYzbMCFrSw8gLOgA2bwRxhEyOCjwZAPA6c7UAuglKB7Kt7rTza7jxMcRDAdvItmmwl SuO00WICGgUez3/CpCSMz5ScMFmbn+cCxaZ+RT6A0Xn6DxxY/dACE3frXUFC4t2p1PhA tq7LduPtQg7lhdAdFKFglB+Bl9YVKD42gr5nZmOGhF19bYqUarX1wheXJn2yxphwQ7Un hIvS5B2AIVUsOzeP44Zh4xuEVlBZKPm6JHUHe4k5TTT/QP6fUBDEj6GXWTeluCTGEv/+ C7A+4sRnGX6DhjH0FWWZtX1gPqDJ3gAqFNGIBFzJeMl50Zbm6EIVEihyXJSF8HcQ05PN QeqA== X-Gm-Message-State: AMCzsaVXM13FYZrNkcN2RMlAzgxNk+urO/VLjGN0sAJ6ft6Td3lH/Qbr +HdmgMR3+/4MCf3+9Z+QbOFclykW3ck= X-Google-Smtp-Source: AOwi7QC6loBZSw8DR3oNmIbwmkiH+Qk/ETsyMMDUQvqUw8nPuVtp7FWd4vYBlJY4vDTw2WSoUohvKw== X-Received: by 10.101.75.2 with SMTP id r2mr12841293pgq.51.1507663815273; Tue, 10 Oct 2017 12:30:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:29:50 -0700 Message-Id: <20171010193003.28857-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PULL v2 07/20] tcg/mips: constify tcg_target_callee_save_regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index ce4030602f..e993138930 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -2341,7 +2341,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) } } =20 -static int tcg_target_callee_save_regs[] =3D { +static const int tcg_target_callee_save_regs[] =3D { TCG_REG_S0, /* used for the global env (TCG_AREG0) */ TCG_REG_S1, TCG_REG_S2, --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664463171933.6215334433289; Tue, 10 Oct 2017 12:41:03 -0700 (PDT) Received: from localhost ([::1]:36844 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Oh-0000FE-Ak for importer@patchew.org; Tue, 10 Oct 2017 15:40:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58853) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20EV-0000gl-6E for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20EM-00053f-Iq for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:22 -0400 Received: from mail-pf0-x230.google.com ([2607:f8b0:400e:c00::230]:47077) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20EM-00053L-A4 for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:18 -0400 Received: by mail-pf0-x230.google.com with SMTP id p87so9224696pfj.3 for ; Tue, 10 Oct 2017 12:30:18 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hwYOkpKJ0TKAga7CCdXbN4jG9AlZr9sHDgWQ00fIyIU=; b=Hffp+1uEL0ERqxXlHxvBDoohpVpdjSdIZzOTrWVOHaTBdzbLb85RCsAa1fkf1P/AT7 6chhK18oCmKLpM8Uc27qG66USkfwF003SYelEyPWpmY4XGuHWUXOPr1u3X78rHxkMtNw QimalpPRD9sCopEil5kbnT+5mLtZ9yL3vUC2E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hwYOkpKJ0TKAga7CCdXbN4jG9AlZr9sHDgWQ00fIyIU=; b=dBTxhTSXEeBEnMKgfF1Z5TYYjWjrKpS6cPlm3czB2KcrMwPIiSNQvBm2rxHeFUb0Fn JYZN6j9EmqaeTHuowgkUq7yCk1toK2iymHjVqn0MszYsppj27o9wUX+MruQnD0/XpgHl gKjxXFgo1atkRfMbb/C0Aj/dtaAjLvr8zn2fg/8CZnQrgf8SHH29UCmuP+ULTFUk+gb0 +Ohvrs3XzS8gRDCSAOQ2qAvqXkKzGB7icBX8xqaYXgVS8Cd0Rpe+SHxyw/SB/nyxzGO6 6ym8jgHw+R4pEgTQWtVg3kIj4LqOXjg9KN+5FeGq5nw+OHoIq6s8I2RGDAeVB9gVbHy4 n3LA== X-Gm-Message-State: AMCzsaUsMh0nIKUNp7XgMEG633kMExX5hsV1moc9inZbWbJ1adNCEYeC ANo/fIvvA+JCtBFk0CaLqZcTF3ThNko= X-Google-Smtp-Source: AOwi7QDGvU+XtD4+BApPhriFTRljoGqQ7dqoU8w6PIuqrOAQOnxqDHBcHWd/Dc/o/leZvOc//UEjJA== X-Received: by 10.159.207.134 with SMTP id z6mr12953706plo.258.1507663816848; Tue, 10 Oct 2017 12:30:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:29:51 -0700 Message-Id: <20171010193003.28857-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::230 Subject: [Qemu-devel] [PULL v2 08/20] tcg: remove addr argument from lookup_tb_ptr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" It is unlikely that we will ever want to call this helper passing an argument other than the current PC. So just remove the argument, and use the pc we already get from cpu_get_tb_cpu_state. This change paves the way to having a common "tb_lookup" function. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 2 +- tcg/tcg-op.h | 4 ++-- accel/tcg/tcg-runtime.c | 20 ++++++++++---------- target/alpha/translate.c | 2 +- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 5 +---- target/hppa/translate.c | 6 +++--- target/i386/translate.c | 17 +++++------------ target/mips/translate.c | 4 ++-- target/s390x/translate.c | 2 +- target/sh4/translate.c | 4 ++-- tcg/tcg-op.c | 4 ++-- 12 files changed, 32 insertions(+), 42 deletions(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index c41d38a557..1df17d0ba9 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -24,7 +24,7 @@ DEF_HELPER_FLAGS_1(clrsb_i64, TCG_CALL_NO_RWG_SE, i64, i6= 4) DEF_HELPER_FLAGS_1(ctpop_i32, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(ctpop_i64, TCG_CALL_NO_RWG_SE, i64, i64) =20 -DEF_HELPER_FLAGS_2(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env, tl) +DEF_HELPER_FLAGS_1(lookup_tb_ptr, TCG_CALL_NO_WG_SE, ptr, env) =20 DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env) =20 diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 5d3278f243..18d01b2f43 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -797,7 +797,7 @@ static inline void tcg_gen_exit_tb(uintptr_t val) void tcg_gen_goto_tb(unsigned idx); =20 /** - * tcg_gen_lookup_and_goto_ptr() - look up a TB and jump to it if valid + * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if v= alid * @addr: Guest address of the target TB * * If the TB is not valid, jump to the epilogue. @@ -805,7 +805,7 @@ void tcg_gen_goto_tb(unsigned idx); * This operation is optional. If the TCG backend does not implement goto_= ptr, * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argume= nt. */ -void tcg_gen_lookup_and_goto_ptr(TCGv addr); +void tcg_gen_lookup_and_goto_ptr(void); =20 #if TARGET_LONG_BITS =3D=3D 32 #define tcg_temp_new() tcg_temp_new_i32() diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index aafb171294..b75394aba8 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -144,33 +144,33 @@ uint64_t HELPER(ctpop_i64)(uint64_t arg) return ctpop64(arg); } =20 -void *HELPER(lookup_tb_ptr)(CPUArchState *env, target_ulong addr) +void *HELPER(lookup_tb_ptr)(CPUArchState *env) { CPUState *cpu =3D ENV_GET_CPU(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags, addr_hash; + uint32_t flags, hash; =20 - addr_hash =3D tb_jmp_cache_hash_func(addr); - tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[addr_hash]); cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + hash =3D tb_jmp_cache_hash_func(pc); + tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[hash]); =20 if (unlikely(!(tb - && tb->pc =3D=3D addr + && tb->pc =3D=3D pc && tb->cs_base =3D=3D cs_base && tb->flags =3D=3D flags && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate))) { - tb =3D tb_htable_lookup(cpu, addr, cs_base, flags); + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); if (!tb) { return tcg_ctx.code_gen_epilogue; } - atomic_set(&cpu->tb_jmp_cache[addr_hash], tb); + atomic_set(&cpu->tb_jmp_cache[hash], tb); } =20 - qemu_log_mask_and_addr(CPU_LOG_EXEC, addr, + qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", - tb->tc_ptr, cpu->cpu_index, addr, - lookup_symbol(addr)); + tb->tc_ptr, cpu->cpu_index, pc, + lookup_symbol(pc)); return tb->tc_ptr; } =20 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 5a92c4accb..f32c95b9a1 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -3029,7 +3029,7 @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) /* FALLTHRU */ case DISAS_PC_UPDATED: if (!use_exit_tb(ctx)) { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); break; } /* FALLTHRU */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 899ffb96fc..a39b9d3633 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -379,7 +379,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, = uint64_t dest) } else if (s->base.singlestep_enabled) { gen_exception_internal(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); s->base.is_jmp =3D DISAS_NORETURN; } } @@ -11363,7 +11363,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) gen_a64_set_pc_im(dc->pc); /* fall through */ case DISAS_JUMP: - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); break; case DISAS_EXIT: tcg_gen_exit_tb(0); diff --git a/target/arm/translate.c b/target/arm/translate.c index ab1a12a1b8..fdc46cc525 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4173,10 +4173,7 @@ static inline bool use_goto_tb(DisasContext *s, targ= et_ulong dest) =20 static void gen_goto_ptr(void) { - TCGv addr =3D tcg_temp_new(); - tcg_gen_extu_i32_tl(addr, cpu_R[15]); - tcg_gen_lookup_and_goto_ptr(addr); - tcg_temp_free(addr); + tcg_gen_lookup_and_goto_ptr(); } =20 /* This will end the TB but doesn't guarantee we'll return to diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b6e2652341..26242f4b3c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -505,7 +505,7 @@ static void gen_goto_tb(DisasContext *ctx, int which, if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); } } } @@ -1515,7 +1515,7 @@ static DisasJumpType do_ibranch(DisasContext *ctx, TC= Gv dest, if (link !=3D 0) { tcg_gen_movi_tl(cpu_gr[link], ctx->iaoq_n); } - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); return nullify_end(ctx, DISAS_NEXT); } else { cond_prep(&ctx->null_cond); @@ -3873,7 +3873,7 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase,= CPUState *cs) if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { - tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); + tcg_gen_lookup_and_goto_ptr(); } break; default: diff --git a/target/i386/translate.c b/target/i386/translate.c index 7b920115f9..5d61fa96ad 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -2511,7 +2511,7 @@ static void gen_bnd_jmp(DisasContext *s) If RECHECK_TF, emit a rechecking helper for #DB, ignoring the state of S->TF. This is used by the syscall/sysret insns. */ static void -do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr) +do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr) { gen_update_cc_op(s); =20 @@ -2532,12 +2532,8 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, boo= l recheck_tf, TCGv jr) tcg_gen_exit_tb(0); } else if (s->tf) { gen_helper_single_step(cpu_env); - } else if (!TCGV_IS_UNUSED(jr)) { - TCGv vaddr =3D tcg_temp_new(); - - tcg_gen_add_tl(vaddr, jr, cpu_seg_base[R_CS]); - tcg_gen_lookup_and_goto_ptr(vaddr); - tcg_temp_free(vaddr); + } else if (jr) { + tcg_gen_lookup_and_goto_ptr(); } else { tcg_gen_exit_tb(0); } @@ -2547,10 +2543,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, boo= l recheck_tf, TCGv jr) static inline void gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf) { - TCGv unused; - - TCGV_UNUSED(unused); - do_gen_eob_worker(s, inhibit, recheck_tf, unused); + do_gen_eob_worker(s, inhibit, recheck_tf, false); } =20 /* End of block. @@ -2569,7 +2562,7 @@ static void gen_eob(DisasContext *s) /* Jump to register */ static void gen_jr(DisasContext *s, TCGv dest) { - do_gen_eob_worker(s, false, false, dest); + do_gen_eob_worker(s, false, false, true); } =20 /* generate a jump to eip. No segment change must happen before as a diff --git a/target/mips/translate.c b/target/mips/translate.c index d16d879df7..ac05f3aa09 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4303,7 +4303,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int= n, target_ulong dest) save_cpu_state(ctx, 0); gen_helper_raise_exception_debug(cpu_env); } - tcg_gen_lookup_and_goto_ptr(cpu_PC); + tcg_gen_lookup_and_goto_ptr(); } } =20 @@ -10883,7 +10883,7 @@ static void gen_branch(DisasContext *ctx, int insn_= bytes) save_cpu_state(ctx, 0); gen_helper_raise_exception_debug(cpu_env); } - tcg_gen_lookup_and_goto_ptr(cpu_PC); + tcg_gen_lookup_and_goto_ptr(); break; default: fprintf(stderr, "unknown branch 0x%x\n", proc_hflags); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 9ef95141f9..165d2cac3e 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -5949,7 +5949,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) } else if (use_exit_tb(&dc) || status =3D=3D EXIT_PC_STALE_NOCHAIN= ) { tcg_gen_exit_tb(0); } else { - tcg_gen_lookup_and_goto_ptr(psw_addr); + tcg_gen_lookup_and_goto_ptr(); } break; default: diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 10191073b2..8db9fba26e 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -261,7 +261,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, targe= t_ulong dest) } else if (use_exit_tb(ctx)) { tcg_gen_exit_tb(0); } else { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); } } } @@ -278,7 +278,7 @@ static void gen_jump(DisasContext * ctx) } else if (use_exit_tb(ctx)) { tcg_gen_exit_tb(0); } else { - tcg_gen_lookup_and_goto_ptr(cpu_pc); + tcg_gen_lookup_and_goto_ptr(); } } else { gen_goto_tb(ctx, 0, ctx->delayed_pc); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 688d91755b..d3c0e4799e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2588,11 +2588,11 @@ void tcg_gen_goto_tb(unsigned idx) tcg_gen_op1i(INDEX_op_goto_tb, idx); } =20 -void tcg_gen_lookup_and_goto_ptr(TCGv addr) +void tcg_gen_lookup_and_goto_ptr(void) { if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)= ) { TCGv_ptr ptr =3D tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env, addr); + gen_helper_lookup_tb_ptr(ptr, tcg_ctx.tcg_env); tcg_gen_op1i(INDEX_op_goto_ptr, GET_TCGV_PTR(ptr)); tcg_temp_free_ptr(ptr); } else { --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664455409398.4496004629202; Tue, 10 Oct 2017 12:40:55 -0700 (PDT) Received: from localhost ([::1]:36842 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20OX-00007L-J1 for importer@patchew.org; Tue, 10 Oct 2017 15:40:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58863) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20EW-0000hv-Gu for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20EN-000541-Vk for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:23 -0400 Received: from mail-pf0-x229.google.com ([2607:f8b0:400e:c00::229]:55364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20EN-00053r-M7 for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:19 -0400 Received: by mail-pf0-x229.google.com with SMTP id 17so9937337pfn.12 for ; Tue, 10 Oct 2017 12:30:19 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::229 Subject: [Qemu-devel] [PULL v2 09/20] tcg: consolidate TB lookups in tb_lookup__cpu_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" This avoids duplicating code. cpu_exec_step will also use the new common function once we integrate parallel_cpus into tb->cflags. Note that in this commit we also fix a race, described by Richard Henderson during review. Think of this scenario with threads A and B: (A) Lookup succeeds for TB in hash without tb_lock (B) Sets the TB's tb->invalid flag (B) Removes the TB from tb_htable (B) Clears all CPU's tb_jmp_cache (A) Store TB into local tb_jmp_cache Given that order of events, (A) will keep executing that invalid TB until another flush of its tb_jmp_cache happens, which in theory might never happ= en. We can fix this by checking the tb->invalid flag every time we look up a TB from tb_jmp_cache, so that in the above scenario, next time we try to find that TB in tb_jmp_cache, we won't, and will therefore be forced to look it up in tb_htable. Performance-wise, I measured a small improvement when booting debian-arm. Note that inlining pays off: Performance counter stats for 'taskset -c 0 qemu-system-arm \ -machine type=3Dvirt -nographic -smp 1 -m 4096 \ -netdev user,id=3Dunet,hostfwd=3Dtcp::2222-:22 \ -device virtio-net-device,netdev=3Dunet \ -drive file=3Djessie.qcow2,id=3Dmyblock,index=3D0,if=3Dnone \ -device virtio-blk-device,drive=3Dmyblock \ -kernel kernel.img -append console=3DttyAMA0 root=3D/dev/vda1 \ -name arm,debug-threads=3Don -smp 1' (10 runs): Before: 18714.917392 task-clock # 0.952 CPUs utilized = ( +- 0.95% ) 23,142 context-switches # 0.001 M/sec = ( +- 0.50% ) 1 CPU-migrations # 0.000 M/sec 10,558 page-faults # 0.001 M/sec = ( +- 0.95% ) 53,957,727,252 cycles # 2.883 GHz = ( +- 0.91% ) [83.33%] 24,440,599,852 stalled-cycles-frontend # 45.30% frontend cycles idl= e ( +- 1.20% ) [83.33%] 16,495,714,424 stalled-cycles-backend # 30.57% backend cycles idl= e ( +- 0.95% ) [66.66%] 76,267,572,582 instructions # 1.41 insns per cycle # 0.32 stalled cycles per = insn ( +- 0.87% ) [83.34%] 12,692,186,323 branches # 678.186 M/sec = ( +- 0.92% ) [83.35%] 263,486,879 branch-misses # 2.08% of all branches = ( +- 0.73% ) [83.34%] 19.648474449 seconds time elapsed = ( +- 0.82% ) After, w/ inline (this patch): 18471.376627 task-clock # 0.955 CPUs utilized = ( +- 0.96% ) 23,048 context-switches # 0.001 M/sec = ( +- 0.48% ) 1 CPU-migrations # 0.000 M/sec 10,708 page-faults # 0.001 M/sec = ( +- 0.81% ) 53,208,990,796 cycles # 2.881 GHz = ( +- 0.98% ) [83.34%] 23,941,071,673 stalled-cycles-frontend # 44.99% frontend cycles idl= e ( +- 0.95% ) [83.34%] 16,161,773,848 stalled-cycles-backend # 30.37% backend cycles idl= e ( +- 0.76% ) [66.67%] 75,786,269,766 instructions # 1.42 insns per cycle # 0.32 stalled cycles per = insn ( +- 1.24% ) [83.34%] 12,573,617,143 branches # 680.708 M/sec = ( +- 1.34% ) [83.33%] 260,235,550 branch-misses # 2.07% of all branches = ( +- 0.66% ) [83.33%] 19.340502161 seconds time elapsed = ( +- 0.56% ) After, w/o inline: 18791.253967 task-clock # 0.954 CPUs utilized = ( +- 0.78% ) 23,230 context-switches # 0.001 M/sec = ( +- 0.42% ) 1 CPU-migrations # 0.000 M/sec 10,563 page-faults # 0.001 M/sec = ( +- 1.27% ) 54,168,674,622 cycles # 2.883 GHz = ( +- 0.80% ) [83.34%] 24,244,712,629 stalled-cycles-frontend # 44.76% frontend cycles idl= e ( +- 1.37% ) [83.33%] 16,288,648,572 stalled-cycles-backend # 30.07% backend cycles idl= e ( +- 0.95% ) [66.66%] 77,659,755,503 instructions # 1.43 insns per cycle # 0.31 stalled cycles per = insn ( +- 0.97% ) [83.34%] 12,922,780,045 branches # 687.702 M/sec = ( +- 1.06% ) [83.34%] 261,962,386 branch-misses # 2.03% of all branches = ( +- 0.71% ) [83.35%] 19.700174670 seconds time elapsed = ( +- 0.56% ) Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/tb-lookup.h | 49 ++++++++++++++++++++++++++++++++++++++++++++= ++++ accel/tcg/cpu-exec.c | 47 ++++++++++++++++++--------------------------= -- accel/tcg/tcg-runtime.c | 24 ++++++------------------ 3 files changed, 73 insertions(+), 47 deletions(-) create mode 100644 include/exec/tb-lookup.h diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h new file mode 100644 index 0000000000..9d32cb0c6e --- /dev/null +++ b/include/exec/tb-lookup.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2017, Emilio G. Cota + * + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#ifndef EXEC_TB_LOOKUP_H +#define EXEC_TB_LOOKUP_H + +#include "qemu/osdep.h" + +#ifdef NEED_CPU_H +#include "cpu.h" +#else +#include "exec/poison.h" +#endif + +#include "exec/exec-all.h" +#include "exec/tb-hash.h" + +/* Might cause an exception, so have a longjmp destination ready */ +static inline TranslationBlock * +tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_bas= e, + uint32_t *flags) +{ + CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; + TranslationBlock *tb; + uint32_t hash; + + cpu_get_tb_cpu_state(env, pc, cs_base, flags); + hash =3D tb_jmp_cache_hash_func(*pc); + tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[hash]); + if (likely(tb && + tb->pc =3D=3D *pc && + tb->cs_base =3D=3D *cs_base && + tb->flags =3D=3D *flags && + tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && + !atomic_read(&tb->invalid))) { + return tb; + } + tb =3D tb_htable_lookup(cpu, *pc, *cs_base, *flags); + if (tb =3D=3D NULL) { + return NULL; + } + atomic_set(&cpu->tb_jmp_cache[hash], tb); + return tb; +} + +#endif /* EXEC_TB_LOOKUP_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 32104b8d8c..f8a1d68db7 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -28,6 +28,7 @@ #include "exec/address-spaces.h" #include "qemu/rcu.h" #include "exec/tb-hash.h" +#include "exec/tb-lookup.h" #include "exec/log.h" #include "qemu/main-loop.h" #if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) @@ -368,43 +369,31 @@ static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *last_tb, int tb_exit) { - CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; bool acquired_tb_lock =3D false; =20 - /* we record a subset of the CPU state. It will - always be the same before a given translated block - is executed. */ - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]); - if (unlikely(!tb || tb->pc !=3D pc || tb->cs_base !=3D cs_base || - tb->flags !=3D flags || - tb->trace_vcpu_dstate !=3D *cpu->trace_dstate)) { - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - - /* mmap_lock is needed by tb_gen_code, and mmap_lock must be - * taken outside tb_lock. As system emulation is currently - * single threaded the locks are NOPs. - */ - mmap_lock(); - tb_lock(); - acquired_tb_lock =3D true; - - /* There's a chance that our desired tb has been translated wh= ile - * taking the locks so we check again inside the lock. - */ - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - /* if no translated code available, then translate it now = */ - tb =3D tb_gen_code(cpu, pc, cs_base, flags, 0); - } + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + if (tb =3D=3D NULL) { + /* mmap_lock is needed by tb_gen_code, and mmap_lock must be + * taken outside tb_lock. As system emulation is currently + * single threaded the locks are NOPs. + */ + mmap_lock(); + tb_lock(); + acquired_tb_lock =3D true; =20 - mmap_unlock(); + /* There's a chance that our desired tb has been translated while + * taking the locks so we check again inside the lock. + */ + tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); + if (likely(tb =3D=3D NULL)) { + /* if no translated code available, then translate it now */ + tb =3D tb_gen_code(cpu, pc, cs_base, flags, 0); } =20 + mmap_unlock(); /* We add the TB in the virtual pc hash table for the fast lookup = */ atomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); } diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index b75394aba8..d0edd944b0 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -27,7 +27,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" -#include "exec/tb-hash.h" +#include "exec/tb-lookup.h" #include "disas/disas.h" #include "exec/log.h" =20 @@ -149,24 +149,12 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) CPUState *cpu =3D ENV_GET_CPU(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags, hash; - - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - hash =3D tb_jmp_cache_hash_func(pc); - tb =3D atomic_rcu_read(&cpu->tb_jmp_cache[hash]); - - if (unlikely(!(tb - && tb->pc =3D=3D pc - && tb->cs_base =3D=3D cs_base - && tb->flags =3D=3D flags - && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate))) { - tb =3D tb_htable_lookup(cpu, pc, cs_base, flags); - if (!tb) { - return tcg_ctx.code_gen_epilogue; - } - atomic_set(&cpu->tb_jmp_cache[hash], tb); - } + uint32_t flags; =20 + tb =3D tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags); + if (tb =3D=3D NULL) { + return tcg_ctx.code_gen_epilogue; + } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", tb->tc_ptr, cpu->cpu_index, pc, --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664111796261.61414512838246; Tue, 10 Oct 2017 12:35:11 -0700 (PDT) Received: from localhost ([::1]:36813 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20J1-0003zV-Uz for importer@patchew.org; Tue, 10 Oct 2017 15:35:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58862) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20EW-0000hu-Gl for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20EP-00054P-A2 for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:23 -0400 Received: from mail-pf0-x235.google.com ([2607:f8b0:400e:c00::235]:53300) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20EO-00054C-St for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:21 -0400 Received: by mail-pf0-x235.google.com with SMTP id n73so11596349pfg.10 for ; Tue, 10 Oct 2017 12:30:20 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AlG96ZS7wj0sBsmbSuh4GY4IomgcygTB/0W6OfuBaEA=; b=MWXNv1Pphelk+q724Nyv4l3lTjDRRs1T3HmCv7m8Fzu0jzl4l7UIjEdQ2wWZUE9jFQ CHcTDVah8dxJ/D5P2vw6L+Fo3DIK0j8bnjHUgEyskwh+bqlJ/pEQBiG8vtwiYxDa3jEt SHkiepDDzCqYfLNHJAlZgXb+ON4pFpK6tNS6s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AlG96ZS7wj0sBsmbSuh4GY4IomgcygTB/0W6OfuBaEA=; b=MKwf4w+cZ6heookGqE44T/hF535hS4auQiZc3MTltuMPGJK7GfjF7ICstt2SHQS98+ V4XYpo9fLBS1m4m+hhjsOcs1Rg7ImuRnNg+iBGN0B5hjplCjB/Ei3In8uv4UB3M91Wh+ D91RTMvijG7ex4Gn3z/pkJtjzTeb1WSvk4f+mgDVSBgWV7o/gduw26A93DOaZgpy6Alj hhTaI6W4WICV7lSbOqwgNe6uPz1Gbva42YpWXZ4hinMSyQGo076sbuuXPduI8Lr8DpXh gPd7CZI2rye6NjIbHZ0yHj8qlr8dsoqjiRMUmJQKZRwbVj2LjoHjI31KwywUzm6v1e58 pheg== X-Gm-Message-State: AMCzsaW/xBT/iejl7LSLScYp4/QJZtiP1oPRlE7OOE+0o/zMIN3mUm06 RgvAW7p6FLsctEutBuy9ksN6tvumOCE= X-Google-Smtp-Source: AOwi7QDzMHTo8WpEeOpAQ8mk5otI5CeG9i9eawZ7HXXoagll5ywevsvmOjy7cmWjDauaWJBxoJwVwQ== X-Received: by 10.98.181.3 with SMTP id y3mr4256181pfe.264.1507663819652; Tue, 10 Oct 2017 12:30:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:29:53 -0700 Message-Id: <20171010193003.28857-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::235 Subject: [Qemu-devel] [PULL v2 10/20] exec-all: bring tb->invalid into tb->cflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" This gets rid of a hole in struct TranslationBlock. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 3 +-- include/exec/tb-lookup.h | 2 +- accel/tcg/cpu-exec.c | 4 ++-- accel/tcg/translate-all.c | 3 +-- 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a9a8bb6f83..3135aaf4c9 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -314,12 +314,11 @@ struct TranslationBlock { #define CF_NOCACHE 0x10000 /* To be freed after execution */ #define CF_USE_ICOUNT 0x20000 #define CF_IGNORE_ICOUNT 0x40000 /* Do not generate icount code */ +#define CF_INVALID 0x80000 /* TB is stale. Setters must acquire tb_loc= k */ =20 /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; =20 - uint16_t invalid; - void *tc_ptr; /* pointer to the translated code */ uint8_t *tc_search; /* pointer to search data */ /* original tb when cflags has CF_NOCACHE */ diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index 9d32cb0c6e..436b6d5ecf 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -35,7 +35,7 @@ tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, tar= get_ulong *cs_base, tb->cs_base =3D=3D *cs_base && tb->flags =3D=3D *flags && tb->trace_vcpu_dstate =3D=3D *cpu->trace_dstate && - !atomic_read(&tb->invalid))) { + !(atomic_read(&tb->cflags) & CF_INVALID))) { return tb; } tb =3D tb_htable_lookup(cpu, *pc, *cs_base, *flags); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f8a1d68db7..9cd809d607 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -294,7 +294,7 @@ static bool tb_cmp(const void *p, const void *d) tb->cs_base =3D=3D desc->cs_base && tb->flags =3D=3D desc->flags && tb->trace_vcpu_dstate =3D=3D desc->trace_vcpu_dstate && - !atomic_read(&tb->invalid)) { + !(atomic_read(&tb->cflags) & CF_INVALID)) { /* check next page if needed */ if (tb->page_addr[1] =3D=3D -1) { return true; @@ -412,7 +412,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, tb_lock(); acquired_tb_lock =3D true; } - if (!tb->invalid) { + if (!(tb->cflags & CF_INVALID)) { tb_add_jump(last_tb, tb_exit, tb); } } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index a7c1d4e3f2..ed65d68709 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1073,7 +1073,7 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page= _addr_t page_addr) =20 assert_tb_locked(); =20 - atomic_set(&tb->invalid, true); + atomic_set(&tb->cflags, tb->cflags | CF_INVALID); =20 /* remove the TB from the hash list */ phys_pc =3D tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); @@ -1269,7 +1269,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->flags =3D flags; tb->cflags =3D cflags; tb->trace_vcpu_dstate =3D *cpu->trace_dstate; - tb->invalid =3D false; =20 #ifdef CONFIG_PROFILER tcg_ctx.tb_count1++; /* includes aborted translations because of --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664292227541.7738189036469; Tue, 10 Oct 2017 12:38:12 -0700 (PDT) Received: from localhost ([::1]:36828 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Lq-0006Gn-Ou for importer@patchew.org; Tue, 10 Oct 2017 15:38:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58871) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20EX-0000jm-7h for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20ES-000551-KD for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:26 -0400 Received: from mail-pf0-x22f.google.com ([2607:f8b0:400e:c00::22f]:50211) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20ES-00054Y-DO for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:24 -0400 Received: by mail-pf0-x22f.google.com with SMTP id m63so18277315pfk.7 for ; Tue, 10 Oct 2017 12:30:22 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LAawtX8GSa0/i2pqKXJe98VeX6zP0igCbj0ZmpFAsd0=; b=R2RlmtJRj9w1kAvh50kLhqBTWXvpEHU44MmSdBZojYjzn+pW5301bHJpOEHYstmVoL yq27lNS9AD1WfJzUuIhVW078bxovxsIRi199+9r40JiW4REdn2LDKSRHJBhK5gn+ROwI BgcWb1yr9z2MvEb/VjTZHEl4M9HAdOpr3858s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LAawtX8GSa0/i2pqKXJe98VeX6zP0igCbj0ZmpFAsd0=; b=qF7XSGaSFOEgV/tt4RN9Q4PtqyRlRFb1XiFmh3QNUO74v/IofTftjSdzGZmabnrR4r 1qhXUhM4xMQnoDqvAIpj11YNM0ARDNDRhXxg7W9oPGteFAjDzvcfODTTrew6lUVdUAu8 41mJ1UJ8cMyEePtGoLQ1GRuT9WbxGolPIQWXe7IwHFz2KHuDFiXiTmqXXSMBjCLsk4wj Fy7zA9zaJVWabYI707tNb0k00hJhUdnWHGAlUFHDlGCygO0ObolnXhRhpbOteek01Ncx 2gMTfJtLBFic8Q43dtcQGRRxGcr088mW7H7IPx22+O3Dqe662Mbf+RqHfXQWDDEAZF9H tdog== X-Gm-Message-State: AMCzsaX/etP0DFwBWH95IarYh83Pgp8AQK7U0I/698lmtsplayHpBUek Cv80Xi7Pli7xgqFmaZlqfGP0we7gyes= X-Google-Smtp-Source: AOwi7QAtihgPimie+jJyk9mXmiKPrpnCi9eg+iZ8qxBo48wINsHbLjxt+QkcuHTQ9osxcHz3Ue8e5Q== X-Received: by 10.101.78.130 with SMTP id b2mr13067806pgs.160.1507663820909; Tue, 10 Oct 2017 12:30:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:29:54 -0700 Message-Id: <20171010193003.28857-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PULL v2 11/20] translate-all: define and use DEBUG_TB_FLUSH_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" This gets rid of some ifdef checks while ensuring that the debug code is compiled, which prevents bit rot. Suggested-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ed65d68709..799b027e79 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -65,6 +65,12 @@ /* make various TB consistency checks */ /* #define DEBUG_TB_CHECK */ =20 +#ifdef DEBUG_TB_FLUSH +#define DEBUG_TB_FLUSH_GATE 1 +#else +#define DEBUG_TB_FLUSH_GATE 0 +#endif + #if !defined(CONFIG_USER_ONLY) /* TB consistency checks only implemented for usermode emulation. */ #undef DEBUG_TB_CHECK @@ -899,13 +905,13 @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_dat= a tb_flush_count) goto done; } =20 -#if defined(DEBUG_TB_FLUSH) - printf("qemu: flush code_size=3D%ld nb_tbs=3D%d avg_tb_size=3D%ld\n", - (unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer), - tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? - ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer= )) / - tcg_ctx.tb_ctx.nb_tbs : 0); -#endif + if (DEBUG_TB_FLUSH_GATE) { + printf("qemu: flush code_size=3D%td nb_tbs=3D%d avg_tb_size=3D%td\= n", + tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, + tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? + (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) / + tcg_ctx.tb_ctx.nb_tbs : 0); + } if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { cpu_abort(cpu, "Internal error: code buffer overflow\n"); --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664625593950.4749536851923; Tue, 10 Oct 2017 12:43:45 -0700 (PDT) Received: from localhost ([::1]:36851 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20RA-0002Qt-2W for importer@patchew.org; Tue, 10 Oct 2017 15:43:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58926) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20EZ-0000mo-DW for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20ET-00055P-QX for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:31 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:54759) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20ET-00054m-Jy for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:25 -0400 Received: by mail-pf0-x233.google.com with SMTP id m28so13339949pfi.11 for ; Tue, 10 Oct 2017 12:30:23 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nCHgQRfd/6L6A+ZFLqYH/ozIQbUkersXx+TPVXfIV2w=; b=fWPlj9AbltdQtnuBqPNPux1kN2vFh8Kyc6GhMNgerN+Tck6b6EFEy6N1O/7pSmdy2u SG3ZHCALoJgC3lS77gqCkZwcjfApjShxbhC8vKsBvYXxdjrkPGFcgdcYAcONwdfeWpBp mDmQt3juUWsnxozpWKmjp4ld8Bw2PQb3EghY4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nCHgQRfd/6L6A+ZFLqYH/ozIQbUkersXx+TPVXfIV2w=; b=Nknr+K12G97lNvW1XRnMSFuk3R+RsGt8MaOeXbkZWTJv3aJ/Io9DEQUfIRPehICATz wm8haKATDVBeHJFmFIZhnpWxnvd6vmpyRgIR3MCdDnQ506IQjHRdT3SVELLrG/x5AGA7 elr70Awd14//OpGUvW6Z2BR5jV+h0XCagtNS7OYhoP+HtgDe/pL3me0++FSBuMjGQ+gz k5PdHq3ZMZm/zdhR4IkbT6MaedpdUhfjnpFU2RqM7/7puq3HBofK15M+fDGDFrU1UClE vYjB2DCTGa1LCU/vQGHvtI78+/c9cPoLyou1e6Ew0zVc3tRcc1i0IQ3LdTK04NSzeO8w vPIw== X-Gm-Message-State: AMCzsaX6rqAhEYIeTKw9kJks1rSYpAQI6DdTr3w8Cq6JId1fjIXz1eUA U7gA8K+sz5CJz26oG2owK2I0HIK/g4A= X-Google-Smtp-Source: AOwi7QC6bmoL69oh9hFA5qv54bdN++zziW0rosKQhlUtpqzA3czzXPQmk8Vt7CTMnU55YzSlM6i9Sg== X-Received: by 10.99.167.68 with SMTP id w4mr12937604pgo.390.1507663822260; Tue, 10 Oct 2017 12:30:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:29:55 -0700 Message-Id: <20171010193003.28857-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PULL v2 12/20] exec-all: introduce TB_PAGE_ADDR_FMT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" And fix the following warning when DEBUG_TB_INVALIDATE is enabled in translate-all.c: CC mipsn32-linux-user/accel/tcg/translate-all.o /data/src/qemu/accel/tcg/translate-all.c: In function =E2=80=98tb_alloc_pag= e=E2=80=99: /data/src/qemu/accel/tcg/translate-all.c:1201:16: error: format =E2=80=98%l= x=E2=80=99 expects argument of type =E2=80=98long unsigned int=E2=80=99, bu= t argument 2 has type =E2=80=98tb_page_addr_t {aka unsigned int}=E2=80=99 [= -Werror=3Dformat=3D] printf("protecting code page: 0x" TARGET_FMT_lx "\n", ^ cc1: all warnings being treated as errors /data/src/qemu/rules.mak:66: recipe for target 'accel/tcg/translate-all.o' = failed make[1]: *** [accel/tcg/translate-all.o] Error 1 Makefile:328: recipe for target 'subdir-mipsn32-linux-user' failed make: *** [subdir-mipsn32-linux-user] Error 2 cota@flamenco:/data/src/qemu/build ((18f3fe1...) *$)$ Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 2 ++ accel/tcg/translate-all.c | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 3135aaf4c9..79f8041811 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -31,8 +31,10 @@ type. */ #if defined(CONFIG_USER_ONLY) typedef abi_ulong tb_page_addr_t; +#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx #else typedef ram_addr_t tb_page_addr_t; +#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT #endif =20 #include "qemu/log.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 799b027e79..90b3eed9c6 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1193,8 +1193,7 @@ static inline void tb_alloc_page(TranslationBlock *tb, mprotect(g2h(page_addr), qemu_host_page_size, (prot & PAGE_BITS) & ~PAGE_WRITE); #ifdef DEBUG_TB_INVALIDATE - printf("protecting code page: 0x" TARGET_FMT_lx "\n", - page_addr); + printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr= ); #endif } #else --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664293261495.94682071544014; Tue, 10 Oct 2017 12:38:13 -0700 (PDT) Received: from localhost ([::1]:36829 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Lt-0006J1-CH for importer@patchew.org; Tue, 10 Oct 2017 15:38:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58877) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20EW-0000jx-Lr for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20EV-00055t-Ek for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:28 -0400 Received: from mail-pf0-x22b.google.com ([2607:f8b0:400e:c00::22b]:45681) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20EV-00054y-8n for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:27 -0400 Received: by mail-pf0-x22b.google.com with SMTP id d28so3569521pfe.2 for ; Tue, 10 Oct 2017 12:30:24 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WtXhE5x32c2lhsKUN0JsspH8di2RIEl9RhyDrTbaDsw=; b=SKaVOj5hTxQ36TQw/DGHWLcge9NjlIjnBkfurMhX+HGzKNW4eQnNVlSP8mYHCvlNkK WkWN/nUFRMe7i0fJM0xxixP3QKf68N8QXtAAVfeIeRsnpwU8KvtumcqbtR71dwpGJJ+i 3cJDtm4zyVM1+kJyzvfhjHK/a5H4p1zWoVqms= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WtXhE5x32c2lhsKUN0JsspH8di2RIEl9RhyDrTbaDsw=; b=ZHWl/I9nfpQTNniAexAOjBwob3GvNs7/hDqwmi0n3y8QNwchWaSC8kuPAgHFWTZeOo qAuLlk+bqRO+WL/Xjss1J6RfzjmJS1gkr74BiaBXj5LyNyQF48g0UDg+qPXbtwVoIZH7 LOiXgiuPjX32fOQTx1mIfWU/xo0HCy3kHDcw/BPEG5ZHNIvsjGLq2eNAsh+5uqz2F79O MifdE0LP+DCjAbQM+AqXbf1s/GWMo2E77LkBjOFhGlNXIrI2FvNQfAEzJ6TAzmsAdZko pgBqcbKq5mU3RWUXRGxWraw9tnI7/lRitjMksXJeutKChE8SLq+celUytVBNJRARodNo QHqA== X-Gm-Message-State: AMCzsaXE0qiPvnNJeVgj0LwWPSQBFzP8tT7z+ZuwXrOir1SAJAdVQNs9 PAlZbBYwaEQ+aUOsMm5g4KAf8btNZxg= X-Google-Smtp-Source: AOwi7QA9K5i3yAn2E6DXoFOTbei4V6l+W9d4oejZU9HVsmYK2gGrizxkTcAbGJ59H0+DHD3S99V/SQ== X-Received: by 10.84.205.69 with SMTP id o5mr13112094plh.122.1507663823825; Tue, 10 Oct 2017 12:30:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:29:56 -0700 Message-Id: <20171010193003.28857-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PULL v2 13/20] translate-all: define and use DEBUG_TB_INVALIDATE_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" This gets rid of an ifdef check while ensuring that the debug code is compiled, which prevents bit rot. Suggested-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 90b3eed9c6..6b853b329c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -65,6 +65,12 @@ /* make various TB consistency checks */ /* #define DEBUG_TB_CHECK */ =20 +#ifdef DEBUG_TB_INVALIDATE +#define DEBUG_TB_INVALIDATE_GATE 1 +#else +#define DEBUG_TB_INVALIDATE_GATE 0 +#endif + #ifdef DEBUG_TB_FLUSH #define DEBUG_TB_FLUSH_GATE 1 #else @@ -1192,9 +1198,9 @@ static inline void tb_alloc_page(TranslationBlock *tb, } mprotect(g2h(page_addr), qemu_host_page_size, (prot & PAGE_BITS) & ~PAGE_WRITE); -#ifdef DEBUG_TB_INVALIDATE - printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr= ); -#endif + if (DEBUG_TB_INVALIDATE_GATE) { + printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_= addr); + } } #else /* if some code is already present, then the pages are already --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150766429307196.67132480123598; Tue, 10 Oct 2017 12:38:13 -0700 (PDT) Received: from localhost ([::1]:36827 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Lp-0006FO-RA for importer@patchew.org; Tue, 10 Oct 2017 15:38:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58905) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20EX-0000l4-MU for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20EW-00056M-MM for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:29 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:50211) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20EW-00055T-Gs for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:28 -0400 Received: by mail-pf0-x233.google.com with SMTP id m63so18277566pfk.7 for ; Tue, 10 Oct 2017 12:30:26 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PULL v2 14/20] translate-all: define and use DEBUG_TB_CHECK_GATE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" This prevents bit rot by ensuring the debug code is compiled when building a user-mode target. Unfortunately the helpers are user-mode-only so we cannot fully get rid of the ifdef checks. Add a comment to explain this. Suggested-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/translate-all.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 6b853b329c..26efad302d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -82,6 +82,12 @@ #undef DEBUG_TB_CHECK #endif =20 +#ifdef DEBUG_TB_CHECK +#define DEBUG_TB_CHECK_GATE 1 +#else +#define DEBUG_TB_CHECK_GATE 0 +#endif + /* Access to the various translations structures need to be serialised via= locks * for consistency. This is automatic for SoftMMU based system * emulation due to its single threaded nature. In user-mode emulation @@ -950,7 +956,13 @@ void tb_flush(CPUState *cpu) } } =20 -#ifdef DEBUG_TB_CHECK +/* + * Formerly ifdef DEBUG_TB_CHECK. These debug functions are user-mode-only, + * so in order to prevent bit rot we compile them unconditionally in user-= mode, + * and let the optimizer get rid of them by wrapping their user-only calle= rs + * with if (DEBUG_TB_CHECK_GATE). + */ +#ifdef CONFIG_USER_ONLY =20 static void do_tb_invalidate_check(struct qht *ht, void *p, uint32_t hash, void *userp) @@ -994,7 +1006,7 @@ static void tb_page_check(void) qht_iter(&tcg_ctx.tb_ctx.htable, do_tb_page_check, NULL); } =20 -#endif +#endif /* CONFIG_USER_ONLY */ =20 static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock= *tb) { @@ -1236,8 +1248,10 @@ static void tb_link_page(TranslationBlock *tb, tb_pa= ge_addr_t phys_pc, h =3D tb_hash_func(phys_pc, tb->pc, tb->flags, tb->trace_vcpu_dstate); qht_insert(&tcg_ctx.tb_ctx.htable, tb, h); =20 -#ifdef DEBUG_TB_CHECK - tb_page_check(); +#ifdef CONFIG_USER_ONLY + if (DEBUG_TB_CHECK_GATE) { + tb_page_check(); + } #endif } =20 @@ -2223,8 +2237,10 @@ int page_unprotect(target_ulong address, uintptr_t p= c) /* and since the content will be modified, we must invalidate the corresponding translated code. */ current_tb_invalidated |=3D tb_invalidate_phys_page(addr, pc); -#ifdef DEBUG_TB_CHECK - tb_invalidate_check(addr); +#ifdef CONFIG_USER_ONLY + if (DEBUG_TB_CHECK_GATE) { + tb_invalidate_check(addr); + } #endif } mprotect((void *)g2h(host_start), qemu_host_page_size, --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664889009729.4958173178946; Tue, 10 Oct 2017 12:48:09 -0700 (PDT) Received: from localhost ([::1]:36875 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20VX-000627-9n for importer@patchew.org; Tue, 10 Oct 2017 15:48:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58942) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Eb-0000oh-7I for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20EX-00056Y-0e for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:33 -0400 Received: from mail-pf0-x22f.google.com ([2607:f8b0:400e:c00::22f]:47078) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20EW-00055l-Pl for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:28 -0400 Received: by mail-pf0-x22f.google.com with SMTP id p87so9225136pfj.3 for ; Tue, 10 Oct 2017 12:30:27 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yvehDTJT52The5SOdJt0x6s/jRMheKd5KLpLoVOTPQ4=; b=ihfLYsAz72s5wjm0FekvHAL6uHRJkXUKIpQmh4mO9AhEzMyBdFj6qkGlnuzwA9V3d1 ogADDBx2Udr4kmx7l1mFrh0zKvBcfCgzbjB2wF0MfUBX0Yt0ZCLMbKM2p/N5IPIHYnOY eeWyCAoOZiW/QWOm7NA8j1R/NxhryWUV3SrDw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yvehDTJT52The5SOdJt0x6s/jRMheKd5KLpLoVOTPQ4=; b=V6cjzXwuSZShidbYq+h5utVhm5JRIXgCKRR3MDOIzWKe9JhSvmcFITa6XQc0s6lwMH al3DFR5W1b0QuHlGiQKDeYsNuvaae6nWuKcayDlqA15Mt8NCx4O+tWmqarpod3Rhs/1s AWK5vt1EUAo+kBFJ6URm4O+H6ywnRPOLd2562EcrLXvg1li8kLMKVCHWRTAoN3CkAHrj z62+vMVxB3Yy7AmZVQ1ssovYl4/9fnizUzN7zjYsJrNu1dJn9CWs84M07Hhuc/SoI2yL fCkDEFptLYsGeP2hChMdKG8zg/eV3Z/YeqTKmav9OzWBEcH1p6XJNYcZ9h7D4sXxhCKp FzEw== X-Gm-Message-State: AMCzsaUk+eRLUH1Wj8LqM7nzHEXXtU36rcPqWX+oycjEMXwOPetBDVsD pqJA6GZJVN5VwrQP7fB0Ow6dA7Td1DY= X-Google-Smtp-Source: AOwi7QDSpdTbJNoBGzwxIVNMrLJ/c4/9rBA8Wn5FJpkg6cOPtBM+EHt3GhckWtzRVpm19co32HdFDA== X-Received: by 10.84.191.129 with SMTP id a1mr12698131pld.272.1507663826483; Tue, 10 Oct 2017 12:30:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:29:58 -0700 Message-Id: <20171010193003.28857-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PULL v2 15/20] exec-all: extract tb->tc_* into a separate struct tc_tb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" In preparation for adding tc.size to be able to keep track of TB's using the binary search tree implementation from glib. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ++++++++++-- accel/tcg/cpu-exec.c | 14 +++++++------- accel/tcg/tcg-runtime.c | 4 ++-- accel/tcg/translate-all.c | 24 ++++++++++++------------ tcg/tcg.c | 4 ++-- 5 files changed, 33 insertions(+), 25 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 79f8041811..53f1835c43 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -303,6 +303,14 @@ static inline void tb_invalidate_phys_addr(AddressSpac= e *as, hwaddr addr) #define CODE_GEN_AVG_BLOCK_SIZE 150 #endif =20 +/* + * Translation Cache-related fields of a TB. + */ +struct tb_tc { + void *ptr; /* pointer to the translated code */ + uint8_t *search; /* pointer to search data */ +}; + struct TranslationBlock { target_ulong pc; /* simulated PC corresponding to this block (EIP + = CS base) */ target_ulong cs_base; /* CS base for this block */ @@ -321,8 +329,8 @@ struct TranslationBlock { /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; =20 - void *tc_ptr; /* pointer to the translated code */ - uint8_t *tc_search; /* pointer to search data */ + struct tb_tc tc; + /* original tb when cflags has CF_NOCACHE */ struct TranslationBlock *orig_tb; /* first and second physical page containing code. The lower bit diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 9cd809d607..363dfa208a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -143,11 +143,11 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *= cpu, TranslationBlock *itb) uintptr_t ret; TranslationBlock *last_tb; int tb_exit; - uint8_t *tb_ptr =3D itb->tc_ptr; + uint8_t *tb_ptr =3D itb->tc.ptr; =20 qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc, "Trace %p [%d: " TARGET_FMT_lx "] %s\n", - itb->tc_ptr, cpu->cpu_index, itb->pc, + itb->tc.ptr, cpu->cpu_index, itb->pc, lookup_symbol(itb->pc)); =20 #if defined(DEBUG_DISAS) @@ -179,7 +179,7 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cp= u, TranslationBlock *itb) qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc, "Stopped execution of TB chain before %p [" TARGET_FMT_lx "] %s\n", - last_tb->tc_ptr, last_tb->pc, + last_tb->tc.ptr, last_tb->pc, lookup_symbol(last_tb->pc)); if (cc->synchronize_from_tb) { cc->synchronize_from_tb(cpu, last_tb); @@ -334,7 +334,7 @@ void tb_set_jmp_target(TranslationBlock *tb, int n, uin= tptr_t addr) { if (TCG_TARGET_HAS_direct_jump) { uintptr_t offset =3D tb->jmp_target_arg[n]; - uintptr_t tc_ptr =3D (uintptr_t)tb->tc_ptr; + uintptr_t tc_ptr =3D (uintptr_t)tb->tc.ptr; tb_target_set_jmp_target(tc_ptr, tc_ptr + offset, addr); } else { tb->jmp_target_arg[n] =3D addr; @@ -354,11 +354,11 @@ static inline void tb_add_jump(TranslationBlock *tb, = int n, qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, "Linking TBs %p [" TARGET_FMT_lx "] index %d -> %p [" TARGET_FMT_lx "]\n", - tb->tc_ptr, tb->pc, n, - tb_next->tc_ptr, tb_next->pc); + tb->tc.ptr, tb->pc, n, + tb_next->tc.ptr, tb_next->pc); =20 /* patch the native jump address */ - tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); + tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc.ptr); =20 /* add in TB jmp circular list */ tb->jmp_list_next[n] =3D tb_next->jmp_list_first; diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index d0edd944b0..54d89100d9 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -157,9 +157,9 @@ void *HELPER(lookup_tb_ptr)(CPUArchState *env) } qemu_log_mask_and_addr(CPU_LOG_EXEC, pc, "Chain %p [%d: " TARGET_FMT_lx "] %s\n", - tb->tc_ptr, cpu->cpu_index, pc, + tb->tc.ptr, cpu->cpu_index, pc, lookup_symbol(pc)); - return tb->tc_ptr; + return tb->tc.ptr; } =20 void HELPER(exit_atomic)(CPUArchState *env) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 26efad302d..c5ce99d549 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -260,7 +260,7 @@ static target_long decode_sleb128(uint8_t **pp) which comes from the host pc of the end of the code implementing the in= sn. =20 Each line of the table is encoded as sleb128 deltas from the previous - line. The seed for the first line is { tb->pc, 0..., tb->tc_ptr }. + line. The seed for the first line is { tb->pc, 0..., tb->tc.ptr }. That is, the first column is seeded with the guest pc, the last column with the host pc, and the middle columns with zeros. */ =20 @@ -270,7 +270,7 @@ static int encode_search(TranslationBlock *tb, uint8_t = *block) uint8_t *p =3D block; int i, j, n; =20 - tb->tc_search =3D block; + tb->tc.search =3D block; =20 for (i =3D 0, n =3D tb->icount; i < n; ++i) { target_ulong prev; @@ -305,9 +305,9 @@ static int cpu_restore_state_from_tb(CPUState *cpu, Tra= nslationBlock *tb, uintptr_t searched_pc) { target_ulong data[TARGET_INSN_START_WORDS] =3D { tb->pc }; - uintptr_t host_pc =3D (uintptr_t)tb->tc_ptr; + uintptr_t host_pc =3D (uintptr_t)tb->tc.ptr; CPUArchState *env =3D cpu->env_ptr; - uint8_t *p =3D tb->tc_search; + uint8_t *p =3D tb->tc.search; int i, j, num_insns =3D tb->icount; #ifdef CONFIG_PROFILER int64_t ti =3D profile_getclock(); @@ -858,7 +858,7 @@ void tb_free(TranslationBlock *tb) tb =3D=3D tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs - 1]) { size_t struct_size =3D ROUND_UP(sizeof(*tb), qemu_icache_linesize); =20 - tcg_ctx.code_gen_ptr =3D tb->tc_ptr - struct_size; + tcg_ctx.code_gen_ptr =3D tb->tc.ptr - struct_size; tcg_ctx.tb_ctx.nb_tbs--; } } @@ -1059,7 +1059,7 @@ static inline void tb_remove_from_jmp_list(Translatio= nBlock *tb, int n) another TB */ static inline void tb_reset_jump(TranslationBlock *tb, int n) { - uintptr_t addr =3D (uintptr_t)(tb->tc_ptr + tb->jmp_reset_offset[n]); + uintptr_t addr =3D (uintptr_t)(tb->tc.ptr + tb->jmp_reset_offset[n]); tb_set_jmp_target(tb, n, addr); } =20 @@ -1288,7 +1288,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } =20 gen_code_buf =3D tcg_ctx.code_gen_ptr; - tb->tc_ptr =3D gen_code_buf; + tb->tc.ptr =3D gen_code_buf; tb->pc =3D pc; tb->cs_base =3D cs_base; tb->flags =3D flags; @@ -1307,7 +1307,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, gen_intermediate_code(cpu, tb); tcg_ctx.cpu =3D NULL; =20 - trace_translate_block(tb, tb->pc, tb->tc_ptr); + trace_translate_block(tb, tb->pc, tb->tc.ptr); =20 /* generate machine code */ tb->jmp_reset_offset[0] =3D TB_JMP_RESET_OFFSET_INVALID; @@ -1354,11 +1354,11 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qemu_log_lock(); qemu_log("OUT: [size=3D%d]\n", gen_code_size); if (tcg_ctx.data_gen_ptr) { - size_t code_size =3D tcg_ctx.data_gen_ptr - tb->tc_ptr; + size_t code_size =3D tcg_ctx.data_gen_ptr - tb->tc.ptr; size_t data_size =3D gen_code_size - code_size; size_t i; =20 - log_disas(tb->tc_ptr, code_size); + log_disas(tb->tc.ptr, code_size); =20 for (i =3D 0; i < data_size; i +=3D sizeof(tcg_target_ulong)) { if (sizeof(tcg_target_ulong) =3D=3D 8) { @@ -1372,7 +1372,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } } } else { - log_disas(tb->tc_ptr, gen_code_size); + log_disas(tb->tc.ptr, gen_code_size); } qemu_log("\n"); qemu_log_flush(); @@ -1699,7 +1699,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) while (m_min <=3D m_max) { m =3D (m_min + m_max) >> 1; tb =3D tcg_ctx.tb_ctx.tbs[m]; - v =3D (uintptr_t)tb->tc_ptr; + v =3D (uintptr_t)tb->tc.ptr; if (v =3D=3D tc_ptr) { return tb; } else if (tc_ptr < v) { diff --git a/tcg/tcg.c b/tcg/tcg.c index dff9999bc6..a874bdd41f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2836,8 +2836,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 tcg_reg_alloc_start(s); =20 - s->code_buf =3D tb->tc_ptr; - s->code_ptr =3D tb->tc_ptr; + s->code_buf =3D tb->tc.ptr; + s->code_ptr =3D tb->tc.ptr; =20 #ifdef TCG_TARGET_NEED_LDST_LABELS s->ldst_labels =3D NULL; --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664643557407.6839205120789; Tue, 10 Oct 2017 12:44:03 -0700 (PDT) Received: from localhost ([::1]:36853 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20RV-0002g2-JJ for importer@patchew.org; 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X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PULL v2 16/20] tci: move tci_regs to tcg_qemu_tb_exec's stack X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. Compile-tested for all targets on an x86_64 host. Suggested-by: Richard Henderson Acked-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tci.c | 552 +++++++++++++++++++++++++++++++---------------------------= ---- 1 file changed, 279 insertions(+), 273 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index f39bfb95c0..63f2cd54ab 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -55,93 +55,95 @@ typedef uint64_t (*helper_function)(tcg_target_ulong, t= cg_target_ulong, tcg_target_ulong); #endif =20 -static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS]; - -static tcg_target_ulong tci_read_reg(TCGReg index) +static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg = index) { - tci_assert(index < ARRAY_SIZE(tci_reg)); - return tci_reg[index]; + tci_assert(index < TCG_TARGET_NB_REGS); + return regs[index]; } =20 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(TCGReg index) +static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index) { - return (int8_t)tci_read_reg(index); + return (int8_t)tci_read_reg(regs, index); } #endif =20 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(TCGReg index) +static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) { - return (int16_t)tci_read_reg(index); + return (int16_t)tci_read_reg(regs, index); } #endif =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static int32_t tci_read_reg32s(TCGReg index) +static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) { - return (int32_t)tci_read_reg(index); + return (int32_t)tci_read_reg(regs, index); } #endif =20 -static uint8_t tci_read_reg8(TCGReg index) +static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index) { - return (uint8_t)tci_read_reg(index); + return (uint8_t)tci_read_reg(regs, index); } =20 -static uint16_t tci_read_reg16(TCGReg index) +static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) { - return (uint16_t)tci_read_reg(index); + return (uint16_t)tci_read_reg(regs, index); } =20 -static uint32_t tci_read_reg32(TCGReg index) +static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) { - return (uint32_t)tci_read_reg(index); + return (uint32_t)tci_read_reg(regs, index); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static uint64_t tci_read_reg64(TCGReg index) +static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { - return tci_read_reg(index); + return tci_read_reg(regs, index); } #endif =20 -static void tci_write_reg(TCGReg index, tcg_target_ulong value) +static void +tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { - tci_assert(index < ARRAY_SIZE(tci_reg)); + tci_assert(index < TCG_TARGET_NB_REGS); tci_assert(index !=3D TCG_AREG0); tci_assert(index !=3D TCG_REG_CALL_STACK); - tci_reg[index] =3D value; + regs[index] =3D value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static void tci_write_reg32s(TCGReg index, int32_t value) +static void +tci_write_reg32s(tcg_target_ulong *regs, TCGReg index, int32_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } #endif =20 -static void tci_write_reg8(TCGReg index, uint8_t value) +static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t v= alue) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } =20 -static void tci_write_reg32(TCGReg index, uint32_t value) +static void +tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 -static void tci_write_reg64(uint32_t high_index, uint32_t low_index, - uint64_t value) +static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, + uint32_t low_index, uint64_t value) { - tci_write_reg(low_index, value); - tci_write_reg(high_index, value >> 32); + tci_write_reg(regs, low_index, value); + tci_write_reg(regs, high_index, value >> 32); } #elif TCG_TARGET_REG_BITS =3D=3D 64 -static void tci_write_reg64(TCGReg index, uint64_t value) +static void +tci_write_reg64(tcg_target_ulong *regs, TCGReg index, uint64_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } #endif =20 @@ -188,94 +190,97 @@ static uint64_t tci_read_i64(uint8_t **tb_ptr) #endif =20 /* Read indexed register (native size) from bytecode. */ -static tcg_target_ulong tci_read_r(uint8_t **tb_ptr) +static tcg_target_ulong +tci_read_r(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - tcg_target_ulong value =3D tci_read_reg(**tb_ptr); + tcg_target_ulong value =3D tci_read_reg(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 /* Read indexed register (8 bit) from bytecode. */ -static uint8_t tci_read_r8(uint8_t **tb_ptr) +static uint8_t tci_read_r8(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - uint8_t value =3D tci_read_reg8(**tb_ptr); + uint8_t value =3D tci_read_reg8(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 /* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(uint8_t **tb_ptr) +static int8_t tci_read_r8s(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - int8_t value =3D tci_read_reg8s(**tb_ptr); + int8_t value =3D tci_read_reg8s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register (16 bit) from bytecode. */ -static uint16_t tci_read_r16(uint8_t **tb_ptr) +static uint16_t tci_read_r16(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint16_t value =3D tci_read_reg16(**tb_ptr); + uint16_t value =3D tci_read_reg16(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 /* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(uint8_t **tb_ptr) +static int16_t tci_read_r16s(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - int16_t value =3D tci_read_reg16s(**tb_ptr); + int16_t value =3D tci_read_reg16s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register (32 bit) from bytecode. */ -static uint32_t tci_read_r32(uint8_t **tb_ptr) +static uint32_t tci_read_r32(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint32_t value =3D tci_read_reg32(**tb_ptr); + uint32_t value =3D tci_read_reg32(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 /* Read two indexed registers (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_r64(uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint32_t low =3D tci_read_r32(tb_ptr); - return tci_uint64(tci_read_r32(tb_ptr), low); + uint32_t low =3D tci_read_r32(regs, tb_ptr); + return tci_uint64(tci_read_r32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(uint8_t **tb_ptr) +static int32_t tci_read_r32s(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - int32_t value =3D tci_read_reg32s(**tb_ptr); + int32_t value =3D tci_read_reg32s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 /* Read indexed register (64 bit) from bytecode. */ -static uint64_t tci_read_r64(uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint64_t value =3D tci_read_reg64(**tb_ptr); + uint64_t value =3D tci_read_reg64(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register(s) with target address from bytecode. */ -static target_ulong tci_read_ulong(uint8_t **tb_ptr) +static target_ulong +tci_read_ulong(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - target_ulong taddr =3D tci_read_r(tb_ptr); + target_ulong taddr =3D tci_read_r(regs, tb_ptr); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr +=3D (uint64_t)tci_read_r(tb_ptr) << 32; + taddr +=3D (uint64_t)tci_read_r(regs, tb_ptr) << 32; #endif return taddr; } =20 /* Read indexed register or constant (native size) from bytecode. */ -static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) +static tcg_target_ulong +tci_read_ri(const tcg_target_ulong *regs, uint8_t **tb_ptr) { tcg_target_ulong value; TCGReg r =3D **tb_ptr; @@ -283,13 +288,13 @@ static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i(tb_ptr); } else { - value =3D tci_read_reg(r); + value =3D tci_read_reg(regs, r); } return value; } =20 /* Read indexed register or constant (32 bit) from bytecode. */ -static uint32_t tci_read_ri32(uint8_t **tb_ptr) +static uint32_t tci_read_ri32(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { uint32_t value; TCGReg r =3D **tb_ptr; @@ -297,21 +302,21 @@ static uint32_t tci_read_ri32(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i32(tb_ptr); } else { - value =3D tci_read_reg32(r); + value =3D tci_read_reg32(regs, r); } return value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_ri64(uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { - uint32_t low =3D tci_read_ri32(tb_ptr); - return tci_uint64(tci_read_ri32(tb_ptr), low); + uint32_t low =3D tci_read_ri32(regs, tb_ptr); + return tci_uint64(tci_read_ri32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register or constant (64 bit) from bytecode. */ -static uint64_t tci_read_ri64(uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { uint64_t value; TCGReg r =3D **tb_ptr; @@ -319,7 +324,7 @@ static uint64_t tci_read_ri64(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i64(tb_ptr); } else { - value =3D tci_read_reg64(r); + value =3D tci_read_reg64(regs, r); } return value; } @@ -465,12 +470,13 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, T= CGCond condition) /* Interpret pseudo code in tb. */ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) { + tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value =3D (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); uintptr_t ret =3D 0; =20 - tci_reg[TCG_AREG0] =3D (tcg_target_ulong)env; - tci_reg[TCG_REG_CALL_STACK] =3D sp_value; + regs[TCG_AREG0] =3D (tcg_target_ulong)env; + regs[TCG_REG_CALL_STACK] =3D sp_value; tci_assert(tb_ptr); =20 for (;;) { @@ -503,27 +509,27 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 switch (opc) { case INDEX_op_call: - t0 =3D tci_read_ri(&tb_ptr); + t0 =3D tci_read_ri(regs, &tb_ptr); #if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D ((helper_function)t0)(tci_read_reg(TCG_REG_R0), - tci_read_reg(TCG_REG_R1), - tci_read_reg(TCG_REG_R2), - tci_read_reg(TCG_REG_R3), - tci_read_reg(TCG_REG_R5), - tci_read_reg(TCG_REG_R6), - tci_read_reg(TCG_REG_R7), - tci_read_reg(TCG_REG_R8), - tci_read_reg(TCG_REG_R9), - tci_read_reg(TCG_REG_R10)); - tci_write_reg(TCG_REG_R0, tmp64); - tci_write_reg(TCG_REG_R1, tmp64 >> 32); + tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R5), + tci_read_reg(regs, TCG_REG_R6), + tci_read_reg(regs, TCG_REG_R7), + tci_read_reg(regs, TCG_REG_R8), + tci_read_reg(regs, TCG_REG_R9), + tci_read_reg(regs, TCG_REG_R10)); + tci_write_reg(regs, TCG_REG_R0, tmp64); + tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else - tmp64 =3D ((helper_function)t0)(tci_read_reg(TCG_REG_R0), - tci_read_reg(TCG_REG_R1), - tci_read_reg(TCG_REG_R2), - tci_read_reg(TCG_REG_R3), - tci_read_reg(TCG_REG_R5)); - tci_write_reg(TCG_REG_R0, tmp64); + tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R5)); + tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; case INDEX_op_br: @@ -533,46 +539,46 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) continue; case INDEX_op_setcond_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg32(t0, tci_compare32(t1, t2, condition)); + tci_write_reg32(regs, t0, tci_compare32(t1, t2, condition)); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: t0 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - v64 =3D tci_read_ri64(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + v64 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg32(t0, tci_compare64(tmp64, v64, condition)); + tci_write_reg32(regs, t0, tci_compare64(tmp64, v64, condition)= ); break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg64(t0, tci_compare64(t1, t2, condition)); + tci_write_reg64(regs, t0, tci_compare64(t1, t2, condition)); break; #endif case INDEX_op_mov_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; case INDEX_op_movi_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_i32(&tb_ptr); - tci_write_reg32(t0, t1); + tci_write_reg32(regs, t0, t1); break; =20 /* Load/store operations (32 bit). */ =20 case INDEX_op_ld8u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg8(t0, *(uint8_t *)(t1 + t2)); + tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: @@ -583,25 +589,25 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) break; case INDEX_op_ld_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32(t0, *(uint32_t *)(t1 + t2)); + tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_st8_i32: - t0 =3D tci_read_r8(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r8(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; case INDEX_op_st16_i32: - t0 =3D tci_read_r16(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i32: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_assert(t1 !=3D sp_value || (int32_t)t2 < 0); *(uint32_t *)(t1 + t2) =3D t0; @@ -611,46 +617,46 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 case INDEX_op_add_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 + t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 + t2); break; case INDEX_op_sub_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 - t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 - t2); break; case INDEX_op_mul_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 * t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i32 case INDEX_op_div_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 / t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 / t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 % t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 % t2); break; #elif TCG_TARGET_HAS_div2_i32 case INDEX_op_div2_i32: @@ -660,71 +666,71 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) #endif case INDEX_op_and_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 & t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 & t2); break; case INDEX_op_or_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 | t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 | t2); break; case INDEX_op_xor_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 ^ t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 ^ t2); break; =20 /* Shift/rotate operations (32 bit). */ =20 case INDEX_op_shl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 << (t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 >> (t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31))); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ((int32_t)t1 >> (t2 & 31))); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, rol32(t1, t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, ror32(t1, t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - t2 =3D tci_read_r32(&tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp32 =3D (((1 << tmp8) - 1) << tmp16); - tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32)); + tci_write_reg32(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp= 32)); break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_ri32(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_ri32(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -737,20 +743,20 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) case INDEX_op_add2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - tmp64 +=3D tci_read_r64(&tb_ptr); - tci_write_reg64(t1, t0, tmp64); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + tmp64 +=3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_sub2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - tmp64 -=3D tci_read_r64(&tb_ptr); - tci_write_reg64(t1, t0, tmp64); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + tmp64 -=3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_brcond2_i32: - tmp64 =3D tci_read_r64(&tb_ptr); - v64 =3D tci_read_ri64(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + v64 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(tmp64, v64, condition)) { @@ -762,86 +768,86 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) case INDEX_op_mulu2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - t2 =3D tci_read_r32(&tb_ptr); - tmp64 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t1, t0, t2 * tmp64); + t2 =3D tci_read_r32(regs, &tb_ptr); + tmp64 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 case INDEX_op_ext8s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r8s(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 case INDEX_op_ext16s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r16s(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 case INDEX_op_ext8u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r8(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 case INDEX_op_ext16u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 case INDEX_op_bswap16_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg32(t0, bswap16(t1)); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg32(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i32 case INDEX_op_bswap32_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, bswap32(t1)); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 case INDEX_op_not_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, ~t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 case INDEX_op_neg_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, -t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, -t1); break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_mov_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; case INDEX_op_movi_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_i64(&tb_ptr); - tci_write_reg64(t0, t1); + tci_write_reg64(regs, t0, t1); break; =20 /* Load/store operations (64 bit). */ =20 case INDEX_op_ld8u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg8(t0, *(uint8_t *)(t1 + t2)); + tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i64: case INDEX_op_ld16u_i64: @@ -850,43 +856,43 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) break; case INDEX_op_ld32u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32(t0, *(uint32_t *)(t1 + t2)); + tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_ld32s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32s(t0, *(int32_t *)(t1 + t2)); + tci_write_reg32s(regs, t0, *(int32_t *)(t1 + t2)); break; case INDEX_op_ld_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg64(t0, *(uint64_t *)(t1 + t2)); + tci_write_reg64(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st8_i64: - t0 =3D tci_read_r8(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r8(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; case INDEX_op_st16_i64: - t0 =3D tci_read_r16(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st32_i64: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i64: - t0 =3D tci_read_r64(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_assert(t1 !=3D sp_value || (int32_t)t2 < 0); *(uint64_t *)(t1 + t2) =3D t0; @@ -896,21 +902,21 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 case INDEX_op_add_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 + t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 - t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 * t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i64 case INDEX_op_div_i64: @@ -927,71 +933,71 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) #endif case INDEX_op_and_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 & t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 | t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 ^ t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 ^ t2); break; =20 /* Shift/rotate operations (64 bit). */ =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 << (t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 >> (t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63))); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, rol64(t1, t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, ror64(t1, t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - t2 =3D tci_read_r64(&tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64)); + tci_write_reg64(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp= 64)); break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_r64(&tb_ptr); - t1 =3D tci_read_ri64(&tb_ptr); + t0 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -1003,29 +1009,29 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) #if TCG_TARGET_HAS_ext8u_i64 case INDEX_op_ext8u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r8(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r8s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r16s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64 case INDEX_op_ext16u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext32s_i64 @@ -1033,50 +1039,50 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) #endif case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r32s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: #endif case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg64(t0, bswap16(t1)); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i64 case INDEX_op_bswap32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t0, bswap32(t1)); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, bswap64(t1)); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, ~t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, -t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, -t1); break; #endif #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ @@ -1097,7 +1103,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) continue; case INDEX_op_qemu_ld_i32: t0 =3D *tb_ptr++; - taddr =3D tci_read_ulong(&tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -1127,14 +1133,14 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) default: tcg_abort(); } - tci_write_reg(t0, tmp32); + tci_write_reg(regs, t0, tmp32); break; case INDEX_op_qemu_ld_i64: t0 =3D *tb_ptr++; if (TCG_TARGET_REG_BITS =3D=3D 32) { t1 =3D *tb_ptr++; } - taddr =3D tci_read_ulong(&tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -1176,14 +1182,14 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) default: tcg_abort(); } - tci_write_reg(t0, tmp64); + tci_write_reg(regs, t0, tmp64); if (TCG_TARGET_REG_BITS =3D=3D 32) { - tci_write_reg(t1, tmp64 >> 32); + tci_write_reg(regs, t1, tmp64 >> 32); } break; case INDEX_op_qemu_st_i32: - t0 =3D tci_read_r(&tb_ptr); - taddr =3D tci_read_ulong(&tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: @@ -1206,8 +1212,8 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) } break; case INDEX_op_qemu_st_i64: - tmp64 =3D tci_read_r64(&tb_ptr); - taddr =3D tci_read_ulong(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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[97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ebVXYo9xSf9+M5MN2bcKmd/IRQv/NN06okyxN5KTf2Q=; b=aCkGXzcplSjdonFm/EZPN8Lq7JM1BQ35PjWcZAlS09l/dpxNGP37KJqXqE93sVo5fT UU/2QcVRalUe2jpBAb/jUSvZfGT048tEIyEUQTScPNbUQG0Lfl1SASANkSm9BRqAiNBl 8Ntt5DmjIT8LYHkc23vTCyHuz2Amz94ZyN/qo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ebVXYo9xSf9+M5MN2bcKmd/IRQv/NN06okyxN5KTf2Q=; b=MYYzdjnpBAg02mDXjiOmQSQ7ml5vqmNYaDa/vvLZ321SvTuLtBRLpY2JgGv2ez2HYF oQkHzqoQU009qN3UCl4wHsem3cbWeT4trr7NC9IhzyAOmIb2zQlCIvWSrA0EU+cGWGt3 6CMk90c7cs8gZaoWLpWIVN+Gm/glXciKPjbPObtpSHeK89d3LaMrh3BrM2uhUsXjHGFN +gsMii1fU3D+8puI5Fp8cmHnqHV0pXHbmXacFXT5mjzs+1HF0KJpf98ap1oEW8MvYPoY q4YXNTAkG7P7zg6mmqF4hZMr1FDaeaOtzZJTBGiweg2UfeB//buKqJHhiNkszRbAYy8R lxJQ== X-Gm-Message-State: AMCzsaU+BoUtEGRWDe85rbWZ8bmA0ZosbX9/aSESMtOWKkQevQ80GlCs IJvvvbC/g1lNQMfLlWH8+STqHA/udWI= X-Google-Smtp-Source: AOwi7QBe0l4rXy7RQSmf4Dv58RXAUj5bYDVeG7wS9pEvgltS03wvqEPHDP8KB+qbdMQitZ0Ok1+kjw== X-Received: by 10.98.185.10 with SMTP id z10mr127287pfe.8.1507663829171; Tue, 10 Oct 2017 12:30:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:30:00 -0700 Message-Id: <20171010193003.28857-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PULL v2 17/20] tcg: take .helpers out of TCGContext X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Groundwork for supporting multiple TCG contexts. The hash table becomes read-only after it is filled in, so we can save space by keeping just a global pointer to it. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tcg.h | 2 -- tcg/tcg.c | 10 +++++----- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 25662c36d4..b2d42e3136 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -656,8 +656,6 @@ struct TCGContext { =20 tcg_insn_unit *code_ptr; =20 - GHashTable *helpers; - #ifdef CONFIG_PROFILER /* profiling info */ int64_t tb_count1; diff --git a/tcg/tcg.c b/tcg/tcg.c index a874bdd41f..ee60798438 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -318,6 +318,7 @@ typedef struct TCGHelperInfo { static const TCGHelperInfo all_helpers[] =3D { #include "exec/helper-tcg.h" }; +static GHashTable *helper_table; =20 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)= ]; static void process_op_defs(TCGContext *s); @@ -328,7 +329,6 @@ void tcg_context_init(TCGContext *s) TCGOpDef *def; TCGArgConstraint *args_ct; int *sorted_args; - GHashTable *helper_table; =20 memset(s, 0, sizeof(*s)); s->nb_globals =3D 0; @@ -356,7 +356,7 @@ void tcg_context_init(TCGContext *s) =20 /* Register helpers. */ /* Use g_direct_hash/equal for direct pointer comparisons on func. */ - s->helpers =3D helper_table =3D g_hash_table_new(NULL, NULL); + helper_table =3D g_hash_table_new(NULL, NULL); =20 for (i =3D 0; i < ARRAY_SIZE(all_helpers); ++i) { g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func, @@ -982,7 +982,7 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg re= t, unsigned sizemask, flags; TCGHelperInfo *info; =20 - info =3D g_hash_table_lookup(s->helpers, (gpointer)func); + info =3D g_hash_table_lookup(helper_table, (gpointer)func); flags =3D info->flags; sizemask =3D info->sizemask; =20 @@ -1211,8 +1211,8 @@ static char *tcg_get_arg_str_idx(TCGContext *s, char = *buf, static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) { const char *ret =3D NULL; - if (s->helpers) { - TCGHelperInfo *info =3D g_hash_table_lookup(s->helpers, (gpointer)= val); + if (helper_table) { + TCGHelperInfo *info =3D g_hash_table_lookup(helper_table, (gpointe= r)val); if (info) { ret =3D info->name; } --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664462099884.4060409525537; Tue, 10 Oct 2017 12:41:02 -0700 (PDT) Received: from localhost ([::1]:36843 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Oe-0000DP-8e for importer@patchew.org; Tue, 10 Oct 2017 15:40:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58954) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Eb-0000pb-WB for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20EZ-000583-OB for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:33 -0400 Received: from mail-pf0-x22e.google.com ([2607:f8b0:400e:c00::22e]:55365) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20EZ-00057k-J5 for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:31 -0400 Received: by mail-pf0-x22e.google.com with SMTP id 17so9937919pfn.12 for ; Tue, 10 Oct 2017 12:30:31 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LEPSQBFcHMdI/3CokXPsBH3v71WBctmmqRbtmcTyRnc=; b=NC3KgIhp8LlhYrA/JvUGJtCd6e3p6X9N1PnVzaYQ2kPXOdgy+92bTaNbXzSonebcyi XuGnWi/EnArQzTUji0w62L/GziO18k+4vp0nQGzSmzADNdbaBObVra0CjZXsFHnnPOXd oZz36c/njuiUul/3zcuv0O266KeuPtKm+eKuY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LEPSQBFcHMdI/3CokXPsBH3v71WBctmmqRbtmcTyRnc=; b=J4mL72GyCkiESZbbq8WY2W4ii48xq70Mzpz+1sjBn9d81euKbsx2C36jushfNV/GDK Xb/uXo02+09neVWmmjfKD3pRCj/zWB6ms1wGEWTpb4vhSpMeOMz+72SVqDVI70YA0xZz asGCXhkDWw7KBNzvR0AgG1BXeywR2sQWNPaEAC2xu7ERLkiq3J3dt1oBW+k3fB784Dxh nqjiLTzDIWSxC0JZLrpV+MiTlTfkbCeF+nvccIE8z/9TBp36Z//QUOp3DyK6ZgnbKGdj RPXn0IU86D8d4xilZPrRzvYPJIMvhMSf3/3EHakE59TKNAbMDafpPMiB8mJIJgBGI/oK N67A== X-Gm-Message-State: AMCzsaUBkdeXJBGiL02MBhb75R9BjJk0T1/8rRUDgOK04/qurTjWt6li bAa8XlIV64Eh7a7HiuoIL9TIi8EH4mM= X-Google-Smtp-Source: AOwi7QC5fqbLvFNbZJkWm9uzkrbPKcp4jkEg7vsgz983Elky6IctE5uZazkAKJqHbYrzi6VWvoH7bQ== X-Received: by 10.98.31.73 with SMTP id f70mr14276179pff.183.1507663830341; Tue, 10 Oct 2017 12:30:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:30:01 -0700 Message-Id: <20171010193003.28857-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22e Subject: [Qemu-devel] [PULL v2 18/20] util: move qemu_real_host_page_size/mask to osdep.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" These only depend on the host and therefore belong in the common osdep, not in a target-dependent object. While at it, query the host during an init constructor, which guarantees the page size will be well-defined throughout the execution of the program. Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 -- include/qemu/osdep.h | 6 ++++++ exec.c | 4 ---- util/pagesize.c | 18 ++++++++++++++++++ util/Makefile.objs | 1 + 5 files changed, 25 insertions(+), 6 deletions(-) create mode 100644 util/pagesize.c diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index ffe43d5654..778031c3d7 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -229,8 +229,6 @@ extern int target_page_bits; /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even * when intptr_t is 32-bit and we are aligning a long long. */ -extern uintptr_t qemu_real_host_page_size; -extern intptr_t qemu_real_host_page_mask; extern uintptr_t qemu_host_page_size; extern intptr_t qemu_host_page_mask; =20 diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 9dd318a7dd..826650c58a 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -505,6 +505,12 @@ char *qemu_get_pid_name(pid_t pid); */ pid_t qemu_fork(Error **errp); =20 +/* Using intptr_t ensures that qemu_*_page_mask is sign-extended even + * when intptr_t is 32-bit and we are aligning a long long. + */ +extern uintptr_t qemu_real_host_page_size; +extern intptr_t qemu_real_host_page_mask; + extern int qemu_icache_linesize; extern int qemu_dcache_linesize; =20 diff --git a/exec.c b/exec.c index 7a80460725..6378714a2b 100644 --- a/exec.c +++ b/exec.c @@ -120,8 +120,6 @@ int use_icount; =20 uintptr_t qemu_host_page_size; intptr_t qemu_host_page_mask; -uintptr_t qemu_real_host_page_size; -intptr_t qemu_real_host_page_mask; =20 bool set_preferred_target_page_bits(int bits) { @@ -3606,8 +3604,6 @@ void page_size_init(void) { /* NOTE: we can always suppose that qemu_host_page_size >=3D TARGET_PAGE_SIZE */ - qemu_real_host_page_size =3D getpagesize(); - qemu_real_host_page_mask =3D -(intptr_t)qemu_real_host_page_size; if (qemu_host_page_size =3D=3D 0) { qemu_host_page_size =3D qemu_real_host_page_size; } diff --git a/util/pagesize.c b/util/pagesize.c new file mode 100644 index 0000000000..998632cf6e --- /dev/null +++ b/util/pagesize.c @@ -0,0 +1,18 @@ +/* + * pagesize.c - query the host about its page size + * + * Copyright (C) 2017, Emilio G. Cota + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +uintptr_t qemu_real_host_page_size; +intptr_t qemu_real_host_page_mask; + +static void __attribute__((constructor)) init_real_host_page_size(void) +{ + qemu_real_host_page_size =3D getpagesize(); + qemu_real_host_page_mask =3D -(intptr_t)qemu_real_host_page_size; +} diff --git a/util/Makefile.objs b/util/Makefile.objs index 50a55ecc75..2973b0a323 100644 --- a/util/Makefile.objs +++ b/util/Makefile.objs @@ -40,6 +40,7 @@ util-obj-y +=3D buffer.o util-obj-y +=3D timed-average.o util-obj-y +=3D base64.o util-obj-y +=3D log.o +util-obj-y +=3D pagesize.o util-obj-y +=3D qdist.o util-obj-y +=3D qht.o util-obj-y +=3D range.o --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664627182243.77649573240603; Tue, 10 Oct 2017 12:43:47 -0700 (PDT) Received: from localhost ([::1]:36852 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20RE-0002Te-3K for importer@patchew.org; Tue, 10 Oct 2017 15:43:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58959) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Ec-0000ps-5G for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20Eb-00058X-2F for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:34 -0400 Received: from mail-pf0-x231.google.com ([2607:f8b0:400e:c00::231]:47480) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20Ea-00058G-T0 for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:32 -0400 Received: by mail-pf0-x231.google.com with SMTP id z11so8330548pfk.4 for ; Tue, 10 Oct 2017 12:30:32 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. [97.126.104.76]) by smtp.gmail.com with ESMTPSA id r22sm19859788pfl.15.2017.10.10.12.30.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2017 12:30:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Xxy9567/LyD/NAl1R9dzWOF5rk63KT8JXQlJtDyUSpQ=; b=CvnQNCw6OVJDXNuXROE0FyeR5W223VwJtXHq1eOFdtzMQmeXIr3Mg4B9IWvOQLbaDe F2BDlyu8vRe8c6vrW24TUUKChAv3rJLE4Ttspn04xq/5z3dgw8Ia0vCJ4b0E402TJBGh UAar8xDPvu99R6HFxFl8mC6HgMhRHfwX4hBFg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xxy9567/LyD/NAl1R9dzWOF5rk63KT8JXQlJtDyUSpQ=; b=CRYydxMD2tDus6L6ZJvSy11CtTMMqm2D8Gjz6lgIac3ezvgY4hYRKQjnAqZLMCv9Mx s/TeDcrem5N0qcMdEgu5cQguw3Rds+YIqzsS6MvockMIcchQTq63TGu5TXlKS3PqgRuS dumguowYP4HtoXvm+3qBj/x3cD6hqVlUC0r+mN0HuRdZnYp0qJTX4elqGxOUQbySDCib 2eWx/TnOhnyq7T/8mLy03ZAbpGjwy4Rbbmahn1/zfjzUlKO5SbqYb7GVhmaP6ioBJXbR RRoaSg97PR/uTr3FkT6NyycHfwECQEuhd2qM34HfESbt3P4lAxTT/2gH4NffyIGqKtA0 pgFw== X-Gm-Message-State: AMCzsaURNe8zDuuHnVh5cL6+SEdBVqGWY5MebkaMsgg6OIJqWzsP58B1 q8VqTi7Hzt/Pg0bcyHI46pQ0mGfO/Io= X-Google-Smtp-Source: AOwi7QClrZlvihdJgRC+g3YU4sZOBnQXgwyO4bY0g2CSu7ytJGPIE6o0Qsos7dGBg4Zn35BbvrgOvw== X-Received: by 10.98.65.27 with SMTP id o27mr14601392pfa.327.1507663831704; Tue, 10 Oct 2017 12:30:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 10 Oct 2017 12:30:02 -0700 Message-Id: <20171010193003.28857-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171010193003.28857-1-richard.henderson@linaro.org> References: <20171010193003.28857-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::231 Subject: [Qemu-devel] [PULL v2 19/20] tcg: define TCG_HIGHWATER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 From: "Emilio G. Cota" Will come in handy very soon. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index ee60798438..4492e1eb3f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -116,6 +116,8 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, static bool tcg_out_ldst_finalize(TCGContext *s); #endif =20 +#define TCG_HIGHWATER 1024 + static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; =20 @@ -430,7 +432,7 @@ void tcg_prologue_init(TCGContext *s) /* Compute a high-water mark, at which we voluntarily flush the buffer and start over. The size here is arbitrary, significantly larger than we expect the code generation for any one opcode to require. = */ - s->code_gen_highwater =3D s->code_gen_buffer + (total_size - 1024); + s->code_gen_highwater =3D s->code_gen_buffer + (total_size - TCG_HIGHW= ATER); =20 tcg_register_jit(s->code_gen_buffer, total_size); =20 --=20 2.13.6 From nobody Thu Mar 28 08:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507664781568423.0728372861648; Tue, 10 Oct 2017 12:46:21 -0700 (PDT) Received: from localhost ([::1]:36869 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Td-0004bP-R4 for importer@patchew.org; Tue, 10 Oct 2017 15:46:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58996) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e20Ed-0000rV-Mb for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e20Ec-00059a-Jr for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:35 -0400 Received: from mail-pf0-x22b.google.com ([2607:f8b0:400e:c00::22b]:54761) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e20Ec-000599-FR for qemu-devel@nongnu.org; Tue, 10 Oct 2017 15:30:34 -0400 Received: by mail-pf0-x22b.google.com with SMTP id m28so13340485pfi.11 for ; Tue, 10 Oct 2017 12:30:34 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-104-76.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PULL v2 20/20] tcg/mips: delete commented out extern keyword. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Jiang Biao Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Jiang Biao Delete commented out extern keyword on link_error(). Signed-off-by: Jiang Biao Message-Id: <1506762042-32145-1-git-send-email-jiang.biao2@zte.com.cn> Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index e993138930..4b55ab8856 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -36,7 +36,7 @@ #else /* To assert at compile-time that these values are never used for TCG_TARGET_REG_BITS =3D=3D 64. */ -/* extern */ int link_error(void); +int link_error(void); # define LO_OFF link_error() # define HI_OFF link_error() #endif --=20 2.13.6