From nobody Sun Feb 8 18:29:50 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1506531730951480.20310992150803; Wed, 27 Sep 2017 10:02:10 -0700 (PDT) Received: from localhost ([::1]:55624 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dxFim-0007V9-VN for importer@patchew.org; Wed, 27 Sep 2017 13:02:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60016) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dxFhU-0006bM-33 for qemu-devel@nongnu.org; Wed, 27 Sep 2017 13:00:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dxFhQ-00064n-0r for qemu-devel@nongnu.org; Wed, 27 Sep 2017 13:00:44 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46742) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dxFhP-00064E-Ou for qemu-devel@nongnu.org; Wed, 27 Sep 2017 13:00:39 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 9BF0A3A58B6; Wed, 27 Sep 2017 17:00:38 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-241.ams2.redhat.com [10.36.117.241]) by smtp.corp.redhat.com (Postfix) with ESMTP id 5BB8AE8184; Wed, 27 Sep 2017 17:00:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 9BF0A3A58B6 Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=david@redhat.com From: David Hildenbrand To: qemu-devel@nongnu.org Date: Wed, 27 Sep 2017 19:00:25 +0200 Message-Id: <20170927170027.8539-2-david@redhat.com> In-Reply-To: <20170927170027.8539-1-david@redhat.com> References: <20170927170027.8539-1-david@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Wed, 27 Sep 2017 17:00:38 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH RFC 1/3] accel/tcg: allow to invalidate a write TLB entry immediately X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, David Hildenbrand , cohuck@redhat.com, Richard Henderson , Alexander Graf , Christian Borntraeger Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Background: s390x implements Low-Address Protection (LAP). If LAP is enabled, writing to effective addresses (before any transaltion) 0-511 and 4096-4607 triggers a protection exception. So we have subpage protection on the first two pages of every address space (where the lowcore - the CPU private data resides). By immediately invalidating the write entry but allowing the caller to continue, we force every write access onto these first two pages into the slow path. we will get a tlb fault with the specific accessed addresses and can then evaluate if protection applies or not. We have to make sure to ignore the invalid bit if tlb_fill() succeeds. Signed-off-by: David Hildenbrand --- accel/tcg/cputlb.c | 5 ++++- accel/tcg/softmmu_template.h | 4 ++-- include/exec/cpu-all.h | 3 +++ 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index bcbcc4db6c..5bc4233961 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -683,6 +683,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, } else { tn.addr_write =3D address; } + if (prot & PAGE_WRITE_INV) { + tn.addr_write |=3D TLB_INVALID_MASK; + } } =20 /* Pairs with flag setting in tlb_reset_dirty_range */ @@ -967,7 +970,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, targe= t_ulong addr, if (!VICTIM_TLB_HIT(addr_write, addr)) { tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, reta= ddr); } - tlb_addr =3D tlbe->addr_write; + tlb_addr =3D tlbe->addr_write & ~TLB_INVALID_MASK; } =20 /* Check notdirty */ diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h index d7563292a5..3fc5144316 100644 --- a/accel/tcg/softmmu_template.h +++ b/accel/tcg/softmmu_template.h @@ -285,7 +285,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, if (!VICTIM_TLB_HIT(addr_write, addr)) { tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, reta= ddr); } - tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write; + tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVA= LID_MASK; } =20 /* Handle an IO access. */ @@ -361,7 +361,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, if (!VICTIM_TLB_HIT(addr_write, addr)) { tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, reta= ddr); } - tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write; + tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVA= LID_MASK; } =20 /* Handle an IO access. */ diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index ffe43d5654..24b9509604 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -247,6 +247,9 @@ extern intptr_t qemu_host_page_mask; /* original state of the write flag (used when tracking self-modifying code */ #define PAGE_WRITE_ORG 0x0010 +/* Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs= () */ +#define PAGE_WRITE_INV 0x0040 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ #define PAGE_RESERVED 0x0020 --=20 2.13.5