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X-Received-From: 2607:f8b0:400d:c0d::241 Subject: [Qemu-devel] [PATCH v4 6/6] mips: replace cpu_mips_init() with cpu_generic_init() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , James Hogan , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Igor Mammedov now cpu_mips_init() reimplements subset of cpu_generic_init() tasks, so just drop it and use cpu_generic_init() directly. Signed-off-by: Igor Mammedov Reviewed-by: Herv=C3=A9 Poussineau Signed-off-by: Philippe Mathieu-Daud=C3=A9 [PMD: use internal.h instead of cpu.h] Tested-by: James Hogan Reviewed-by: Eduardo Habkost --- target/mips/cpu.h | 3 +-- hw/mips/cps.c | 2 +- hw/mips/mips_fulong2e.c | 2 +- hw/mips/mips_jazz.c | 2 +- hw/mips/mips_malta.c | 2 +- hw/mips/mips_mipssim.c | 2 +- hw/mips/mips_r4k.c | 2 +- target/mips/translate.c | 17 ----------------- 8 files changed, 7 insertions(+), 25 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 2f81e0f950..66265e4eb6 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -737,10 +737,9 @@ enum { */ #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 =20 -MIPSCPU *cpu_mips_init(const char *cpu_model); int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); =20 -#define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model)) +#define cpu_init(cpu_model) cpu_generic_init(TYPE_MIPS_CPU, cpu_model) bool cpu_supports_cps_smp(const char *cpu_model); bool cpu_supports_isa(const char *cpu_model, unsigned int isa); void cpu_set_exception_base(int vp_index, target_ulong address); diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 79d4c5e30a..fe5c630af6 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -71,7 +71,7 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) bool itu_present =3D false; =20 for (i =3D 0; i < s->num_vp; i++) { - cpu =3D cpu_mips_init(s->cpu_model); + cpu =3D MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, s->cpu_model)); =20 /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index 439a3d7a66..75318680e1 100644 --- a/hw/mips/mips_fulong2e.c +++ b/hw/mips/mips_fulong2e.c @@ -280,7 +280,7 @@ static void mips_fulong2e_init(MachineState *machine) if (cpu_model =3D=3D NULL) { cpu_model =3D "Loongson-2E"; } - cpu =3D cpu_mips_init(cpu_model); + cpu =3D MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model)); env =3D &cpu->env; =20 qemu_register_reset(main_cpu_reset, cpu); diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index ae10670efd..7e6626dc88 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -151,7 +151,7 @@ static void mips_jazz_init(MachineState *machine, if (cpu_model =3D=3D NULL) { cpu_model =3D "R4000"; } - cpu =3D cpu_mips_init(cpu_model); + cpu =3D MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model)); env =3D &cpu->env; qemu_register_reset(main_cpu_reset, cpu); =20 diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index e87cd3230b..2adb9bcf89 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -931,7 +931,7 @@ static void create_cpu_without_cps(const char *cpu_mode= l, int i; =20 for (i =3D 0; i < smp_cpus; i++) { - cpu =3D cpu_mips_init(cpu_model); + cpu =3D MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model)); =20 /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c index 49cd38d680..a092072e2a 100644 --- a/hw/mips/mips_mipssim.c +++ b/hw/mips/mips_mipssim.c @@ -163,7 +163,7 @@ mips_mipssim_init(MachineState *machine) cpu_model =3D "24Kf"; #endif } - cpu =3D cpu_mips_init(cpu_model); + cpu =3D MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model)); env =3D &cpu->env; =20 reset_info =3D g_malloc0(sizeof(ResetData)); diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index 7efee94431..1272d4ef9d 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -193,7 +193,7 @@ void mips_r4k_init(MachineState *machine) cpu_model =3D "24Kf"; #endif } - cpu =3D cpu_mips_init(cpu_model); + cpu =3D MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model)); env =3D &cpu->env; =20 reset_info =3D g_malloc0(sizeof(ResetData)); diff --git a/target/mips/translate.c b/target/mips/translate.c index f7128bc91d..d16d879df7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20523,23 +20523,6 @@ void cpu_mips_realize_env(CPUMIPSState *env) mvp_init(env, env->cpu_model); } =20 -MIPSCPU *cpu_mips_init(const char *cpu_model) -{ - ObjectClass *oc; - MIPSCPU *cpu; - - oc =3D cpu_class_by_name(TYPE_MIPS_CPU, cpu_model); - if (oc =3D=3D NULL) { - return NULL; - } - - cpu =3D MIPS_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; -} - bool cpu_supports_cps_smp(const char *cpu_model) { const mips_def_t *def =3D cpu_mips_find_by_name(cpu_model); --=20 2.14.1