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X-Received-From: 2607:f8b0:400d:c0d::241 Subject: [Qemu-devel] [PATCH v4 1/6] mips: move hw/mips/cputimer.c to target/mips/ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , James Hogan , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This timer is a required part of the MIPS32/MIPS64 System Control coprocess= or (CP0). Moving it with the other architecture related files will allow an op= aque use of CPUMIPSState* in the next commit (introduce "internal.h"). also remove it from 'user' targets, remove an unnecessary include. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Igor Mammedov Tested-by: James Hogan Acked-by: Eduardo Habkost --- hw/mips/cputimer.c =3D> target/mips/cp0_timer.c | 1 - hw/mips/Makefile.objs | 2 +- target/mips/Makefile.objs | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) rename hw/mips/cputimer.c =3D> target/mips/cp0_timer.c (99%) diff --git a/hw/mips/cputimer.c b/target/mips/cp0_timer.c similarity index 99% rename from hw/mips/cputimer.c rename to target/mips/cp0_timer.c index 8a166b3ea7..a9a58c5604 100644 --- a/hw/mips/cputimer.c +++ b/target/mips/cp0_timer.c @@ -21,7 +21,6 @@ */ =20 #include "qemu/osdep.h" -#include "hw/hw.h" #include "hw/mips/cpudevs.h" #include "qemu/timer.h" #include "sysemu/kvm.h" diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs index 48cd2ef50e..17a311aaba 100644 --- a/hw/mips/Makefile.objs +++ b/hw/mips/Makefile.objs @@ -1,5 +1,5 @@ obj-y +=3D mips_r4k.o mips_malta.o mips_mipssim.o -obj-y +=3D addr.o cputimer.o mips_int.o +obj-y +=3D addr.o mips_int.o obj-$(CONFIG_JAZZ) +=3D mips_jazz.o obj-$(CONFIG_FULONG) +=3D mips_fulong2e.o obj-y +=3D gt64xxx_pci.o diff --git a/target/mips/Makefile.objs b/target/mips/Makefile.objs index bc5ed8511f..651f36f517 100644 --- a/target/mips/Makefile.objs +++ b/target/mips/Makefile.objs @@ -1,4 +1,4 @@ obj-y +=3D translate.o dsp_helper.o op_helper.o lmi_helper.o helper.o cpu.o obj-y +=3D gdbstub.o msa_helper.o mips-semi.o -obj-$(CONFIG_SOFTMMU) +=3D machine.o +obj-$(CONFIG_SOFTMMU) +=3D machine.o cp0_timer.o obj-$(CONFIG_KVM) +=3D kvm.o --=20 2.14.1 From nobody Fri May 17 22:06:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH v4 2/6] mips: introduce internal.h and cleanup cpu.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , James Hogan , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 no logical change, only code movement (and fix a comment typo). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Igor Mammedov Tested-by: James Hogan Acked-by: Eduardo Habkost --- This patch triggers 3 positive falses from checkpatch: ERROR: space prohibited after that '&' (ctx:WxW) #664: FILE: target/mips/internal.h:230: + if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { ^ #672: FILE: target/mips/internal.h:238: + ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) { ^ #692: FILE: target/mips/internal.h:258: + env->hflags |=3D (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; ^ total: 3 errors, 0 warnings, 842 lines checked This is a "binary vs unary operators" confusion. target/mips/cpu.h | 354 +------------------------------------------= -- target/mips/internal.h | 362 +++++++++++++++++++++++++++++++++++++++++++= ++++ target/mips/cp0_timer.c | 1 + target/mips/cpu.c | 1 + target/mips/gdbstub.c | 1 + target/mips/helper.c | 1 + target/mips/kvm.c | 1 + target/mips/machine.c | 1 + target/mips/msa_helper.c | 1 + target/mips/op_helper.c | 1 + target/mips/translate.c | 1 + 11 files changed, 372 insertions(+), 353 deletions(-) create mode 100644 target/mips/internal.h diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 74f6a5b098..2f81e0f950 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1,8 +1,6 @@ #ifndef MIPS_CPU_H #define MIPS_CPU_H =20 -//#define DEBUG_OP - #define ALIGNED_ONLY =20 #define CPUArchState struct CPUMIPSState @@ -15,56 +13,11 @@ =20 struct CPUMIPSState; =20 -typedef struct r4k_tlb_t r4k_tlb_t; -struct r4k_tlb_t { - target_ulong VPN; - uint32_t PageMask; - uint16_t ASID; - unsigned int G:1; - unsigned int C0:3; - unsigned int C1:3; - unsigned int V0:1; - unsigned int V1:1; - unsigned int D0:1; - unsigned int D1:1; - unsigned int XI0:1; - unsigned int XI1:1; - unsigned int RI0:1; - unsigned int RI1:1; - unsigned int EHINV:1; - uint64_t PFN[2]; -}; - -#if !defined(CONFIG_USER_ONLY) typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; -struct CPUMIPSTLBContext { - uint32_t nb_tlb; - uint32_t tlb_in_use; - int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *p= rot, target_ulong address, int rw, int access_type); - void (*helper_tlbwi)(struct CPUMIPSState *env); - void (*helper_tlbwr)(struct CPUMIPSState *env); - void (*helper_tlbp)(struct CPUMIPSState *env); - void (*helper_tlbr)(struct CPUMIPSState *env); - void (*helper_tlbinv)(struct CPUMIPSState *env); - void (*helper_tlbinvf)(struct CPUMIPSState *env); - union { - struct { - r4k_tlb_t tlb[MIPS_TLB_MAX]; - } r4k; - } mmu; -}; -#endif =20 /* MSA Context */ #define MSA_WRLEN (128) =20 -enum CPUMIPSMSADataFormat { - DF_BYTE =3D 0, - DF_HALF, - DF_WORD, - DF_DOUBLE -}; - typedef union wr_t wr_t; union wr_t { int8_t b[MSA_WRLEN/8]; @@ -682,40 +635,6 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *= env) =20 #define ENV_OFFSET offsetof(MIPSCPU, env) =20 -#ifndef CONFIG_USER_ONLY -extern const struct VMStateDescription vmstate_mips_cpu; -#endif - -void mips_cpu_do_interrupt(CPUState *cpu); -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fpri= ntf, - int flags); -hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); -int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); - -#if !defined(CONFIG_USER_ONLY) -int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type); -int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type); -int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, int rw, int access_type); -void r4k_helper_tlbwi(CPUMIPSState *env); -void r4k_helper_tlbwr(CPUMIPSState *env); -void r4k_helper_tlbp(CPUMIPSState *env); -void r4k_helper_tlbr(CPUMIPSState *env); -void r4k_helper_tlbinv(CPUMIPSState *env); -void r4k_helper_tlbinvf(CPUMIPSState *env); - -void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, int unused, - unsigned size); -#endif - void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); =20 #define cpu_signal_handler cpu_mips_signal_handler @@ -746,42 +665,6 @@ static inline int cpu_mmu_index (CPUMIPSState *env, bo= ol ifetch) return hflags_mmu_index(env->hflags); } =20 -static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) -{ - return (env->CP0_Status & (1 << CP0St_IE)) && - !(env->CP0_Status & (1 << CP0St_EXL)) && - !(env->CP0_Status & (1 << CP0St_ERL)) && - !(env->hflags & MIPS_HFLAG_DM) && - /* Note that the TCStatus IXMT field is initialized to zero, - and only MT capable cores can set it to one. So we don't - need to check for MT capabilities here. */ - !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); -} - -/* Check if there is pending and not masked out interrupt */ -static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) -{ - int32_t pending; - int32_t status; - bool r; - - pending =3D env->CP0_Cause & CP0Ca_IP_mask; - status =3D env->CP0_Status & CP0Ca_IP_mask; - - if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { - /* A MIPS configured with a vectorizing external interrupt control= ler - will feed a vector into the Cause pending lines. The core treats - the status lines as a vector level, not as indiviual masks. */ - r =3D pending > status; - } else { - /* A MIPS configured with compatibility or VInt (Vectored Interrup= ts) - treats the pending lines as individual interrupt lines, the sta= tus - lines are individual masks. */ - r =3D (pending & status) !=3D 0; - } - return r; -} - #include "exec/cpu-all.h" =20 /* Memory access type : @@ -847,14 +730,13 @@ enum { #define EXCP_SC 0x100 =20 /* - * This is an interrnally generated WAKE request line. + * This is an internally generated WAKE request line. * It is driven by the CPU itself. Raised when the MT * block wants to wake a VPE from an inactive state and * cleared when VPE goes from active to inactive. */ #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 =20 -void mips_tcg_init(void); MIPSCPU *cpu_mips_init(const char *cpu_model); int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); =20 @@ -863,84 +745,18 @@ bool cpu_supports_cps_smp(const char *cpu_model); bool cpu_supports_isa(const char *cpu_model, unsigned int isa); void cpu_set_exception_base(int vp_index, target_ulong address); =20 -/* TODO QOM'ify CPU reset and remove */ -void cpu_state_reset(CPUMIPSState *s); - -/* mips_timer.c */ -uint32_t cpu_mips_get_random (CPUMIPSState *env); -uint32_t cpu_mips_get_count (CPUMIPSState *env); -void cpu_mips_store_count (CPUMIPSState *env, uint32_t value); -void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value); -void cpu_mips_start_count(CPUMIPSState *env); -void cpu_mips_stop_count(CPUMIPSState *env); - /* mips_int.c */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); =20 /* helper.c */ -int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, - int mmu_idx); - -/* op_helper.c */ -uint32_t float_class_s(uint32_t arg, float_status *fst); -uint64_t float_class_d(uint64_t arg, float_status *fst); - -#if !defined(CONFIG_USER_ONLY) -void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); -hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, - int rw); -#endif target_ulong exception_resume_pc (CPUMIPSState *env); =20 -/* op_helper.c */ -extern unsigned int ieee_rm[]; -int ieee_ex_to_mips(int xcpt); - -static inline void restore_rounding_mode(CPUMIPSState *env) -{ - set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], - &env->active_fpu.fp_status); -} - -static inline void restore_flush_mode(CPUMIPSState *env) -{ - set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) !=3D 0, - &env->active_fpu.fp_status); -} - static inline void restore_snan_bit_mode(CPUMIPSState *env) { set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) =3D= =3D 0, &env->active_fpu.fp_status); } =20 -static inline void restore_fp_status(CPUMIPSState *env) -{ - restore_rounding_mode(env); - restore_flush_mode(env); - restore_snan_bit_mode(env); -} - -static inline void restore_msa_fp_status(CPUMIPSState *env) -{ - float_status *status =3D &env->active_tc.msa_fp_status; - int rounding_mode =3D (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSAC= SR_RM; - bool flush_to_zero =3D (env->active_tc.msacsr & MSACSR_FS_MASK) !=3D 0; - - set_float_rounding_mode(ieee_rm[rounding_mode], status); - set_flush_to_zero(flush_to_zero, status); - set_flush_inputs_to_zero(flush_to_zero, status); -} - -static inline void restore_pamask(CPUMIPSState *env) -{ - if (env->hflags & MIPS_HFLAG_ELPA) { - env->PAMask =3D (1ULL << env->PABITS) - 1; - } else { - env->PAMask =3D PAMASK_BASE; - } -} - static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *p= c, target_ulong *cs_base, uint32_t *f= lags) { @@ -950,172 +766,4 @@ static inline void cpu_get_tb_cpu_state(CPUMIPSState = *env, target_ulong *pc, MIPS_HFLAG_HWRENA_ULR); } =20 -static inline int mips_vpe_active(CPUMIPSState *env) -{ - int active =3D 1; - - /* Check that the VPE is enabled. */ - if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { - active =3D 0; - } - /* Check that the VPE is activated. */ - if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { - active =3D 0; - } - - /* Now verify that there are active thread contexts in the VPE. - - This assumes the CPU model will internally reschedule threads - if the active one goes to sleep. If there are no threads available - the active one will be in a sleeping state, and we can turn off - the entire VPE. */ - if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { - /* TC is not activated. */ - active =3D 0; - } - if (env->active_tc.CP0_TCHalt & 1) { - /* TC is in halt state. */ - active =3D 0; - } - - return active; -} - -static inline int mips_vp_active(CPUMIPSState *env) -{ - CPUState *other_cs =3D first_cpu; - - /* Check if the VP disabled other VPs (which means the VP is enabled) = */ - if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { - return 1; - } - - /* Check if the virtual processor is disabled due to a DVP */ - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); - if ((&other_cpu->env !=3D env) && - ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) { - return 0; - } - } - return 1; -} - -static inline void compute_hflags(CPUMIPSState *env) -{ - env->hflags &=3D ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | - MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | - MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 | - MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE | - MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); - if (env->CP0_Status & (1 << CP0St_ERL)) { - env->hflags |=3D MIPS_HFLAG_ERL; - } - if (!(env->CP0_Status & (1 << CP0St_EXL)) && - !(env->CP0_Status & (1 << CP0St_ERL)) && - !(env->hflags & MIPS_HFLAG_DM)) { - env->hflags |=3D (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; - } -#if defined(TARGET_MIPS64) - if ((env->insn_flags & ISA_MIPS3) && - (((env->hflags & MIPS_HFLAG_KSU) !=3D MIPS_HFLAG_UM) || - (env->CP0_Status & (1 << CP0St_PX)) || - (env->CP0_Status & (1 << CP0St_UX)))) { - env->hflags |=3D MIPS_HFLAG_64; - } - - if (!(env->insn_flags & ISA_MIPS3)) { - env->hflags |=3D MIPS_HFLAG_AWRAP; - } else if (((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_UM) && - !(env->CP0_Status & (1 << CP0St_UX))) { - env->hflags |=3D MIPS_HFLAG_AWRAP; - } else if (env->insn_flags & ISA_MIPS64R6) { - /* Address wrapping for Supervisor and Kernel is specified in R6 */ - if ((((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_SM) && - !(env->CP0_Status & (1 << CP0St_SX))) || - (((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_KM) && - !(env->CP0_Status & (1 << CP0St_KX)))) { - env->hflags |=3D MIPS_HFLAG_AWRAP; - } - } -#endif - if (((env->CP0_Status & (1 << CP0St_CU0)) && - !(env->insn_flags & ISA_MIPS32R6)) || - !(env->hflags & MIPS_HFLAG_KSU)) { - env->hflags |=3D MIPS_HFLAG_CP0; - } - if (env->CP0_Status & (1 << CP0St_CU1)) { - env->hflags |=3D MIPS_HFLAG_FPU; - } - if (env->CP0_Status & (1 << CP0St_FR)) { - env->hflags |=3D MIPS_HFLAG_F64; - } - if (((env->hflags & MIPS_HFLAG_KSU) !=3D MIPS_HFLAG_KM) && - (env->CP0_Config5 & (1 << CP0C5_SBRI))) { - env->hflags |=3D MIPS_HFLAG_SBRI; - } - if (env->insn_flags & ASE_DSPR2) { - /* Enables access MIPS DSP resources, now our cpu is DSP ASER2, - so enable to access DSPR2 resources. */ - if (env->CP0_Status & (1 << CP0St_MX)) { - env->hflags |=3D MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2; - } - - } else if (env->insn_flags & ASE_DSP) { - /* Enables access MIPS DSP resources, now our cpu is DSP ASE, - so enable to access DSP resources. */ - if (env->CP0_Status & (1 << CP0St_MX)) { - env->hflags |=3D MIPS_HFLAG_DSP; - } - - } - if (env->insn_flags & ISA_MIPS32R2) { - if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { - env->hflags |=3D MIPS_HFLAG_COP1X; - } - } else if (env->insn_flags & ISA_MIPS32) { - if (env->hflags & MIPS_HFLAG_64) { - env->hflags |=3D MIPS_HFLAG_COP1X; - } - } else if (env->insn_flags & ISA_MIPS4) { - /* All supported MIPS IV CPUs use the XX (CU3) to enable - and disable the MIPS IV extensions to the MIPS III ISA. - Some other MIPS IV CPUs ignore the bit, so the check here - would be too restrictive for them. */ - if (env->CP0_Status & (1U << CP0St_CU3)) { - env->hflags |=3D MIPS_HFLAG_COP1X; - } - } - if (env->insn_flags & ASE_MSA) { - if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { - env->hflags |=3D MIPS_HFLAG_MSA; - } - } - if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { - if (env->CP0_Config5 & (1 << CP0C5_FRE)) { - env->hflags |=3D MIPS_HFLAG_FRE; - } - } - if (env->CP0_Config3 & (1 << CP0C3_LPA)) { - if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) { - env->hflags |=3D MIPS_HFLAG_ELPA; - } - } -} - -void cpu_mips_tlb_flush(CPUMIPSState *env); -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exce= ption, - int error_code, uintptr_t pc); - -static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, - uint32_t exception, - uintptr_t pc) -{ - do_raise_exception_err(env, exception, 0, pc); -} - #endif /* MIPS_CPU_H */ diff --git a/target/mips/internal.h b/target/mips/internal.h new file mode 100644 index 0000000000..91c2df4537 --- /dev/null +++ b/target/mips/internal.h @@ -0,0 +1,362 @@ +/* mips internal definitions and helpers + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_INTERNAL_H +#define MIPS_INTERNAL_H + +enum CPUMIPSMSADataFormat { + DF_BYTE =3D 0, + DF_HALF, + DF_WORD, + DF_DOUBLE +}; + +void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); +void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fpri= ntf, + int flags); +hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); + +#if !defined(CONFIG_USER_ONLY) + +typedef struct r4k_tlb_t r4k_tlb_t; +struct r4k_tlb_t { + target_ulong VPN; + uint32_t PageMask; + uint16_t ASID; + unsigned int G:1; + unsigned int C0:3; + unsigned int C1:3; + unsigned int V0:1; + unsigned int V1:1; + unsigned int D0:1; + unsigned int D1:1; + unsigned int XI0:1; + unsigned int XI1:1; + unsigned int RI0:1; + unsigned int RI1:1; + unsigned int EHINV:1; + uint64_t PFN[2]; +}; + +struct CPUMIPSTLBContext { + uint32_t nb_tlb; + uint32_t tlb_in_use; + int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *pr= ot, + target_ulong address, int rw, int access_type); + void (*helper_tlbwi)(struct CPUMIPSState *env); + void (*helper_tlbwr)(struct CPUMIPSState *env); + void (*helper_tlbp)(struct CPUMIPSState *env); + void (*helper_tlbr)(struct CPUMIPSState *env); + void (*helper_tlbinv)(struct CPUMIPSState *env); + void (*helper_tlbinvf)(struct CPUMIPSState *env); + union { + struct { + r4k_tlb_t tlb[MIPS_TLB_MAX]; + } r4k; + } mmu; +}; + +int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type); +int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type); +int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, int rw, int access_type); +void r4k_helper_tlbwi(CPUMIPSState *env); +void r4k_helper_tlbwr(CPUMIPSState *env); +void r4k_helper_tlbp(CPUMIPSState *env); +void r4k_helper_tlbr(CPUMIPSState *env); +void r4k_helper_tlbinv(CPUMIPSState *env); +void r4k_helper_tlbinvf(CPUMIPSState *env); +void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); + +void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr, + bool is_write, bool is_exec, int unused, + unsigned size); +hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, + int rw); +#endif + +#define cpu_signal_handler cpu_mips_signal_handler + +#ifndef CONFIG_USER_ONLY +extern const struct VMStateDescription vmstate_mips_cpu; +#endif + +static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) +{ + return (env->CP0_Status & (1 << CP0St_IE)) && + !(env->CP0_Status & (1 << CP0St_EXL)) && + !(env->CP0_Status & (1 << CP0St_ERL)) && + !(env->hflags & MIPS_HFLAG_DM) && + /* Note that the TCStatus IXMT field is initialized to zero, + and only MT capable cores can set it to one. So we don't + need to check for MT capabilities here. */ + !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); +} + +/* Check if there is pending and not masked out interrupt */ +static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) +{ + int32_t pending; + int32_t status; + bool r; + + pending =3D env->CP0_Cause & CP0Ca_IP_mask; + status =3D env->CP0_Status & CP0Ca_IP_mask; + + if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { + /* A MIPS configured with a vectorizing external interrupt control= ler + will feed a vector into the Cause pending lines. The core treats + the status lines as a vector level, not as indiviual masks. */ + r =3D pending > status; + } else { + /* A MIPS configured with compatibility or VInt (Vectored Interrup= ts) + treats the pending lines as individual interrupt lines, the sta= tus + lines are individual masks. */ + r =3D (pending & status) !=3D 0; + } + return r; +} + +void mips_tcg_init(void); + +/* TODO QOM'ify CPU reset and remove */ +void cpu_state_reset(CPUMIPSState *s); + +/* cp0_timer.c */ +uint32_t cpu_mips_get_random(CPUMIPSState *env); +uint32_t cpu_mips_get_count(CPUMIPSState *env); +void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); +void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); +void cpu_mips_start_count(CPUMIPSState *env); +void cpu_mips_stop_count(CPUMIPSState *env); + +/* helper.c */ +int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, + int mmu_idx); + +/* op_helper.c */ +uint32_t float_class_s(uint32_t arg, float_status *fst); +uint64_t float_class_d(uint64_t arg, float_status *fst); + +extern unsigned int ieee_rm[]; +int ieee_ex_to_mips(int xcpt); + +static inline void restore_rounding_mode(CPUMIPSState *env) +{ + set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], + &env->active_fpu.fp_status); +} + +static inline void restore_flush_mode(CPUMIPSState *env) +{ + set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) !=3D 0, + &env->active_fpu.fp_status); +} + +static inline void restore_fp_status(CPUMIPSState *env) +{ + restore_rounding_mode(env); + restore_flush_mode(env); + restore_snan_bit_mode(env); +} + +static inline void restore_msa_fp_status(CPUMIPSState *env) +{ + float_status *status =3D &env->active_tc.msa_fp_status; + int rounding_mode =3D (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSAC= SR_RM; + bool flush_to_zero =3D (env->active_tc.msacsr & MSACSR_FS_MASK) !=3D 0; + + set_float_rounding_mode(ieee_rm[rounding_mode], status); + set_flush_to_zero(flush_to_zero, status); + set_flush_inputs_to_zero(flush_to_zero, status); +} + +static inline void restore_pamask(CPUMIPSState *env) +{ + if (env->hflags & MIPS_HFLAG_ELPA) { + env->PAMask =3D (1ULL << env->PABITS) - 1; + } else { + env->PAMask =3D PAMASK_BASE; + } +} + +static inline int mips_vpe_active(CPUMIPSState *env) +{ + int active =3D 1; + + /* Check that the VPE is enabled. */ + if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { + active =3D 0; + } + /* Check that the VPE is activated. */ + if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { + active =3D 0; + } + + /* Now verify that there are active thread contexts in the VPE. + + This assumes the CPU model will internally reschedule threads + if the active one goes to sleep. If there are no threads available + the active one will be in a sleeping state, and we can turn off + the entire VPE. */ + if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { + /* TC is not activated. */ + active =3D 0; + } + if (env->active_tc.CP0_TCHalt & 1) { + /* TC is in halt state. */ + active =3D 0; + } + + return active; +} + +static inline int mips_vp_active(CPUMIPSState *env) +{ + CPUState *other_cs =3D first_cpu; + + /* Check if the VP disabled other VPs (which means the VP is enabled) = */ + if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { + return 1; + } + + /* Check if the virtual processor is disabled due to a DVP */ + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); + if ((&other_cpu->env !=3D env) && + ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) { + return 0; + } + } + return 1; +} + +static inline void compute_hflags(CPUMIPSState *env) +{ + env->hflags &=3D ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | + MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | + MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 | + MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE | + MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); + if (env->CP0_Status & (1 << CP0St_ERL)) { + env->hflags |=3D MIPS_HFLAG_ERL; + } + if (!(env->CP0_Status & (1 << CP0St_EXL)) && + !(env->CP0_Status & (1 << CP0St_ERL)) && + !(env->hflags & MIPS_HFLAG_DM)) { + env->hflags |=3D (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; + } +#if defined(TARGET_MIPS64) + if ((env->insn_flags & ISA_MIPS3) && + (((env->hflags & MIPS_HFLAG_KSU) !=3D MIPS_HFLAG_UM) || + (env->CP0_Status & (1 << CP0St_PX)) || + (env->CP0_Status & (1 << CP0St_UX)))) { + env->hflags |=3D MIPS_HFLAG_64; + } + + if (!(env->insn_flags & ISA_MIPS3)) { + env->hflags |=3D MIPS_HFLAG_AWRAP; + } else if (((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_UM) && + !(env->CP0_Status & (1 << CP0St_UX))) { + env->hflags |=3D MIPS_HFLAG_AWRAP; + } else if (env->insn_flags & ISA_MIPS64R6) { + /* Address wrapping for Supervisor and Kernel is specified in R6 */ + if ((((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_SM) && + !(env->CP0_Status & (1 << CP0St_SX))) || + (((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_KM) && + !(env->CP0_Status & (1 << CP0St_KX)))) { + env->hflags |=3D MIPS_HFLAG_AWRAP; + } + } +#endif + if (((env->CP0_Status & (1 << CP0St_CU0)) && + !(env->insn_flags & ISA_MIPS32R6)) || + !(env->hflags & MIPS_HFLAG_KSU)) { + env->hflags |=3D MIPS_HFLAG_CP0; + } + if (env->CP0_Status & (1 << CP0St_CU1)) { + env->hflags |=3D MIPS_HFLAG_FPU; + } + if (env->CP0_Status & (1 << CP0St_FR)) { + env->hflags |=3D MIPS_HFLAG_F64; + } + if (((env->hflags & MIPS_HFLAG_KSU) !=3D MIPS_HFLAG_KM) && + (env->CP0_Config5 & (1 << CP0C5_SBRI))) { + env->hflags |=3D MIPS_HFLAG_SBRI; + } + if (env->insn_flags & ASE_DSPR2) { + /* Enables access MIPS DSP resources, now our cpu is DSP ASER2, + so enable to access DSPR2 resources. */ + if (env->CP0_Status & (1 << CP0St_MX)) { + env->hflags |=3D MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2; + } + + } else if (env->insn_flags & ASE_DSP) { + /* Enables access MIPS DSP resources, now our cpu is DSP ASE, + so enable to access DSP resources. */ + if (env->CP0_Status & (1 << CP0St_MX)) { + env->hflags |=3D MIPS_HFLAG_DSP; + } + + } + if (env->insn_flags & ISA_MIPS32R2) { + if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { + env->hflags |=3D MIPS_HFLAG_COP1X; + } + } else if (env->insn_flags & ISA_MIPS32) { + if (env->hflags & MIPS_HFLAG_64) { + env->hflags |=3D MIPS_HFLAG_COP1X; + } + } else if (env->insn_flags & ISA_MIPS4) { + /* All supported MIPS IV CPUs use the XX (CU3) to enable + and disable the MIPS IV extensions to the MIPS III ISA. + Some other MIPS IV CPUs ignore the bit, so the check here + would be too restrictive for them. */ + if (env->CP0_Status & (1U << CP0St_CU3)) { + env->hflags |=3D MIPS_HFLAG_COP1X; + } + } + if (env->insn_flags & ASE_MSA) { + if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { + env->hflags |=3D MIPS_HFLAG_MSA; + } + } + if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { + if (env->CP0_Config5 & (1 << CP0C5_FRE)) { + env->hflags |=3D MIPS_HFLAG_FRE; + } + } + if (env->CP0_Config3 & (1 << CP0C3_LPA)) { + if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) { + env->hflags |=3D MIPS_HFLAG_ELPA; + } + } +} + +void cpu_mips_tlb_flush(CPUMIPSState *env); +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); + +void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exce= ption, + int error_code, uintptr_t pc); + +static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, + uint32_t exception, + uintptr_t pc) +{ + do_raise_exception_err(env, exception, 0, pc); +} + +#endif diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index a9a58c5604..f4716395df 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -24,6 +24,7 @@ #include "hw/mips/cpudevs.h" #include "qemu/timer.h" #include "sysemu/kvm.h" +#include "internal.h" =20 #define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */ =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 1bb66b7a5a..68bf423e9d 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" +#include "internal.h" #include "kvm_mips.h" #include "qemu-common.h" #include "sysemu/kvm.h" diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index 7c682289c2..6d1fb70f2c 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "cpu.h" +#include "internal.h" #include "exec/gdbstub.h" =20 int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) diff --git a/target/mips/helper.c b/target/mips/helper.c index ca39aca08a..ea076261af 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" =20 #include "cpu.h" +#include "internal.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/log.h" diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 3b7b1d962a..8e72850962 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -16,6 +16,7 @@ =20 #include "qemu-common.h" #include "cpu.h" +#include "internal.h" #include "qemu/error-report.h" #include "qemu/timer.h" #include "sysemu/sysemu.h" diff --git a/target/mips/machine.c b/target/mips/machine.c index 898825de3b..20100d5adb 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -1,6 +1,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "cpu.h" +#include "internal.h" #include "hw/hw.h" #include "migration/cpu.h" =20 diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 1fdb0d9792..f167a42655 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "internal.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" =20 diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 320f2b0dc4..e537a8bfd8 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "internal.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" diff --git a/target/mips/translate.c b/target/mips/translate.c index c78d27294c..f0febaf1b2 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -23,6 +23,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "internal.h" #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg-op.h" --=20 2.14.1 From nobody Fri May 17 22:06:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH v4 3/6] mips: split cpu_mips_realize_env() out of cpu_mips_init() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , James Hogan , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 so it can be used in mips_cpu_realizefn() in the next commit Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Igor Mammedov Tested-by: James Hogan Reviewed-by: Eduardo Habkost --- target/mips/internal.h | 1 + target/mips/translate.c | 19 ++++++++++++------- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 91c2df4537..cf4c9db427 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -132,6 +132,7 @@ void mips_tcg_init(void); =20 /* TODO QOM'ify CPU reset and remove */ void cpu_state_reset(CPUMIPSState *s); +void cpu_mips_realize_env(CPUMIPSState *env); =20 /* cp0_timer.c */ uint32_t cpu_mips_get_random(CPUMIPSState *env); diff --git a/target/mips/translate.c b/target/mips/translate.c index f0febaf1b2..5fc7979ac5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20512,6 +20512,17 @@ void mips_tcg_init(void) =20 #include "translate_init.c" =20 +void cpu_mips_realize_env(CPUMIPSState *env) +{ + env->exception_base =3D (int32_t)0xBFC00000; + +#ifndef CONFIG_USER_ONLY + mmu_init(env, env->cpu_model); +#endif + fpu_init(env, env->cpu_model); + mvp_init(env, env->cpu_model); +} + MIPSCPU *cpu_mips_init(const char *cpu_model) { MIPSCPU *cpu; @@ -20524,13 +20535,7 @@ MIPSCPU *cpu_mips_init(const char *cpu_model) cpu =3D MIPS_CPU(object_new(TYPE_MIPS_CPU)); env =3D &cpu->env; env->cpu_model =3D def; - env->exception_base =3D (int32_t)0xBFC00000; - -#ifndef CONFIG_USER_ONLY - mmu_init(env, def); -#endif - fpu_init(env, def); - mvp_init(env, def); + cpu_mips_realize_env(env); =20 object_property_set_bool(OBJECT(cpu), true, "realized", NULL); =20 --=20 2.14.1 From nobody Fri May 17 22:06:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505937230589414.9183811811906; Wed, 20 Sep 2017 12:53:50 -0700 (PDT) Received: from localhost ([::1]:50399 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dul49-00074C-Em for importer@patchew.org; Wed, 20 Sep 2017 15:53:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37799) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dul0R-0004GF-QE for qemu-devel@nongnu.org; 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Wed, 20 Sep 2017 12:49:57 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Igor Mammedov , Eduardo Habkost , Aurelien Jarno , Yongbok Kim , Marcel Apfelbaum Date: Wed, 20 Sep 2017 16:49:32 -0300 Message-Id: <20170920194934.23071-5-f4bug@amsat.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170920194934.23071-1-f4bug@amsat.org> References: <20170920194934.23071-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH v4 4/6] mips: call cpu_mips_realize_env() from mips_cpu_realizefn() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , James Hogan , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This changes the order between cpu_mips_realize_env() and cpu_exec_initfn(), but cpu_exec_initfn() don't have anything that depends on cpu_mips_realize_env() being called first. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Igor Mammedov Tested-by: James Hogan Reviewed-by: Eduardo Habkost --- target/mips/cpu.c | 3 +++ target/mips/translate.c | 1 - 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 68bf423e9d..e3ef835599 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -123,6 +123,7 @@ static void mips_cpu_disas_set_info(CPUState *s, disass= emble_info *info) { static void mips_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); + MIPSCPU *cpu =3D MIPS_CPU(dev); MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 @@ -132,6 +133,8 @@ static void mips_cpu_realizefn(DeviceState *dev, Error = **errp) return; } =20 + cpu_mips_realize_env(&cpu->env); + cpu_reset(cs); qemu_init_vcpu(cs); =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index 5fc7979ac5..94c38e8755 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20535,7 +20535,6 @@ MIPSCPU *cpu_mips_init(const char *cpu_model) cpu =3D MIPS_CPU(object_new(TYPE_MIPS_CPU)); env =3D &cpu->env; env->cpu_model =3D def; - cpu_mips_realize_env(env); =20 object_property_set_bool(OBJECT(cpu), true, "realized", NULL); =20 --=20 2.14.1 From nobody Fri May 17 22:06:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505937345660378.54538567157795; Wed, 20 Sep 2017 12:55:45 -0700 (PDT) Received: from localhost ([::1]:50411 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dul60-0008Pw-PZ for importer@patchew.org; Wed, 20 Sep 2017 15:55:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37860) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dul0U-0004Jb-VX for qemu-devel@nongnu.org; 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Wed, 20 Sep 2017 12:50:00 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Igor Mammedov , Eduardo Habkost , Aurelien Jarno , Yongbok Kim , Marcel Apfelbaum Date: Wed, 20 Sep 2017 16:49:33 -0300 Message-Id: <20170920194934.23071-6-f4bug@amsat.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170920194934.23071-1-f4bug@amsat.org> References: <20170920194934.23071-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH v4 5/6] mips: MIPSCPU model subclasses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , James Hogan , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Igor Mammedov Register separate QOM types for each mips cpu model, so it would be possible to reuse generic CPU creation routines. Signed-off-by: Igor Mammedov Signed-off-by: Philippe Mathieu-Daud=C3=A9 [PMD: use internal.h, use void* to hold cpu_def in MIPSCPUClass, mark MIPSCPU abstract, address Eduardo Habkost review] Tested-by: James Hogan Reviewed-by: Eduardo Habkost --- target/mips/cpu-qom.h | 1 + target/mips/internal.h | 59 ++++++++++++++++++++++++++++++++++++++++= ++++ target/mips/cpu.c | 50 ++++++++++++++++++++++++++++++++++++- target/mips/translate.c | 13 +++++----- target/mips/translate_init.c | 58 ++--------------------------------------= --- 5 files changed, 117 insertions(+), 64 deletions(-) diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 3f5bf23823..ee58606afe 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -49,6 +49,7 @@ typedef struct MIPSCPUClass { =20 DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); + const struct mips_def_t *cpu_def; } MIPSCPUClass; =20 typedef struct MIPSCPU MIPSCPU; diff --git a/target/mips/internal.h b/target/mips/internal.h index cf4c9db427..45ded3484c 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -7,6 +7,65 @@ #ifndef MIPS_INTERNAL_H #define MIPS_INTERNAL_H =20 + +/* MMU types, the first four entries have the same layout as the + CP0C0_MT field. */ +enum mips_mmu_types { + MMU_TYPE_NONE, + MMU_TYPE_R4000, + MMU_TYPE_RESERVED, + MMU_TYPE_FMT, + MMU_TYPE_R3000, + MMU_TYPE_R6000, + MMU_TYPE_R8000 +}; + +struct mips_def_t { + const char *name; + int32_t CP0_PRid; + int32_t CP0_Config0; + int32_t CP0_Config1; + int32_t CP0_Config2; + int32_t CP0_Config3; + int32_t CP0_Config4; + int32_t CP0_Config4_rw_bitmask; + int32_t CP0_Config5; + int32_t CP0_Config5_rw_bitmask; + int32_t CP0_Config6; + int32_t CP0_Config7; + target_ulong CP0_LLAddr_rw_bitmask; + int CP0_LLAddr_shift; + int32_t SYNCI_Step; + int32_t CCRes; + int32_t CP0_Status_rw_bitmask; + int32_t CP0_TCStatus_rw_bitmask; + int32_t CP0_SRSCtl; + int32_t CP1_fcr0; + int32_t CP1_fcr31_rw_bitmask; + int32_t CP1_fcr31; + int32_t MSAIR; + int32_t SEGBITS; + int32_t PABITS; + int32_t CP0_SRSConf0_rw_bitmask; + int32_t CP0_SRSConf0; + int32_t CP0_SRSConf1_rw_bitmask; + int32_t CP0_SRSConf1; + int32_t CP0_SRSConf2_rw_bitmask; + int32_t CP0_SRSConf2; + int32_t CP0_SRSConf3_rw_bitmask; + int32_t CP0_SRSConf3; + int32_t CP0_SRSConf4_rw_bitmask; + int32_t CP0_SRSConf4; + int32_t CP0_PageGrain_rw_bitmask; + int32_t CP0_PageGrain; + target_ulong CP0_EBaseWG_rw_bitmask; + int insn_flags; + enum mips_mmu_types mmu_type; +}; + +extern const struct mips_def_t mips_defs[]; +extern const int mips_defs_number; + enum CPUMIPSMSADataFormat { DF_BYTE =3D 0, DF_HALF, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e3ef835599..1a9a3ed94d 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -146,14 +146,36 @@ static void mips_cpu_initfn(Object *obj) CPUState *cs =3D CPU(obj); MIPSCPU *cpu =3D MIPS_CPU(obj); CPUMIPSState *env =3D &cpu->env; + MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(obj); =20 cs->env_ptr =3D env; + env->cpu_model =3D mcc->cpu_def; =20 if (tcg_enabled()) { mips_tcg_init(); } } =20 +static char *mips_cpu_type_name(const char *cpu_model) +{ + return g_strdup_printf("%s-" TYPE_MIPS_CPU, cpu_model); +} + +static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) +{ + ObjectClass *oc; + char *typename; + + if (cpu_model =3D=3D NULL) { + return NULL; + } + + typename =3D mips_cpu_type_name(cpu_model); + oc =3D object_class_by_name(typename); + g_free(typename); + return oc; +} + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(c); @@ -166,6 +188,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) mcc->parent_reset =3D cc->reset; cc->reset =3D mips_cpu_reset; =20 + cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; cc->do_interrupt =3D mips_cpu_do_interrupt; cc->cpu_exec_interrupt =3D mips_cpu_exec_interrupt; @@ -193,14 +216,39 @@ static const TypeInfo mips_cpu_type_info =3D { .parent =3D TYPE_CPU, .instance_size =3D sizeof(MIPSCPU), .instance_init =3D mips_cpu_initfn, - .abstract =3D false, + .abstract =3D true, .class_size =3D sizeof(MIPSCPUClass), .class_init =3D mips_cpu_class_init, }; =20 +static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data) +{ + MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(oc); + mcc->cpu_def =3D data; +} + +static void mips_register_cpudef_type(const struct mips_def_t *def) +{ + char *typename =3D mips_cpu_type_name(def->name); + TypeInfo ti =3D { + .name =3D typename, + .parent =3D TYPE_MIPS_CPU, + .class_init =3D mips_cpu_cpudef_class_init, + .class_data =3D (void *)def, + }; + + type_register(&ti); + g_free(typename); +} + static void mips_cpu_register_types(void) { + int i; + type_register_static(&mips_cpu_type_info); + for (i =3D 0; i < mips_defs_number; i++) { + mips_register_cpudef_type(&mips_defs[i]); + } } =20 type_init(mips_cpu_register_types) diff --git a/target/mips/translate.c b/target/mips/translate.c index 94c38e8755..f7128bc91d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20525,16 +20525,15 @@ void cpu_mips_realize_env(CPUMIPSState *env) =20 MIPSCPU *cpu_mips_init(const char *cpu_model) { + ObjectClass *oc; MIPSCPU *cpu; - CPUMIPSState *env; - const mips_def_t *def; =20 - def =3D cpu_mips_find_by_name(cpu_model); - if (!def) + oc =3D cpu_class_by_name(TYPE_MIPS_CPU, cpu_model); + if (oc =3D=3D NULL) { return NULL; - cpu =3D MIPS_CPU(object_new(TYPE_MIPS_CPU)); - env =3D &cpu->env; - env->cpu_model =3D def; + } + + cpu =3D MIPS_CPU(object_new(object_class_get_name(oc))); =20 object_property_set_bool(OBJECT(cpu), true, "realized", NULL); =20 diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c index 255d25bacd..8bbded46c4 100644 --- a/target/mips/translate_init.c +++ b/target/mips/translate_init.c @@ -51,64 +51,9 @@ #define MIPS_CONFIG5 \ ((0 << CP0C5_M)) =20 -/* MMU types, the first four entries have the same layout as the - CP0C0_MT field. */ -enum mips_mmu_types { - MMU_TYPE_NONE, - MMU_TYPE_R4000, - MMU_TYPE_RESERVED, - MMU_TYPE_FMT, - MMU_TYPE_R3000, - MMU_TYPE_R6000, - MMU_TYPE_R8000 -}; - -struct mips_def_t { - const char *name; - int32_t CP0_PRid; - int32_t CP0_Config0; - int32_t CP0_Config1; - int32_t CP0_Config2; - int32_t CP0_Config3; - int32_t CP0_Config4; - int32_t CP0_Config4_rw_bitmask; - int32_t CP0_Config5; - int32_t CP0_Config5_rw_bitmask; - int32_t CP0_Config6; - int32_t CP0_Config7; - target_ulong CP0_LLAddr_rw_bitmask; - int CP0_LLAddr_shift; - int32_t SYNCI_Step; - int32_t CCRes; - int32_t CP0_Status_rw_bitmask; - int32_t CP0_TCStatus_rw_bitmask; - int32_t CP0_SRSCtl; - int32_t CP1_fcr0; - int32_t CP1_fcr31_rw_bitmask; - int32_t CP1_fcr31; - int32_t MSAIR; - int32_t SEGBITS; - int32_t PABITS; - int32_t CP0_SRSConf0_rw_bitmask; - int32_t CP0_SRSConf0; - int32_t CP0_SRSConf1_rw_bitmask; - int32_t CP0_SRSConf1; - int32_t CP0_SRSConf2_rw_bitmask; - int32_t CP0_SRSConf2; - int32_t CP0_SRSConf3_rw_bitmask; - int32_t CP0_SRSConf3; - int32_t CP0_SRSConf4_rw_bitmask; - int32_t CP0_SRSConf4; - int32_t CP0_PageGrain_rw_bitmask; - int32_t CP0_PageGrain; - target_ulong CP0_EBaseWG_rw_bitmask; - int insn_flags; - enum mips_mmu_types mmu_type; -}; - /*************************************************************************= ****/ /* MIPS CPU definitions */ -static const mips_def_t mips_defs[] =3D +const mips_def_t mips_defs[] =3D { { .name =3D "4Kc", @@ -808,6 +753,7 @@ static const mips_def_t mips_defs[] =3D =20 #endif }; +const int mips_defs_number =3D ARRAY_SIZE(mips_defs); =20 static const mips_def_t *cpu_mips_find_by_name (const char *name) { --=20 2.14.1 From nobody Fri May 17 22:06:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150593745304263.574996224970505; Wed, 20 Sep 2017 12:57:33 -0700 (PDT) Received: from localhost ([::1]:50417 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dul7k-0001Ky-9v for importer@patchew.org; Wed, 20 Sep 2017 15:57:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37932) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dul0c-0004SO-HT for qemu-devel@nongnu.org; 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Wed, 20 Sep 2017 12:50:05 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Igor Mammedov , Eduardo Habkost , Aurelien Jarno , Yongbok Kim , Marcel Apfelbaum Date: Wed, 20 Sep 2017 16:49:34 -0300 Message-Id: <20170920194934.23071-7-f4bug@amsat.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170920194934.23071-1-f4bug@amsat.org> References: <20170920194934.23071-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::241 Subject: [Qemu-devel] [PATCH v4 6/6] mips: replace cpu_mips_init() with cpu_generic_init() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , James Hogan , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Igor Mammedov now cpu_mips_init() reimplements subset of cpu_generic_init() tasks, so just drop it and use cpu_generic_init() directly. Signed-off-by: Igor Mammedov Reviewed-by: Herv=C3=A9 Poussineau Signed-off-by: Philippe Mathieu-Daud=C3=A9 [PMD: use internal.h instead of cpu.h] Tested-by: James Hogan Reviewed-by: Eduardo Habkost --- target/mips/cpu.h | 3 +-- hw/mips/cps.c | 2 +- hw/mips/mips_fulong2e.c | 2 +- hw/mips/mips_jazz.c | 2 +- hw/mips/mips_malta.c | 2 +- hw/mips/mips_mipssim.c | 2 +- hw/mips/mips_r4k.c | 2 +- target/mips/translate.c | 17 ----------------- 8 files changed, 7 insertions(+), 25 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 2f81e0f950..66265e4eb6 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -737,10 +737,9 @@ enum { */ #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 =20 -MIPSCPU *cpu_mips_init(const char *cpu_model); int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); =20 -#define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model)) +#define cpu_init(cpu_model) cpu_generic_init(TYPE_MIPS_CPU, cpu_model) bool cpu_supports_cps_smp(const char *cpu_model); bool cpu_supports_isa(const char *cpu_model, unsigned int isa); void cpu_set_exception_base(int vp_index, target_ulong address); diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 79d4c5e30a..fe5c630af6 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -71,7 +71,7 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) bool itu_present =3D false; =20 for (i =3D 0; i < s->num_vp; i++) { - cpu =3D cpu_mips_init(s->cpu_model); + cpu =3D MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, s->cpu_model)); =20 /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index 439a3d7a66..75318680e1 100644 --- a/hw/mips/mips_fulong2e.c +++ b/hw/mips/mips_fulong2e.c @@ -280,7 +280,7 @@ static void mips_fulong2e_init(MachineState *machine) if (cpu_model =3D=3D NULL) { cpu_model =3D "Loongson-2E"; } - cpu =3D cpu_mips_init(cpu_model); + cpu =3D MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model)); env =3D &cpu->env; =20 qemu_register_reset(main_cpu_reset, cpu); diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index ae10670efd..7e6626dc88 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -151,7 +151,7 @@ static void mips_jazz_init(MachineState *machine, if (cpu_model =3D=3D NULL) { cpu_model =3D "R4000"; } - cpu =3D cpu_mips_init(cpu_model); + cpu =3D MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model)); env =3D &cpu->env; qemu_register_reset(main_cpu_reset, cpu); =20 diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index e87cd3230b..2adb9bcf89 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -931,7 +931,7 @@ static void create_cpu_without_cps(const char *cpu_mode= l, int i; =20 for (i =3D 0; i < smp_cpus; i++) { - cpu =3D cpu_mips_init(cpu_model); + cpu =3D MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model)); =20 /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c index 49cd38d680..a092072e2a 100644 --- a/hw/mips/mips_mipssim.c +++ b/hw/mips/mips_mipssim.c @@ -163,7 +163,7 @@ mips_mipssim_init(MachineState *machine) cpu_model =3D "24Kf"; #endif } - cpu =3D cpu_mips_init(cpu_model); + cpu =3D MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model)); env =3D &cpu->env; =20 reset_info =3D g_malloc0(sizeof(ResetData)); diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index 7efee94431..1272d4ef9d 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -193,7 +193,7 @@ void mips_r4k_init(MachineState *machine) cpu_model =3D "24Kf"; #endif } - cpu =3D cpu_mips_init(cpu_model); + cpu =3D MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model)); env =3D &cpu->env; =20 reset_info =3D g_malloc0(sizeof(ResetData)); diff --git a/target/mips/translate.c b/target/mips/translate.c index f7128bc91d..d16d879df7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20523,23 +20523,6 @@ void cpu_mips_realize_env(CPUMIPSState *env) mvp_init(env, env->cpu_model); } =20 -MIPSCPU *cpu_mips_init(const char *cpu_model) -{ - ObjectClass *oc; - MIPSCPU *cpu; - - oc =3D cpu_class_by_name(TYPE_MIPS_CPU, cpu_model); - if (oc =3D=3D NULL) { - return NULL; - } - - cpu =3D MIPS_CPU(object_new(object_class_get_name(oc))); - - object_property_set_bool(OBJECT(cpu), true, "realized", NULL); - - return cpu; -} - bool cpu_supports_cps_smp(const char *cpu_model) { const mips_def_t *def =3D cpu_mips_find_by_name(cpu_model); --=20 2.14.1