From nobody Mon May 6 16:02:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150583046929956.6872975597563; Tue, 19 Sep 2017 07:14:29 -0700 (PDT) Received: from localhost ([::1]:43162 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1duJIC-0006DZ-9U for importer@patchew.org; Tue, 19 Sep 2017 10:14:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44396) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1duJH4-0005WL-I0 for qemu-devel@nongnu.org; Tue, 19 Sep 2017 10:13:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1duJGy-0004Bz-RC for qemu-devel@nongnu.org; Tue, 19 Sep 2017 10:13:18 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37644) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1duJGy-0004BY-I4; Tue, 19 Sep 2017 10:13:12 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id CC8737EA9A; Tue, 19 Sep 2017 14:13:10 +0000 (UTC) Received: from red.redhat.com (ovpn-124-97.rdu2.redhat.com [10.10.124.97]) by smtp.corp.redhat.com (Postfix) with ESMTP id D77BC600C2; Tue, 19 Sep 2017 14:13:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com CC8737EA9A Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=eblake@redhat.com From: Eric Blake To: qemu-devel@nongnu.org Date: Tue, 19 Sep 2017 09:13:07 -0500 Message-Id: <20170919141307.23113-1-eblake@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Tue, 19 Sep 2017 14:13:11 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH] mips: Improve macro parenthesization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-trivial@nongnu.org, Yongbok Kim , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Although none of the existing macro call-sites were broken, it's always better to write macros that properly parenthesize arguments that can be complex expressions, so that the intended order of operations is not broken. Signed-off-by: Eric Blake Reviewed-by: Yongbok Kim --- target/mips/dsp_helper.c | 56 ++++++++++++++++++++++++--------------------= ---- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/target/mips/dsp_helper.c b/target/mips/dsp_helper.c index dc707934ea..f152fea34a 100644 --- a/target/mips/dsp_helper.c +++ b/target/mips/dsp_helper.c @@ -45,9 +45,9 @@ typedef union { } DSP64Value; /*** MIPS DSP internal functions begin ***/ -#define MIPSDSP_ABS(x) (((x) >=3D 0) ? x : -x) -#define MIPSDSP_OVERFLOW_ADD(a, b, c, d) (~(a ^ b) & (a ^ c) & d) -#define MIPSDSP_OVERFLOW_SUB(a, b, c, d) ((a ^ b) & (a ^ c) & d) +#define MIPSDSP_ABS(x) (((x) >=3D 0) ? (x) : -(x)) +#define MIPSDSP_OVERFLOW_ADD(a, b, c, d) (~((a) ^ (b)) & ((a) ^ (c)) & (d)) +#define MIPSDSP_OVERFLOW_SUB(a, b, c, d) (((a) ^ (b)) & ((a) ^ (c)) & (d)) static inline void set_DSPControl_overflow_flag(uint32_t flag, int positio= n, CPUMIPSState *env) @@ -1047,47 +1047,47 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, u= int32_t b) #define MIPSDSP_SPLIT32_8(num, a, b, c, d) \ do { \ - a =3D (num >> 24) & MIPSDSP_Q0; \ - b =3D (num >> 16) & MIPSDSP_Q0; \ - c =3D (num >> 8) & MIPSDSP_Q0; \ - d =3D num & MIPSDSP_Q0; \ + a =3D ((num) >> 24) & MIPSDSP_Q0; \ + b =3D ((num) >> 16) & MIPSDSP_Q0; \ + c =3D ((num) >> 8) & MIPSDSP_Q0; \ + d =3D (num) & MIPSDSP_Q0; \ } while (0) #define MIPSDSP_SPLIT32_16(num, a, b) \ do { \ - a =3D (num >> 16) & MIPSDSP_LO; \ - b =3D num & MIPSDSP_LO; \ + a =3D ((num) >> 16) & MIPSDSP_LO; \ + b =3D (num) & MIPSDSP_LO; \ } while (0) -#define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \ - (((uint32_t)a << 24) | \ - (((uint32_t)b << 16) | \ - (((uint32_t)c << 8) | \ - ((uint32_t)d & 0xFF))))) -#define MIPSDSP_RETURN32_16(a, b) ((target_long)(int32_t) \ - (((uint32_t)a << 16) | \ - ((uint32_t)b & 0xFFFF))) +#define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \ + (((uint32_t)(a) << 24) | \ + ((uint32_t)(b) << 16) | \ + ((uint32_t)(c) << 8) | \ + ((uint32_t)(d) & 0xFF))) +#define MIPSDSP_RETURN32_16(a, b) ((target_long)(int32_t) \ + (((uint32_t)(a) << 16) | \ + ((uint32_t)(b) & 0xFFFF))) #ifdef TARGET_MIPS64 #define MIPSDSP_SPLIT64_16(num, a, b, c, d) \ do { \ - a =3D (num >> 48) & MIPSDSP_LO; \ - b =3D (num >> 32) & MIPSDSP_LO; \ - c =3D (num >> 16) & MIPSDSP_LO; \ - d =3D num & MIPSDSP_LO; \ + a =3D ((num) >> 48) & MIPSDSP_LO; \ + b =3D ((num) >> 32) & MIPSDSP_LO; \ + c =3D ((num) >> 16) & MIPSDSP_LO; \ + d =3D (num) & MIPSDSP_LO; \ } while (0) #define MIPSDSP_SPLIT64_32(num, a, b) \ do { \ - a =3D (num >> 32) & MIPSDSP_LLO; \ - b =3D num & MIPSDSP_LLO; \ + a =3D ((num) >> 32) & MIPSDSP_LLO; \ + b =3D (num) & MIPSDSP_LLO; \ } while (0) -#define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)a << 48) | \ - ((uint64_t)b << 32) | \ - ((uint64_t)c << 16) | \ - (uint64_t)d) -#define MIPSDSP_RETURN64_32(a, b) (((uint64_t)a << 32) | (uint64_t)b) +#define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)(a) << 48) | \ + ((uint64_t)(b) << 32) | \ + ((uint64_t)(c) << 16) | \ + (uint64_t)(d)) +#define MIPSDSP_RETURN64_32(a, b) (((uint64_t)(a) << 32) | (uint64_t= )(b)) #endif /** DSP Arithmetic Sub-class insns **/ --=20 2.13.5