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X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH 08/17] imx_fec: Add support for multiple Tx DMA rings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , Jason Wang , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" More recent version of the IP block support more than one Tx DMA ring, so add the code implementing that feature. Cc: Peter Maydell Cc: Jason Wang Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/net/imx_fec.c | 97 +++++++++++++++++++++++++++++++++++++++-----= ---- include/hw/net/imx_fec.h | 23 +++++++++++- 2 files changed, 101 insertions(+), 19 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index bd62d7a75f..6045ffe673 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -196,6 +196,17 @@ static const char *imx_eth_reg_name(IMXFECState *s, ui= nt32_t index) } } =20 +static const VMStateDescription vmstate_imx_eth_tx_ring =3D { + .name =3D "fec-tx-ring", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(descriptor, IMXFECTxRing), + VMSTATE_UINT32(tdsr, IMXFECTxRing), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_imx_eth =3D { .name =3D TYPE_IMX_FEC, .version_id =3D 2, @@ -203,8 +214,10 @@ static const VMStateDescription vmstate_imx_eth =3D { .fields =3D (VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX), VMSTATE_UINT32(rx_descriptor, IMXFECState), - VMSTATE_UINT32(tx_descriptor, IMXFECState), - + VMSTATE_STRUCT_ARRAY(tx_ring, IMXFECState, + ENET_TX_RING_NUM, + 1, vmstate_imx_eth_tx_ring, + IMXFECTxRing), VMSTATE_UINT32(phy_status, IMXFECState), VMSTATE_UINT32(phy_control, IMXFECState), VMSTATE_UINT32(phy_advertise, IMXFECState), @@ -407,7 +420,7 @@ static void imx_fec_do_tx(IMXFECState *s) int frame_size =3D 0, descnt =3D 0; uint8_t frame[ENET_MAX_FRAME_SIZE]; uint8_t *ptr =3D frame; - uint32_t addr =3D s->tx_descriptor; + uint32_t addr =3D s->tx_ring[0].descriptor; =20 while (descnt++ < IMX_MAX_DESC) { IMXFECBufDesc bd; @@ -448,17 +461,38 @@ static void imx_fec_do_tx(IMXFECState *s) } } =20 - s->tx_descriptor =3D addr; + s->tx_ring[0].descriptor =3D addr; =20 imx_eth_update(s); } =20 -static void imx_enet_do_tx(IMXFECState *s) +static void imx_enet_do_tx(IMXFECState *s, uint32_t index) { int frame_size =3D 0, descnt =3D 0; uint8_t frame[ENET_MAX_FRAME_SIZE]; uint8_t *ptr =3D frame; - uint32_t addr =3D s->tx_descriptor; + IMXFECTxRing *ring; + uint32_t addr; + + switch (index) { + case ENET_TDAR: + ring =3D &s->tx_ring[0]; + break; + case ENET_TDAR1: + ring =3D &s->tx_ring[1]; + break; + case ENET_TDAR2: + ring =3D &s->tx_ring[2]; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bogus value for index %x\n", + __func__, index); + abort(); + break; + } + + addr =3D ring->descriptor; =20 while (descnt++ < IMX_MAX_DESC) { IMXENETBufDesc bd; @@ -502,32 +536,32 @@ static void imx_enet_do_tx(IMXFECState *s) ptr =3D frame; frame_size =3D 0; if (bd.option & ENET_BD_TX_INT) { - s->regs[ENET_EIR] |=3D ENET_INT_TXF; + s->regs[ENET_EIR] |=3D ring->int_txf; } } if (bd.option & ENET_BD_TX_INT) { - s->regs[ENET_EIR] |=3D ENET_INT_TXB; + s->regs[ENET_EIR] |=3D ring->int_txb; } bd.flags &=3D ~ENET_BD_R; /* Write back the modified descriptor. */ imx_enet_write_bd(&bd, addr); /* Advance to the next descriptor. */ if ((bd.flags & ENET_BD_W) !=3D 0) { - addr =3D s->regs[ENET_TDSR]; + addr =3D s->regs[ring->tdsr]; } else { addr +=3D sizeof(bd); } } =20 - s->tx_descriptor =3D addr; + ring->descriptor =3D addr; =20 imx_eth_update(s); } =20 -static void imx_eth_do_tx(IMXFECState *s) +static void imx_eth_do_tx(IMXFECState *s, uint32_t index) { if (!s->is_fec && (s->regs[ENET_ECR] & ENET_ECR_EN1588)) { - imx_enet_do_tx(s); + imx_enet_do_tx(s, index); } else { imx_fec_do_tx(s); } @@ -586,7 +620,22 @@ static void imx_eth_reset(DeviceState *d) } =20 s->rx_descriptor =3D 0; - s->tx_descriptor =3D 0; + + s->tx_ring[0].tdsr =3D ENET_TDSR; + s->tx_ring[1].tdsr =3D ENET_TDSR1; + s->tx_ring[2].tdsr =3D ENET_TDSR2; + + s->tx_ring[0].int_txf =3D ENET_INT_TXF; + s->tx_ring[1].int_txf =3D ENET_INT_TXF1; + s->tx_ring[2].int_txf =3D ENET_INT_TXF2; + + s->tx_ring[0].int_txb =3D ENET_INT_TXB; + s->tx_ring[1].int_txb =3D ENET_INT_TXB1; + s->tx_ring[2].int_txb =3D ENET_INT_TXB2; + + s->tx_ring[0].descriptor =3D 0; + s->tx_ring[1].descriptor =3D 0; + s->tx_ring[2].descriptor =3D 0; =20 /* We also reset the PHY */ phy_reset(s); @@ -814,10 +863,12 @@ static void imx_eth_write(void *opaque, hwaddr offset= , uint64_t value, s->regs[index] =3D 0; } break; + case ENET_TDAR1: /* FALLTHROUGH */ + case ENET_TDAR2: /* FALLTHROUGH */ case ENET_TDAR: if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { s->regs[index] =3D ENET_TDAR_TDAR; - imx_eth_do_tx(s); + imx_eth_do_tx(s, index); } s->regs[index] =3D 0; break; @@ -829,8 +880,12 @@ static void imx_eth_write(void *opaque, hwaddr offset,= uint64_t value, if ((s->regs[index] & ENET_ECR_ETHEREN) =3D=3D 0) { s->regs[ENET_RDAR] =3D 0; s->rx_descriptor =3D s->regs[ENET_RDSR]; - s->regs[ENET_TDAR] =3D 0; - s->tx_descriptor =3D s->regs[ENET_TDSR]; + s->regs[ENET_TDAR] =3D 0; + s->regs[ENET_TDAR1] =3D 0; + s->regs[ENET_TDAR2] =3D 0; + s->tx_ring[0].descriptor =3D s->regs[ENET_TDSR]; + s->tx_ring[1].descriptor =3D s->regs[ENET_TDSR1]; + s->tx_ring[2].descriptor =3D s->regs[ENET_TDSR2]; } break; case ENET_MMFR: @@ -908,7 +963,15 @@ static void imx_eth_write(void *opaque, hwaddr offset,= uint64_t value, } else { s->regs[index] =3D value & ~7; } - s->tx_descriptor =3D s->regs[index]; + s->tx_ring[0].descriptor =3D s->regs[index]; + break; + case ENET_TDSR1: + s->regs[index] =3D value & ~7; + s->tx_ring[1].descriptor =3D s->regs[index]; + break; + case ENET_TDSR2: + s->regs[index] =3D value & ~7; + s->tx_ring[2].descriptor =3D s->regs[index]; break; case ENET_MRBR: s->regs[index] =3D value & 0x00003ff0; diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 20a6aa98b4..40bd29771f 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -52,6 +52,8 @@ #define ENET_TFWR 81 #define ENET_FRBR 83 #define ENET_FRSR 84 +#define ENET_TDSR1 89 +#define ENET_TDSR2 92 #define ENET_RDSR 96 #define ENET_TDSR 97 #define ENET_MRBR 98 @@ -66,6 +68,8 @@ #define ENET_FTRL 108 #define ENET_TACC 112 #define ENET_RACC 113 +#define ENET_TDAR1 121 +#define ENET_TDAR2 123 #define ENET_MIIGSK_CFGR 192 #define ENET_MIIGSK_ENR 194 #define ENET_ATCR 256 @@ -106,13 +110,18 @@ #define ENET_INT_WAKEUP (1 << 17) #define ENET_INT_TS_AVAIL (1 << 16) #define ENET_INT_TS_TIMER (1 << 15) +#define ENET_INT_TXF2 (1 << 7) +#define ENET_INT_TXB2 (1 << 6) +#define ENET_INT_TXF1 (1 << 3) +#define ENET_INT_TXB1 (1 << 2) =20 #define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BAB= T | \ ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB= | \ ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII= | \ ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL= | \ ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKE= UP | \ - ENET_INT_TS_AVAIL) + ENET_INT_TS_AVAIL | ENET_INT_TXF1 | ENET_I= NT_TXB1 |\ + ENET_INT_TXF2 | ENET_INT_TXB2) =20 /* RDAR */ #define ENET_RDAR_RDAR (1 << 24) @@ -233,6 +242,15 @@ typedef struct { =20 #define ENET_BD_BDU (1 << 31) =20 +#define ENET_TX_RING_NUM 3 + +typedef struct IMXFECTxRing { + uint32_t descriptor; + uint32_t tdsr; + uint32_t int_txf; + uint32_t int_txb; +} IMXFECTxRing; + typedef struct IMXFECState { /*< private >*/ SysBusDevice parent_obj; @@ -245,7 +263,8 @@ typedef struct IMXFECState { =20 uint32_t regs[ENET_MAX]; uint32_t rx_descriptor; - uint32_t tx_descriptor; + + IMXFECTxRing tx_ring[ENET_TX_RING_NUM]; =20 uint32_t phy_status; uint32_t phy_control; --=20 2.13.5