From nobody Wed Nov 5 05:27:30 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505764784839765.9662992362314; Mon, 18 Sep 2017 12:59:44 -0700 (PDT) Received: from localhost ([::1]:38656 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du2Cm-0005Ix-3m for importer@patchew.org; Mon, 18 Sep 2017 15:59:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37641) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du256-0007Bk-DK for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1du253-0006RW-6f for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:48 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:33830) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1du250-0006Oo-GF; Mon, 18 Sep 2017 15:51:42 -0400 Received: by mail-pg0-x243.google.com with SMTP id u18so658895pgo.1; Mon, 18 Sep 2017 12:51:42 -0700 (PDT) Received: from squirtle.westlake.spaceflightindustries.com ([173.226.206.194]) by smtp.gmail.com with ESMTPSA id d186sm200791pfd.117.2017.09.18.12.51.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Sep 2017 12:51:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N9QB2DN+EchfJsJbXlsKbcMgz3nhojo1joW5GYmvljw=; b=pNN2Pz6eBhFo5dnTKDBacvMdW9pyBeCD7lfFR499jdJZJBclOmYgVxWO/m+nZM88Ak 2CO8nVqD+PXFil/SL3pMLazkNXqPrqJh8BqAgBNtabUqvkUT8UPn3eW+kKo1sNcXZ5fL CM6Vigw6V/sGJitEB+z95JyayWC7CaX0KhzNuhsASCbQhc4AguuSMViD8N2u6DDzbuTM JawI4cTREKvbviu+mTQvDHjY6XzUyWHZHsSVL9ktZ/xhnqchY4EerjOd97pqAkaSm308 SZrZvlCksR6YxVmFvGwTD6u4Md+JCPH8smK4uDh7e80TC8g2kEDqFi421TlYXTdsr9Kc cP6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N9QB2DN+EchfJsJbXlsKbcMgz3nhojo1joW5GYmvljw=; b=mu5nsCdNQj+j0xTQ6EYbmSOBaXhP4rq06coXyhld0lyJCpkAxjloGJ/JC7Aw/b4oyw y/vGZx8tDenIUQB6JXJ4X5C4dvI5gRa+J94INiJP+j4x5TdW6lV8HumIYrN0gW9h+jhe JbYBbkimvounhk8CkvGkmSzaynzCzfS0pNaJMI6wJd0XdxmRuO2eWO9zHz9Us4QeTswE GMYZYHiWKhvQ71v2iAobox2RFjcNGK0T79ItFGryXQrfl1lbH1AhmHPAkNs46iyPbDba 4WEbLUgtXjadWA1ofLouk5ODt4Rx6pUE7nKGRxGdRLFawLxDfVgG71uDkKu3qnm9W9op 4HKQ== X-Gm-Message-State: AHPjjUjvLpKUK/klLKXAnS8NzQWfQ8pRx/ljifQJ58Y4CwnJ5Y7qQHiX 5b6sgbPvq5ws5Vw5wsA= X-Google-Smtp-Source: ADKCNb71/N8mEGUIss7vGWJiC8l7fsoA99/eCHBbM1Hiwyh8Fl38sH/DRGfxTBj+/kdrvcEw/h8ESg== X-Received: by 10.101.86.79 with SMTP id m15mr32906450pgs.157.1505764301248; Mon, 18 Sep 2017 12:51:41 -0700 (PDT) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 18 Sep 2017 12:51:00 -0700 Message-Id: <20170918195100.17593-18-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918195100.17593-1-andrew.smirnov@gmail.com> References: <20170918195100.17593-1-andrew.smirnov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH 17/17] Implement support for i.MX7 Sabre board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Peter Maydell Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/arm/Makefile.objs | 2 +- hw/arm/mcimx7d-sabre.c | 100 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 hw/arm/mcimx7d-sabre.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 33f6051ae3..fc4a963de8 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -19,5 +19,5 @@ obj-$(CONFIG_FSL_IMX31) +=3D fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) +=3D fsl-imx6.o sabrelite.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_soc.o aspeed.o obj-$(CONFIG_MPS2) +=3D mps2.o -obj-$(CONFIG_FSL_IMX7) +=3D fsl-imx7.o +obj-$(CONFIG_FSL_IMX7) +=3D fsl-imx7.o mcimx7d-sabre.o =20 diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c new file mode 100644 index 0000000000..34e3933db8 --- /dev/null +++ b/hw/arm/mcimx7d-sabre.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * MCIMX7D_SABRE Board System emulation. + * + * Author: Andrey Smirnov + * + * This code is licensed under the GPL, version 2 or later. + * See the file `COPYING' in the top level directory. + * + * It (partially) emulates a mcimx7d_sabre board, with a Freescale + * i.MX7 SoC + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/fsl-imx7.h" +#include "hw/boards.h" +#include "sysemu/sysemu.h" +#include "sysemu/device_tree.h" +#include "qemu/error-report.h" +#include "sysemu/qtest.h" +#include "net/net.h" + +typedef struct { + FslIMX7State soc; + MemoryRegion ram; +} MCIMX7Sabre; + +static void mcimx7d_add_psci_node(const struct arm_boot_info *boot_info, v= oid *fdt) +{ + const char comp[] =3D "arm,psci-0.2\0arm,psci"; + + qemu_fdt_add_subnode(fdt, "/psci"); + qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); + qemu_fdt_setprop_string(fdt, "/psci", "method", "smc"); +} + +static void mcimx7d_sabre_init(MachineState *machine) +{ + static struct arm_boot_info boot_info; + MCIMX7Sabre *s =3D g_new0(MCIMX7Sabre, 1); + Object *soc; + int i; + + if (machine->ram_size > FSL_IMX7_MMDC_SIZE) { + error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)= ", + machine->ram_size, FSL_IMX7_MMDC_SIZE); + exit(1); + } + + boot_info =3D (struct arm_boot_info) { + .loader_start =3D FSL_IMX7_MMDC_ADDR, + .board_id =3D -1, + .ram_size =3D machine->ram_size, + .kernel_filename =3D machine->kernel_filename, + .kernel_cmdline =3D machine->kernel_cmdline, + .initrd_filename =3D machine->initrd_filename, + .nb_cpus =3D smp_cpus, + .modify_dtb =3D mcimx7d_add_psci_node, + }; + + object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX7); + soc =3D OBJECT(&s->soc); + object_property_add_child(OBJECT(machine), "soc", soc, &error_fatal); + object_property_set_bool(soc, true, "realized", &error_fatal); + + memory_region_allocate_system_memory(&s->ram, NULL, "mcimx7d-sabre.ram= ", + machine->ram_size); + memory_region_add_subregion(get_system_memory(), + FSL_IMX7_MMDC_ADDR, &s->ram); + + for (i =3D 0; i < FSL_IMX7_NUM_USDHCS; i++) { + BusState *bus; + DeviceState *carddev; + DriveInfo *di; + BlockBackend *blk; + + di =3D drive_get_next(IF_SD); + blk =3D di ? blk_by_legacy_dinfo(di) : NULL; + bus =3D qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus"); + carddev =3D qdev_create(bus, TYPE_SD_CARD); + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); + object_property_set_bool(OBJECT(carddev), true, "realized", &error= _fatal); + } + + if (!qtest_enabled()) { + arm_load_kernel(&s->soc.cpu[0], &boot_info); + } +} + +static void mcimx7d_sabre_machine_init(MachineClass *mc) +{ + mc->desc =3D "Freescale i.MX7 DUAL SABRE (Cortex A7)"; + mc->init =3D mcimx7d_sabre_init; + mc->max_cpus =3D FSL_IMX7_NUM_CPUS; + mc->ignore_memory_transaction_failures =3D true; +} +DEFINE_MACHINE("mcimx7d-sabre", mcimx7d_sabre_machine_init) --=20 2.13.5