From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505764859135507.83760871100367; Mon, 18 Sep 2017 13:00:59 -0700 (PDT) Received: from localhost ([::1]:38666 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du2Dy-0006Vx-7u for importer@patchew.org; Mon, 18 Sep 2017 16:00:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37291) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du24r-0006lU-58 for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1du24q-0006Ga-8P for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:33 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:36998) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1du24l-0006E4-Us; Mon, 18 Sep 2017 15:51:28 -0400 Received: by mail-pg0-x242.google.com with SMTP id v5so767411pgn.4; Mon, 18 Sep 2017 12:51:26 -0700 (PDT) Received: from squirtle.westlake.spaceflightindustries.com ([173.226.206.194]) by smtp.gmail.com with ESMTPSA id d186sm200791pfd.117.2017.09.18.12.51.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Sep 2017 12:51:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PPFJJFGlz6LRNHc5NYzxKFNjJDNoIVP9JQBS0o4H3QE=; b=lITy7IMEvHkQjyM34xV2lrEPZ1FRqo2tqMg3i7lTkeyK7W6V8OyXI8YBMzD9Y6I22m uTd+l3io7YD6OH652Z0SKvXRflsByIAzAk3eEsmcogB7rYZPy6j9OL0ExzGW319LDl9L R/DyiKLx7aKbOgzOlMAmkcqvVFXKUPO7R1l5nCb9QhZ3+3F70clfklV2mR2N8EXMJles givaXJ/03UBUKTRUdnH9qooFu2WLOnm9TIewMQE4F38EJd2HxoATPBYk/lD5nnkDVi0R ReqS2dBlB62cR7bp913gFUZyXODhBC1545ndtZkIK2OuQ7tzP13S5BDOLRRHPf9q+Wrs kC6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PPFJJFGlz6LRNHc5NYzxKFNjJDNoIVP9JQBS0o4H3QE=; b=p6MhJ3AVTBmF1eOHLfPzjMw+L6BKI8i8Fa6+gcUXghJe5AtnftqJQGDmm2e5A+yJZC Ayy2l21QDtvRLDeTEJlvNb9xRylcw4WRdydqBi+rutaX/w4ssv7ccQSL3GShqX25D00m 0R01cSxRwYOH5iFQdPnFU654B2z3kbxq+nwDRXYvo+EBETVMPlpqlv53FqeHQZcRZcPG 261YNpY6Q8Fe+NpvjPF3uSV2RvTLvl8dQHZvDBWXwmuPdr4hy5aPianB822J/nR1I2bI 9Imb7t9fl+W56iakgpTciLBMnEa7HxzQxBBSNys4I5c/edYazAn2AaECOmGrJpRizuMI R0Gg== X-Gm-Message-State: AHPjjUi+G511n7QZPihgjqHRGW9XAoD8BMhzUxaS8RTITH7GhKJPRIuh 4BAA6H6lrcb1nPdNovg= X-Google-Smtp-Source: AOwi7QBnlrdV2dAjPJ5o6XU0B1ZZT9VKBl9Vuwn1QtXL8E3m1hY6XRJ/FKEnoE1O67FGru4a6K14rw== X-Received: by 10.84.211.36 with SMTP id b33mr24405445pli.47.1505764285554; Mon, 18 Sep 2017 12:51:25 -0700 (PDT) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 18 Sep 2017 12:50:44 -0700 Message-Id: <20170918195100.17593-2-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918195100.17593-1-andrew.smirnov@gmail.com> References: <20170918195100.17593-1-andrew.smirnov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH 01/17] imx_fec: Do not link to netdev X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , Jason Wang , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Binding to a particular netdev doesn't seem to belong to this layer and should probably be done as a part of board or SoC specific code. Convert all of the users of this IP block to use qdev_set_nic_properties() instead. Cc: Peter Maydell Cc: Jason Wang Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov Reviewed-by: Peter Maydell --- hw/arm/fsl-imx6.c | 1 + hw/net/imx_fec.c | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 26fd214004..2ed7146c52 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -385,6 +385,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **= errp) spi_table[i].irq)); } =20 + qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]); object_property_set_bool(OBJECT(&s->eth), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 90e6ee35ba..88b4b049d7 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -1171,8 +1171,6 @@ static void imx_eth_realize(DeviceState *dev, Error *= *errp) =20 qemu_macaddr_default_if_unset(&s->conf.macaddr); =20 - s->conf.peers.ncs[0] =3D nd_table[0].netdev; - s->nic =3D qemu_new_nic(&imx_eth_net_info, &s->conf, object_get_typename(OBJECT(dev)), DEVICE(dev)->id, s); --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505764422043108.23356520873278; Mon, 18 Sep 2017 12:53:42 -0700 (PDT) Received: from localhost ([::1]:38621 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du26t-0008Lm-4i for importer@patchew.org; Mon, 18 Sep 2017 15:53:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37280) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du24q-0006lF-UO for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1du24q-0006GU-63 for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:33 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:38190) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1du24m-0006EG-LT; Mon, 18 Sep 2017 15:51:28 -0400 Received: by mail-pg0-x242.google.com with SMTP id m30so769240pgn.5; Mon, 18 Sep 2017 12:51:27 -0700 (PDT) Received: from squirtle.westlake.spaceflightindustries.com ([173.226.206.194]) by smtp.gmail.com with ESMTPSA id d186sm200791pfd.117.2017.09.18.12.51.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Sep 2017 12:51:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fqyxREB/kyB4rLmYAfwHoD8/bcback+XMLXwJhswt3g=; b=XcViKd/ix2EM8U4XBY3NPtSSicRXCejfizUgbfEFhjK+53/fD609VCeuG5N5KQhNr2 HfXJ02Yaa9eUk8piYrgWX0i+FbDlTSi7/pAs65bO0gYWRhIL0XPZQW/2TBOe5GtUXjb5 +Dkei8H0j/hSgpplXky9ZWFZkxyF7FxXimBGwhUmrAPfUjJpvcqrZgGu3BRDrXOT4UQJ nZu4h/C47Hh7LSGHrjl7ZFBe9s4F98mE0FZe57IZA3Y3urvhUGtJO+OvIUKHvE0TV2Ms CD+K8Ei0MQmniSrLUIG0tXIgBLxmcQB78lVOK5RbV2mPmbqrijwAv1lTxObcR8g2Qzor YGoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fqyxREB/kyB4rLmYAfwHoD8/bcback+XMLXwJhswt3g=; b=a33+2n7ReqvK12YICxff9QmdGXWarJOJLM5EzRbm1JnyszFE4ogM/TmVxVYrfbFiC5 0rrqynC0rSkFMN+ZqsYoJmsk+YfgWs/VpKGWtwOlaV3S7MU/vVW6+QQDhbly2DfT3i16 lTO2Lapa+x4DJ8aaWBl94DuyPN4imVxFSnx3WWTR5Qt1ppzf43hDuSjeazumIk0A60BA r2tLhQEOqqyXbE245aLEX8dTq5Uw/3onQfqaGrquofLSNk5D9yGe4rYf9dNgyGEooL2Y YyqGMnYqApwtPTsYpGubpwTxIdBhcD0C6zWLDM4rssadrSXKwRojyBsjnujpX9m5WPWe 9EgQ== X-Gm-Message-State: AHPjjUgBSsV2Ym/N0u7Ml7lw3gn63oCbTkggMRemIj3A0hH1AUFHBluf Q5zjstUpPQSye40gN0s= X-Google-Smtp-Source: ADKCNb4qmc7gVXVS1qu693uWcLRpCSSs/4iax0kO7frxyEwN3OnGiEwviLwzCHQwb4bCnbgG99OquA== X-Received: by 10.84.129.193 with SMTP id b59mr36843429plb.147.1505764286313; Mon, 18 Sep 2017 12:51:26 -0700 (PDT) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 18 Sep 2017 12:50:45 -0700 Message-Id: <20170918195100.17593-3-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918195100.17593-1-andrew.smirnov@gmail.com> References: <20170918195100.17593-1-andrew.smirnov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH 02/17] imx_fec: Do not calculate FEC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , Jason Wang , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Save some computation time and avoid calculating CRC's frame Cc: Peter Maydell Cc: Jason Wang Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/net/imx_fec.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 88b4b049d7..75822344fc 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -1032,9 +1032,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, c= onst uint8_t *buf, IMXENETBufDesc bd; uint32_t flags =3D 0; uint32_t addr; - uint32_t crc; uint32_t buf_addr; - uint8_t *crc_ptr; unsigned int buf_len; size_t size =3D len; =20 @@ -1048,8 +1046,6 @@ static ssize_t imx_enet_receive(NetClientState *nc, c= onst uint8_t *buf, =20 /* 4 bytes for the CRC. */ size +=3D 4; - crc =3D cpu_to_be32(crc32(~0, buf, size)); - crc_ptr =3D (uint8_t *) &crc; =20 /* Huge frames are truncted. */ if (size > ENET_MAX_FRAME_SIZE) { @@ -1090,9 +1086,10 @@ static ssize_t imx_enet_receive(NetClientState *nc, = const uint8_t *buf, dma_memory_write(&address_space_memory, buf_addr, buf, buf_len); buf +=3D buf_len; if (size < 4) { + const uint8_t zeros[4] =3D { 0 }; + dma_memory_write(&address_space_memory, buf_addr + buf_len, - crc_ptr, 4 - size); - crc_ptr +=3D 4 - size; + zeros, 4 - size); } bd.flags &=3D ~ENET_BD_E; if (size =3D=3D 0) { --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 03/17] imx_fec: Refactor imx_eth_enable_rx() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , Jason Wang , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Refactor imx_eth_enable_rx() to have more meaningfull variable name than 'tmp' and to reduce number of logical negations done. Cc: Peter Maydell Cc: Jason Wang Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov Reviewed-by: Peter Maydell --- hw/net/imx_fec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 75822344fc..84085afe09 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -536,19 +536,19 @@ static void imx_eth_do_tx(IMXFECState *s) static void imx_eth_enable_rx(IMXFECState *s) { IMXFECBufDesc bd; - bool tmp; + bool rx_ring_full; =20 imx_fec_read_bd(&bd, s->rx_descriptor); =20 - tmp =3D ((bd.flags & ENET_BD_E) !=3D 0); + rx_ring_full =3D !(bd.flags & ENET_BD_E); =20 - if (!tmp) { + if (rx_ring_full) { FEC_PRINTF("RX buffer full\n"); } else if (!s->regs[ENET_RDAR]) { qemu_flush_queued_packets(qemu_get_queue(s->nic)); } =20 - s->regs[ENET_RDAR] =3D tmp ? ENET_RDAR_RDAR : 0; + s->regs[ENET_RDAR] =3D rx_ring_full ? 0 : ENET_RDAR_RDAR; } =20 static void imx_eth_reset(DeviceState *d) --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150576473722699.21442404582979; Mon, 18 Sep 2017 12:58:57 -0700 (PDT) Received: from localhost ([::1]:38654 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du2C0-0004dg-5b for importer@patchew.org; Mon, 18 Sep 2017 15:58:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37311) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du24r-0006lr-Hy for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1du24q-0006Gn-GX for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:33 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:38322) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1du24n-0006FC-Ni; Mon, 18 Sep 2017 15:51:29 -0400 Received: by mail-pf0-x242.google.com with SMTP id q76so589281pfq.5; Mon, 18 Sep 2017 12:51:29 -0700 (PDT) Received: from squirtle.westlake.spaceflightindustries.com ([173.226.206.194]) by smtp.gmail.com with ESMTPSA id d186sm200791pfd.117.2017.09.18.12.51.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Sep 2017 12:51:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rzYOxbYwJj+GD3IhY8nPvTyU1APl7Am2GgKyHUaZxR0=; b=W6iI7d0oIv6XqgMHmdsZzBumdw3nGzpaxkDGch2t+yPPPg2wxRKKE9fAKi798wpAq7 ghL1H0PX7akWAu0xOX/GhwEOZv5RnpqMVpgU5A338bv1L7H1eO5aAyiYuIfkhb9ynk8O Z38YYtDh5UzbgNkPEIuXSlZSTpMYKCC+bLmnwF3zFT6xTZGTUyyiOW7jAx5Ke8nDIuzg Vchbg12xPCRB6OUe6Qrej58fU8Yk4/ABJlezodr+uUMvZtlM8yYwBnXZm6A86o03mjSE fLM8E2veoUw7ic0lHNZVELHeRIqg5W6pmvxo4NyXN/4kIm6kqYjboeLQKhTGsGU7Odaw h/0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rzYOxbYwJj+GD3IhY8nPvTyU1APl7Am2GgKyHUaZxR0=; b=CnMU4yna4SgFJHx5MqMZ06mYD6d4QiCRLcRVEZlrNgL2JMAHmTNpLoUBDTyIW0Nv08 C3k++5KQkZIjbZbHTfQro8fcbKfw4g/gsQjrpTREdlIxFfURvASv3fkbzwEhZ1b56wQz Sl/je8e1e3rq+pxF67Eld9h2PfXjjZIf43nZbL8NGMbZrWvSe5fIHEJUtLEBshLIBjc/ B8rl0x+L1DAlS5YxtmV+kzkHx122ZPyimGeDYq1DnCyWfbAjsSn1z8IdsotlKadSNgBU E3bIMXO7jZhNqPlWkj5nuR0iotpFZgvJFW8nX//pOWKcKdMB2c0IQL6AmSO9coCDDJcg W/tQ== X-Gm-Message-State: AHPjjUg79QiXJXLwyeudOFvT5PVfT8xnAG+ZJqLXolbFe79PQJ1wBtxq gjq6DrLKmknk+Q/kKp4= X-Google-Smtp-Source: ADKCNb6wPrW/ShCNW8Pn3hcKtceQotREduEqqlVp+wXATyQ3NhUkdSgzQyz4Bz4Jc94/sueKSowv8A== X-Received: by 10.84.133.37 with SMTP id 34mr38289850plf.362.1505764288325; Mon, 18 Sep 2017 12:51:28 -0700 (PDT) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 18 Sep 2017 12:50:47 -0700 Message-Id: <20170918195100.17593-5-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918195100.17593-1-andrew.smirnov@gmail.com> References: <20170918195100.17593-1-andrew.smirnov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH 04/17] imx_fec: Change queue flushing heuristics X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , Jason Wang , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In current implementation, packet queue flushing logic seem to suffer from a deadlock like scenario if a packet is received by the interface before before Rx ring is initialized by Guest's driver. Consider the following sequence of events: 1. A QEMU instance is started against a TAP device on Linux host, running Linux guest, e. g., something to the effect of: qemu-system-arm \ -net nic,model=3Dimx.fec,netdev=3Dlan0 \ netdev tap,id=3Dlan0,ifname=3Dtap0,script=3Dno,downscript=3Dno \ ... rest of the arguments ... 2. Once QEMU starts, but before guest reaches the point where FEC deriver is done initializing the HW, Guest, via TAP interface, receives a number of multicast MDNS packets from Host (not necessarily true for every OS, but it happens at least on Fedora 25) 3. Recieving a packet in such a state results in imx_eth_can_receive() returning '0', which in turn causes tap_send() to disable corresponding event (tap.c:203) 4. Once Guest's driver reaches the point where it is ready to recieve packets it prepares Rx ring descriptors and writes ENET_RDAR_RDAR to ENET_RDAR register to indicate to HW that more descriptors are ready. And at this points emulation layer does this: s->regs[index] =3D ENET_RDAR_RDAR; imx_eth_enable_rx(s); which, combined with: if (!s->regs[ENET_RDAR]) { qemu_flush_queued_packets(qemu_get_queue(s->nic)); } results in Rx queue never being flushed and corresponding I/O event beign disabled. Change the code to remember the fact that can_receive callback was called before Rx ring was ready and use it to make a decision if receive queue needs to be flushed. Cc: Peter Maydell Cc: Jason Wang Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/net/imx_fec.c | 6 ++++-- include/hw/net/imx_fec.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 84085afe09..767402909d 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -544,8 +544,9 @@ static void imx_eth_enable_rx(IMXFECState *s) =20 if (rx_ring_full) { FEC_PRINTF("RX buffer full\n"); - } else if (!s->regs[ENET_RDAR]) { + } else if (s->needs_flush) { qemu_flush_queued_packets(qemu_get_queue(s->nic)); + s->needs_flush =3D false; } =20 s->regs[ENET_RDAR] =3D rx_ring_full ? 0 : ENET_RDAR_RDAR; @@ -930,7 +931,8 @@ static int imx_eth_can_receive(NetClientState *nc) =20 FEC_PRINTF("\n"); =20 - return s->regs[ENET_RDAR] ? 1 : 0; + s->needs_flush =3D !s->regs[ENET_RDAR]; + return !!s->regs[ENET_RDAR]; } =20 static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 62ad473b05..4bc8f03ec2 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -252,6 +252,7 @@ typedef struct IMXFECState { uint32_t phy_int_mask; =20 bool is_fec; + bool needs_flush; } IMXFECState; =20 #endif --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505764577126489.0557367894254; Mon, 18 Sep 2017 12:56:17 -0700 (PDT) Received: from localhost ([::1]:38638 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du29Q-0002GS-Dh for importer@patchew.org; Mon, 18 Sep 2017 15:56:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37315) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du24r-0006lx-L5 for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1du24q-0006H7-RM for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:33 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:33183) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1du24o-0006FP-Dg; Mon, 18 Sep 2017 15:51:30 -0400 Received: by mail-pg0-x242.google.com with SMTP id i130so781785pgc.0; Mon, 18 Sep 2017 12:51:30 -0700 (PDT) Received: from squirtle.westlake.spaceflightindustries.com ([173.226.206.194]) by smtp.gmail.com with ESMTPSA id d186sm200791pfd.117.2017.09.18.12.51.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Sep 2017 12:51:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ogk4glSLUUFcMz+YRhCxIE+lk8AJJwGYtZEpni0jNJI=; b=KRDEtcOhKRN9ZJNGtIfM2LVyCUaewoiO/QQ3C+Pu53/O35+1T/INqSqfwYkbYAMeO1 tP+MIqONxPC7575sheeemI1Iquv4zzHmtm7evgvT5UTpbs3sLFGp7CrlpsLLb1eghV2r ycCLqpWMrMmZhI0e2BEzPZ7UhfR2jrGpCruv3y58I9udRSu0P+kHniwg4SA+R+nJRSrG HcSlgD/SJLxhQJWEJtVN6djL7TsYiW0SZhPYGVtjDFefv1JokqRs0bwHBNKjXeEWytzx VIWXmhxERb3xGoAlWSpArND3ENxvU2ebjCyWF9L/kNVNRarW1rTFX0G97trxRMuM8POS qcYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ogk4glSLUUFcMz+YRhCxIE+lk8AJJwGYtZEpni0jNJI=; b=Go0aWpg06Bj32ZTvDAm/rK/mjuvtmOpccCZL/5OQXygR/OiZx2IaeSE8ufGSHJXEY4 n0DH0xNffMU9fzLYsk2gR6tHTiHoXgxo4sviBVWVGezZj9l4TT2NetBfnpEXXGBM1tLV +j2FkK+9urE4801jzrPPX7PLI5nPv3aFHsK7h3FE6iioFJngv+F0eONYbUYczaCl+iXV Re+rKZwbuLRZEYWZNmgP/PGNPbTXaC/pzgeoGKM0gGGmCJWHkLmepEGEpht8AXRrU/Rh mBUh7Yu8V2OxBoEtUwHPJFyoXIFIt9AkSPMTbwXzw7RVQNIvUfXIrTdIA0mRGZ2o3KKF j0JA== X-Gm-Message-State: AHPjjUhA+Ax2zs0/MsowsGMVnEZViI5qja17QO1MSb6edPyOmTbGxoLA fk0xyHDH7J5qc5ESgGQ= X-Google-Smtp-Source: AOwi7QBZWZ0wVgj6zmm688V+R954QQuXKWt58Jknd9kSWhTvuixBbt2YShOAik6gtVSB95fi6OM28g== X-Received: by 10.84.150.129 with SMTP id h1mr18981044plh.59.1505764289306; Mon, 18 Sep 2017 12:51:29 -0700 (PDT) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 18 Sep 2017 12:50:48 -0700 Message-Id: <20170918195100.17593-6-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918195100.17593-1-andrew.smirnov@gmail.com> References: <20170918195100.17593-1-andrew.smirnov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH 05/17] imx_fec: Use ENET_FTRL to determine truncation length X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , Jason Wang , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Frame truncation length, TRUNC_FL, is determined by the contents of ENET_FTRL register, so convert the code to use it instead of a hardcoded constant. Cc: Peter Maydell Cc: Jason Wang Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/net/imx_fec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 767402909d..989c11be5f 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -1050,8 +1050,8 @@ static ssize_t imx_enet_receive(NetClientState *nc, c= onst uint8_t *buf, size +=3D 4; =20 /* Huge frames are truncted. */ - if (size > ENET_MAX_FRAME_SIZE) { - size =3D ENET_MAX_FRAME_SIZE; + if (size > s->regs[ENET_FTRL]) { + size =3D s->regs[ENET_FTRL]; flags |=3D ENET_BD_TR | ENET_BD_LG; } =20 --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505764885566844.5190511867197; Mon, 18 Sep 2017 13:01:25 -0700 (PDT) Received: from localhost ([::1]:38671 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du2EO-0006qi-QY for importer@patchew.org; Mon, 18 Sep 2017 16:01:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37370) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du24t-0006ox-BP for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1du24s-0006IQ-LC for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:35 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:35297) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1du24q-0006G7-8H; Mon, 18 Sep 2017 15:51:32 -0400 Received: by mail-pf0-x242.google.com with SMTP id i23so595368pfi.2; Mon, 18 Sep 2017 12:51:32 -0700 (PDT) Received: from squirtle.westlake.spaceflightindustries.com ([173.226.206.194]) by smtp.gmail.com with ESMTPSA id d186sm200791pfd.117.2017.09.18.12.51.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Sep 2017 12:51:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BNk/XMXexa9eZG4ckigFUy60XK40Fo/MvaxQGV5lvgQ=; b=QvhgHHB8flbUfpapmkGLhLYiMeXuQ25iYA143oGavJCb3eZovhxdABdDGg6sgsiUZ3 /V7sRrZO6UO9M/dJ5t92RkEdcvslWJt7p/Awr07+cIVbW8qlJEvHsrXmR7Bz3moPmXPJ 2LUxODZbk1vpAo070mikblrl+2h+Xb66xoNUwYHK/nPjOl1siVPLCh3l857PKYghMbnB bksEh2CoIA5jqi7HXLkV4GU4uKyvTvi61PRFnpFDC02SPwhmJvXSCETGFomoNGkSdA4C Kp4/gJ2xdTrADHqCU9EKAXvT6CO+Vak8tBQtdAJU38dsYHxUwzD+rePsgUe9VHcvv4M0 oCzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BNk/XMXexa9eZG4ckigFUy60XK40Fo/MvaxQGV5lvgQ=; b=dIK2H42UrddseyAdfwxnKgwBuL95XFCGOKVr9HJNRrrlerTN9QLzakXDbPtSnY5TMh 3/IfiSvx64Dk79L4IAt/iD56UQW3cga9PRAijXJHIQ3dpTBsCNgoUPztbzRwDNGcZA2m PLRt65F2oCQ7R4VeLgNSxUOdOHzN4jQl/Bdntb4TCKrYxFGoN46/rkxPUDhanO8Prt// PA6wgi9cS4IHUZjoLMoC7pcZELNDiHqomTlOIUzhwzg0+EUaTC+AwJjU0ngpMflUkjzp Z8czHepy0v1T2UvIrjELzBFVfQJeLnTKJ63Q0BzzeK/mGQynx7NHcMvFapTBYkVySwK2 qhcA== X-Gm-Message-State: AHPjjUjcs/s/tZJ3AMMw+OOXp/iqbV3g7caP/jv1V1FfLK1Jj0hjUzX+ la+Xa2W2BTY4fuBkP/4= X-Google-Smtp-Source: AOwi7QAMng1NP353B/itu0CPRwDTFZErnf5F1S0bvXKcywbKS7WTmgd9r/CbBBdZ3qWTYL7YsNeUMw== X-Received: by 10.84.253.23 with SMTP id z23mr18994021pll.210.1505764291145; Mon, 18 Sep 2017 12:51:31 -0700 (PDT) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 18 Sep 2017 12:50:49 -0700 Message-Id: <20170918195100.17593-7-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918195100.17593-1-andrew.smirnov@gmail.com> References: <20170918195100.17593-1-andrew.smirnov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH 06/17] imx_fec: Use MIN instead of explicit ternary operator X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , Jason Wang , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Peter Maydell Cc: Jason Wang Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/imx_fec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 989c11be5f..8a77136d38 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -1074,7 +1074,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, c= onst uint8_t *buf, TYPE_IMX_FEC, __func__); break; } - buf_len =3D (size <=3D s->regs[ENET_MRBR]) ? size : s->regs[ENET_M= RBR]; + buf_len =3D MIN(size, s->regs[ENET_MRBR]); bd.length =3D buf_len; size -=3D buf_len; =20 --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505764610342341.36223242576625; Mon, 18 Sep 2017 12:56:50 -0700 (PDT) Received: from localhost ([::1]:38642 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du29x-0002jN-HX for importer@patchew.org; Mon, 18 Sep 2017 15:56:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37403) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du24u-0006pz-CU for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1du24t-0006Ir-DO for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:36 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:34992) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1du24r-0006Gs-1T; Mon, 18 Sep 2017 15:51:33 -0400 Received: by mail-pg0-x241.google.com with SMTP id j16so775197pga.2; Mon, 18 Sep 2017 12:51:32 -0700 (PDT) Received: from squirtle.westlake.spaceflightindustries.com ([173.226.206.194]) by smtp.gmail.com with ESMTPSA id d186sm200791pfd.117.2017.09.18.12.51.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Sep 2017 12:51:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gosmns9ewTlxveN5Eu1UJHKyNHtlDRa4EATGzSoL4Do=; b=Ak+/3gYS5Hi/JBHz/t2OZcadyj1fGAo1yHscBfyCu+TpbomGTu2wg7EVlanoixcYyc W9OzKggA1fHgQZR5QBp0ZoqvPJJN1MU9j1GsB9lF+wNQzyDvpTM9yvXVORpULLAUQIH+ gQGtOhVqFOzV2zEh33tW+ZQ5ZlG8BVFWC0KXBNstOSYtdOO+YB4yTHhM3cOP7l9saNUm bPWgelT1B3IQrIuT9nEMee7t7m4wE7jf+EzCrxVlL1N7fh6sp+7Q4y46HK63GCFL9Np1 kdZR+zL6HDPF5ZnbgU0jotfUGd1sTlWtnJQoBPUoehYyDO7JG3kg+dW2LjUau4/dNRSX nslQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gosmns9ewTlxveN5Eu1UJHKyNHtlDRa4EATGzSoL4Do=; b=q/nq7rJl+/qnBltduBbMdVWxryVSsggwPqfmCZ4AThnOzlcE8TbNxOxrs+NLrZ45iL 45B3/s/MdLwrO0K7j9Hw8YrjRKROP7p2RoZTjY9hvmqfeXLihFiudJrgWpKZPe/xtyKs 3z5q2ojPTbeE5INRv5EYak9oAKqivTaPkIS5xWgCLJlhyOvUQ+iLxSa4uvClNilPvUWO MfR+wOwFjrih7jzzG3vZtfk1cSGUCB06BanSsbAuSw5hSmgYeO/wlb2f4CsGefEplnSk XH4ZLcpHttxIge1JQFwW3Fa2/wJiYVfHK7EQsjMLYKOy0Z59Qf+ldIclbb1+58WDxW7/ zedQ== X-Gm-Message-State: AHPjjUggZLlgx0cOBfi+iyaw0IDk37zqs6MHVO62aV9tnq+OhzTBgZEH akTrp3iMgvJduYe1vk8= X-Google-Smtp-Source: ADKCNb5zgtJorYeSnDmcyNQoXvc0jzRlTJM3+lqwjno2BXj8kx7Lk9EJae4kuMnJrOglqGK1JYADIA== X-Received: by 10.84.129.193 with SMTP id b59mr36779462plb.88.1505764291848; Mon, 18 Sep 2017 12:51:31 -0700 (PDT) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 18 Sep 2017 12:50:50 -0700 Message-Id: <20170918195100.17593-8-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918195100.17593-1-andrew.smirnov@gmail.com> References: <20170918195100.17593-1-andrew.smirnov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH 07/17] imx_fec: Emulate SHIFT16 in ENETx_RACC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , Jason Wang , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Needed to support latest Linux kernel driver which relies on that functionality. Cc: Peter Maydell Cc: Jason Wang Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov Reviewed-by: Peter Maydell --- hw/net/imx_fec.c | 23 +++++++++++++++++++++++ include/hw/net/imx_fec.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 8a77136d38..bd62d7a75f 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -1037,6 +1037,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, c= onst uint8_t *buf, uint32_t buf_addr; unsigned int buf_len; size_t size =3D len; + bool shift16 =3D s->regs[ENET_RACC] & ENET_RACC_SHIFT16; =20 FEC_PRINTF("len %d\n", (int)size); =20 @@ -1049,6 +1050,10 @@ static ssize_t imx_enet_receive(NetClientState *nc, = const uint8_t *buf, /* 4 bytes for the CRC. */ size +=3D 4; =20 + if (shift16) { + size +=3D 2; + } + /* Huge frames are truncted. */ if (size > s->regs[ENET_FTRL]) { size =3D s->regs[ENET_FTRL]; @@ -1085,6 +1090,24 @@ static ssize_t imx_enet_receive(NetClientState *nc, = const uint8_t *buf, buf_len +=3D size - 4; } buf_addr =3D bd.data; + + if (shift16) { + /* + * If SHIFT16 bit of ENETx_RACC register is set we need to + * align the payload to 4-byte boundary. + */ + const uint8_t zeros[2] =3D { 0 }; + + dma_memory_write(&address_space_memory, buf_addr, + zeros, sizeof(zeros)); + + buf_addr +=3D sizeof(zeros); + buf_len -=3D sizeof(zeros); + + shift16 =3D false; /* We only do this once per Ethernet + * frame */ + } + dma_memory_write(&address_space_memory, buf_addr, buf, buf_len); buf +=3D buf_len; if (size < 4) { diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 4bc8f03ec2..20a6aa98b4 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -169,6 +169,8 @@ #define ENET_TWFR_TFWR_LENGTH (6) #define ENET_TWFR_STRFWD (1 << 8) =20 +#define ENET_RACC_SHIFT16 BIT(7) + /* Buffer Descriptor. */ typedef struct { uint16_t length; --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH 08/17] imx_fec: Add support for multiple Tx DMA rings X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , Jason Wang , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" More recent version of the IP block support more than one Tx DMA ring, so add the code implementing that feature. Cc: Peter Maydell Cc: Jason Wang Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/net/imx_fec.c | 97 +++++++++++++++++++++++++++++++++++++++-----= ---- include/hw/net/imx_fec.h | 23 +++++++++++- 2 files changed, 101 insertions(+), 19 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index bd62d7a75f..6045ffe673 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -196,6 +196,17 @@ static const char *imx_eth_reg_name(IMXFECState *s, ui= nt32_t index) } } =20 +static const VMStateDescription vmstate_imx_eth_tx_ring =3D { + .name =3D "fec-tx-ring", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(descriptor, IMXFECTxRing), + VMSTATE_UINT32(tdsr, IMXFECTxRing), + VMSTATE_END_OF_LIST() + }, +}; + static const VMStateDescription vmstate_imx_eth =3D { .name =3D TYPE_IMX_FEC, .version_id =3D 2, @@ -203,8 +214,10 @@ static const VMStateDescription vmstate_imx_eth =3D { .fields =3D (VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX), VMSTATE_UINT32(rx_descriptor, IMXFECState), - VMSTATE_UINT32(tx_descriptor, IMXFECState), - + VMSTATE_STRUCT_ARRAY(tx_ring, IMXFECState, + ENET_TX_RING_NUM, + 1, vmstate_imx_eth_tx_ring, + IMXFECTxRing), VMSTATE_UINT32(phy_status, IMXFECState), VMSTATE_UINT32(phy_control, IMXFECState), VMSTATE_UINT32(phy_advertise, IMXFECState), @@ -407,7 +420,7 @@ static void imx_fec_do_tx(IMXFECState *s) int frame_size =3D 0, descnt =3D 0; uint8_t frame[ENET_MAX_FRAME_SIZE]; uint8_t *ptr =3D frame; - uint32_t addr =3D s->tx_descriptor; + uint32_t addr =3D s->tx_ring[0].descriptor; =20 while (descnt++ < IMX_MAX_DESC) { IMXFECBufDesc bd; @@ -448,17 +461,38 @@ static void imx_fec_do_tx(IMXFECState *s) } } =20 - s->tx_descriptor =3D addr; + s->tx_ring[0].descriptor =3D addr; =20 imx_eth_update(s); } =20 -static void imx_enet_do_tx(IMXFECState *s) +static void imx_enet_do_tx(IMXFECState *s, uint32_t index) { int frame_size =3D 0, descnt =3D 0; uint8_t frame[ENET_MAX_FRAME_SIZE]; uint8_t *ptr =3D frame; - uint32_t addr =3D s->tx_descriptor; + IMXFECTxRing *ring; + uint32_t addr; + + switch (index) { + case ENET_TDAR: + ring =3D &s->tx_ring[0]; + break; + case ENET_TDAR1: + ring =3D &s->tx_ring[1]; + break; + case ENET_TDAR2: + ring =3D &s->tx_ring[2]; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bogus value for index %x\n", + __func__, index); + abort(); + break; + } + + addr =3D ring->descriptor; =20 while (descnt++ < IMX_MAX_DESC) { IMXENETBufDesc bd; @@ -502,32 +536,32 @@ static void imx_enet_do_tx(IMXFECState *s) ptr =3D frame; frame_size =3D 0; if (bd.option & ENET_BD_TX_INT) { - s->regs[ENET_EIR] |=3D ENET_INT_TXF; + s->regs[ENET_EIR] |=3D ring->int_txf; } } if (bd.option & ENET_BD_TX_INT) { - s->regs[ENET_EIR] |=3D ENET_INT_TXB; + s->regs[ENET_EIR] |=3D ring->int_txb; } bd.flags &=3D ~ENET_BD_R; /* Write back the modified descriptor. */ imx_enet_write_bd(&bd, addr); /* Advance to the next descriptor. */ if ((bd.flags & ENET_BD_W) !=3D 0) { - addr =3D s->regs[ENET_TDSR]; + addr =3D s->regs[ring->tdsr]; } else { addr +=3D sizeof(bd); } } =20 - s->tx_descriptor =3D addr; + ring->descriptor =3D addr; =20 imx_eth_update(s); } =20 -static void imx_eth_do_tx(IMXFECState *s) +static void imx_eth_do_tx(IMXFECState *s, uint32_t index) { if (!s->is_fec && (s->regs[ENET_ECR] & ENET_ECR_EN1588)) { - imx_enet_do_tx(s); + imx_enet_do_tx(s, index); } else { imx_fec_do_tx(s); } @@ -586,7 +620,22 @@ static void imx_eth_reset(DeviceState *d) } =20 s->rx_descriptor =3D 0; - s->tx_descriptor =3D 0; + + s->tx_ring[0].tdsr =3D ENET_TDSR; + s->tx_ring[1].tdsr =3D ENET_TDSR1; + s->tx_ring[2].tdsr =3D ENET_TDSR2; + + s->tx_ring[0].int_txf =3D ENET_INT_TXF; + s->tx_ring[1].int_txf =3D ENET_INT_TXF1; + s->tx_ring[2].int_txf =3D ENET_INT_TXF2; + + s->tx_ring[0].int_txb =3D ENET_INT_TXB; + s->tx_ring[1].int_txb =3D ENET_INT_TXB1; + s->tx_ring[2].int_txb =3D ENET_INT_TXB2; + + s->tx_ring[0].descriptor =3D 0; + s->tx_ring[1].descriptor =3D 0; + s->tx_ring[2].descriptor =3D 0; =20 /* We also reset the PHY */ phy_reset(s); @@ -814,10 +863,12 @@ static void imx_eth_write(void *opaque, hwaddr offset= , uint64_t value, s->regs[index] =3D 0; } break; + case ENET_TDAR1: /* FALLTHROUGH */ + case ENET_TDAR2: /* FALLTHROUGH */ case ENET_TDAR: if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { s->regs[index] =3D ENET_TDAR_TDAR; - imx_eth_do_tx(s); + imx_eth_do_tx(s, index); } s->regs[index] =3D 0; break; @@ -829,8 +880,12 @@ static void imx_eth_write(void *opaque, hwaddr offset,= uint64_t value, if ((s->regs[index] & ENET_ECR_ETHEREN) =3D=3D 0) { s->regs[ENET_RDAR] =3D 0; s->rx_descriptor =3D s->regs[ENET_RDSR]; - s->regs[ENET_TDAR] =3D 0; - s->tx_descriptor =3D s->regs[ENET_TDSR]; + s->regs[ENET_TDAR] =3D 0; + s->regs[ENET_TDAR1] =3D 0; + s->regs[ENET_TDAR2] =3D 0; + s->tx_ring[0].descriptor =3D s->regs[ENET_TDSR]; + s->tx_ring[1].descriptor =3D s->regs[ENET_TDSR1]; + s->tx_ring[2].descriptor =3D s->regs[ENET_TDSR2]; } break; case ENET_MMFR: @@ -908,7 +963,15 @@ static void imx_eth_write(void *opaque, hwaddr offset,= uint64_t value, } else { s->regs[index] =3D value & ~7; } - s->tx_descriptor =3D s->regs[index]; + s->tx_ring[0].descriptor =3D s->regs[index]; + break; + case ENET_TDSR1: + s->regs[index] =3D value & ~7; + s->tx_ring[1].descriptor =3D s->regs[index]; + break; + case ENET_TDSR2: + s->regs[index] =3D value & ~7; + s->tx_ring[2].descriptor =3D s->regs[index]; break; case ENET_MRBR: s->regs[index] =3D value & 0x00003ff0; diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 20a6aa98b4..40bd29771f 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -52,6 +52,8 @@ #define ENET_TFWR 81 #define ENET_FRBR 83 #define ENET_FRSR 84 +#define ENET_TDSR1 89 +#define ENET_TDSR2 92 #define ENET_RDSR 96 #define ENET_TDSR 97 #define ENET_MRBR 98 @@ -66,6 +68,8 @@ #define ENET_FTRL 108 #define ENET_TACC 112 #define ENET_RACC 113 +#define ENET_TDAR1 121 +#define ENET_TDAR2 123 #define ENET_MIIGSK_CFGR 192 #define ENET_MIIGSK_ENR 194 #define ENET_ATCR 256 @@ -106,13 +110,18 @@ #define ENET_INT_WAKEUP (1 << 17) #define ENET_INT_TS_AVAIL (1 << 16) #define ENET_INT_TS_TIMER (1 << 15) +#define ENET_INT_TXF2 (1 << 7) +#define ENET_INT_TXB2 (1 << 6) +#define ENET_INT_TXF1 (1 << 3) +#define ENET_INT_TXB1 (1 << 2) =20 #define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BAB= T | \ ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB= | \ ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII= | \ ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL= | \ ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKE= UP | \ - ENET_INT_TS_AVAIL) + ENET_INT_TS_AVAIL | ENET_INT_TXF1 | ENET_I= NT_TXB1 |\ + ENET_INT_TXF2 | ENET_INT_TXB2) =20 /* RDAR */ #define ENET_RDAR_RDAR (1 << 24) @@ -233,6 +242,15 @@ typedef struct { =20 #define ENET_BD_BDU (1 << 31) =20 +#define ENET_TX_RING_NUM 3 + +typedef struct IMXFECTxRing { + uint32_t descriptor; + uint32_t tdsr; + uint32_t int_txf; + uint32_t int_txb; +} IMXFECTxRing; + typedef struct IMXFECState { /*< private >*/ SysBusDevice parent_obj; @@ -245,7 +263,8 @@ typedef struct IMXFECState { =20 uint32_t regs[ENET_MAX]; uint32_t rx_descriptor; - uint32_t tx_descriptor; + + IMXFECTxRing tx_ring[ENET_TX_RING_NUM]; =20 uint32_t phy_status; uint32_t phy_control; --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505764421300249.79193179880838; Mon, 18 Sep 2017 12:53:41 -0700 (PDT) Received: from localhost ([::1]:38622 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du26u-0008NV-AK for importer@patchew.org; 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Mon, 18 Sep 2017 12:51:33 -0700 (PDT) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 18 Sep 2017 12:50:52 -0700 Message-Id: <20170918195100.17593-10-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918195100.17593-1-andrew.smirnov@gmail.com> References: <20170918195100.17593-1-andrew.smirnov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH 09/17] imx_fec: Use correct length for packet size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , Jason Wang , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use 'frame_size' instead of 'len' when calling qemu_send_packet(), failing to do so results in malformed packets send in case when that packed is fragmented into multiple DMA transactions. Cc: Peter Maydell Cc: Jason Wang Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov Reviewed-by: Peter Maydell --- hw/net/imx_fec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 6045ffe673..c45b9648d9 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -532,7 +532,7 @@ static void imx_enet_do_tx(IMXFECState *s, uint32_t ind= ex) } } /* Last buffer in frame. */ - qemu_send_packet(qemu_get_queue(s->nic), frame, len); + qemu_send_packet(qemu_get_queue(s->nic), frame, frame_size); ptr =3D frame; frame_size =3D 0; if (bd.option & ENET_BD_TX_INT) { --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505764609706935.7614156150668; Mon, 18 Sep 2017 12:56:49 -0700 (PDT) Received: from localhost ([::1]:38641 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du29w-0002jE-Ui for importer@patchew.org; Mon, 18 Sep 2017 15:56:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37544) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du250-00070D-EK for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1du24z-0006Na-5q for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:42 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:38193) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1du24t-0006Iw-UQ; Mon, 18 Sep 2017 15:51:36 -0400 Received: by mail-pg0-x242.google.com with SMTP id m30so769426pgn.5; Mon, 18 Sep 2017 12:51:35 -0700 (PDT) Received: from squirtle.westlake.spaceflightindustries.com ([173.226.206.194]) by smtp.gmail.com with ESMTPSA id d186sm200791pfd.117.2017.09.18.12.51.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Sep 2017 12:51:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1FZYThZcvEKwD8CQazehQwvfTizUwANxhisZI+lJUFc=; b=tqr68R1T6fZEojpzsKidmWyKgXgk2CEfBcGaJdFbOYNIotZTr2lyuwF7vw2rr/2wM6 1z0/WUfhggzPq6MBJkL72PExNYZ43XIPTFhxt9S+WtEeZsPmrWL51h29aZ6mi6aPbGhW k0PcD2+hGls+WDNta5YWsmciyRat72qrrzszAexsjcjW+FvRAts7FIvYnx5IbqZX8vSF 7JGF4jN4GxfTtzMW8Tw4OMJGQHOFh4mRgOWrXQck1rMqCy3wADDQaibBjceFBuCqIrp7 fZ5KzKdCssH24/UiEILAzgZKELo2P7pm54MXyr4gnZTkrKRO/C2oW4ym1z/Npf/x5HHf 0OpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1FZYThZcvEKwD8CQazehQwvfTizUwANxhisZI+lJUFc=; b=lgqXhMhGMXPhJiQHKhYn4XZo93bSwIwsw1Xdr8pz10LpFaDvkJk3wIeNrxw7ixNLI4 z3VSpijnuhkC44/f9CbLMVwSngXNh5dRiBKndLcGjbgV3HwEPZtkXx9jObGFwYcVTdfp vONv3ZXleGvyjohmV8Rcb/VzAuki5Rg/cNYPLd0/BqEs0ROXc43AKa3a/NXITaCcKwHk jT0/CF9GjISzQPxoV4UwSlLtHoiMK7OOsRO9DZbau52rd4gY432l05oybYfh+F3F62b0 YAFXKSQ5q1fcIi1XEjGFe/yKsCwZ4gNIaTwqJfTmQxm8Qv/6qfdpVOCBnQxHT82jyrLF K1Rg== X-Gm-Message-State: AHPjjUi5pZJ5swsLbEMWC5Etf8kiwAFPnuujDyazAFoBnVryQzjMVdED x5C7INgoBVxEhsPxLMk= X-Google-Smtp-Source: ADKCNb5PktKLumCB64gHHo+6o9FU8xZFFWeHbeidKX+0ewmHPj7Rgs+lqHD4bnCUgOIiX3oYk4okhw== X-Received: by 10.84.234.197 with SMTP id i5mr37544648plt.184.1505764294770; Mon, 18 Sep 2017 12:51:34 -0700 (PDT) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 18 Sep 2017 12:50:53 -0700 Message-Id: <20170918195100.17593-11-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918195100.17593-1-andrew.smirnov@gmail.com> References: <20170918195100.17593-1-andrew.smirnov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH 10/17] sdhci: Add i.MX specific subtype of SDHCI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" IP block found on several generations of i.MX family does not use vanilla SDHCI implementation and it comes with a number of quirks. Introduce i.MX SDHCI subtype of SDHCI block to add code necessary to support unmodified Linux guest driver. Cc: Peter Maydell Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/sd/sdhci-internal.h | 15 ++++++ hw/sd/sdhci.c | 123 +++++++++++++++++++++++++++++++++++++++++++++= +++- include/hw/sd/sdhci.h | 8 ++++ 3 files changed, 144 insertions(+), 2 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 161177cf39..7b9ed06c36 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -91,6 +91,8 @@ #define SDHC_CTRL_ADMA2_32 0x10 #define SDHC_CTRL_ADMA2_64 0x18 #define SDHC_DMA_TYPE(x) ((x) & SDHC_CTRL_DMA_CHECK_MASK) +#define SDHC_CTRL_4BITBUS 0x02 +#define SDHC_CTRL_8BITBUS 0x20 =20 /* R/W Power Control Register 0x0 */ #define SDHC_PWRCON 0x29 @@ -229,4 +231,17 @@ enum { =20 extern const VMStateDescription sdhci_vmstate; =20 + +#define ESDHC_MIX_CTRL 0x48 +#define ESDHC_VENDOR_SPEC 0xc0 +#define ESDHC_DLL_CTRL 0x60 + +#define ESDHC_TUNING_CTRL 0xcc +#define ESDHC_TUNE_CTRL_STATUS 0x68 +#define ESDHC_WTMK_LVL 0x44 + +#define ESDHC_CTRL_4BITBUS (0x1 << 1) +#define ESDHC_CTRL_8BITBUS (0x2 << 1) + + #endif diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 6d6a791ee9..73e7910ba9 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -265,7 +265,8 @@ static void sdhci_send_command(SDHCIState *s) } } =20 - if ((s->norintstsen & SDHC_NISEN_TRSCMP) && + if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && + (s->norintstsen & SDHC_NISEN_TRSCMP) && (s->cmdreg & SDHC_CMD_RESPONSE) =3D=3D SDHC_CMD_RSP_WITH_BUSY)= { s->norintsts |=3D SDHC_NIS_TRSCMP; } @@ -1191,6 +1192,8 @@ static void sdhci_initfn(SDHCIState *s) =20 s->insert_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_inser= tion_irq, s); s->transfer_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_tran= sfer, s); + + s->io_ops =3D &sdhci_mmio_ops; } =20 static void sdhci_uninitfn(SDHCIState *s) @@ -1347,7 +1350,7 @@ static void sdhci_sysbus_realize(DeviceState *dev, Er= ror ** errp) s->buf_maxsz =3D sdhci_get_fifolen(s); s->fifo_buffer =3D g_malloc0(s->buf_maxsz); sysbus_init_irq(sbd, &s->irq); - memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci= ", + memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", SDHC_REGISTERS_MAP_SIZE); sysbus_init_mmio(sbd, &s->iomem); } @@ -1386,11 +1389,127 @@ static const TypeInfo sdhci_bus_info =3D { .class_init =3D sdhci_bus_class_init, }; =20 +static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) +{ + SDHCIState *s =3D SYSBUS_SDHCI(opaque); + uint32_t ret; + uint16_t hostctl; + + switch (offset) { + default: + return sdhci_read(opaque, offset, size); + + case SDHC_HOSTCTL: + hostctl =3D SDHC_DMA_TYPE(s->hostctl) << 5; + + if (s->hostctl & SDHC_CTRL_8BITBUS) + hostctl |=3D ESDHC_CTRL_8BITBUS; + + if (s->hostctl & SDHC_CTRL_4BITBUS) + hostctl |=3D ESDHC_CTRL_4BITBUS; + + ret =3D hostctl | (s->blkgap << 16) | + (s->wakcon << 24); + + break; + + case ESDHC_DLL_CTRL: + case ESDHC_TUNE_CTRL_STATUS: + case 0x6c: + case ESDHC_TUNING_CTRL: + case ESDHC_VENDOR_SPEC: + case ESDHC_MIX_CTRL: + case ESDHC_WTMK_LVL: + ret =3D 0; + break; + } + + return ret; +} + +static void +usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) +{ + SDHCIState *s =3D SYSBUS_SDHCI(opaque); + uint8_t hostctl =3D 0; + uint32_t value =3D (uint32_t)val; + + switch (offset) { + case ESDHC_DLL_CTRL: + case ESDHC_TUNE_CTRL_STATUS: + case 0x6c: + case ESDHC_TUNING_CTRL: + case ESDHC_WTMK_LVL: + case ESDHC_VENDOR_SPEC: + break; + + case SDHC_HOSTCTL: + if (value & ESDHC_CTRL_8BITBUS) + hostctl |=3D SDHC_CTRL_8BITBUS; + + if (value & ESDHC_CTRL_4BITBUS) + hostctl |=3D ESDHC_CTRL_4BITBUS; + + hostctl |=3D SDHC_DMA_TYPE(value >> 5); + + value &=3D ~0xFE; + value |=3D hostctl; + value &=3D ~0xFF00; + value |=3D s->pwrcon; + + sdhci_write(opaque, offset, value, size); + break; + + case ESDHC_MIX_CTRL: + /* + * The layout of the register is slightly different, but we + * don't care about those bits + */ + s->trnmod =3D value & 0xFFFF; + break; + case SDHC_TRNMOD: + sdhci_write(opaque, offset, val | s->trnmod, size); + break; + case SDHC_BLKSIZE: + val |=3D 0x7 << 12; + default: /* FALLTHROUGH */ + sdhci_write(opaque, offset, val, size); + break; + } +} + + +static const MemoryRegionOps usdhc_mmio_ops =3D { + .read =3D usdhc_read, + .write =3D usdhc_write, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + .unaligned =3D false + }, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void imx_usdhc_init(Object *obj) +{ + SDHCIState *s =3D SYSBUS_SDHCI(obj); + + s->io_ops =3D &usdhc_mmio_ops; + s->quirks =3D SDHCI_QUIRK_NO_BUSY_IRQ; +} + +static const TypeInfo imx_usdhc_info =3D { + .name =3D TYPE_IMX_USDHC, + .parent =3D TYPE_SYSBUS_SDHCI, + .instance_init =3D imx_usdhc_init, +}; + static void sdhci_register_types(void) { type_register_static(&sdhci_pci_info); type_register_static(&sdhci_sysbus_info); type_register_static(&sdhci_bus_info); + type_register_static(&imx_usdhc_info); } =20 type_init(sdhci_register_types) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 0f0c3f1e64..903472c901 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -39,6 +39,7 @@ typedef struct SDHCIState { }; SDBus sdbus; MemoryRegion iomem; + const MemoryRegionOps *io_ops; =20 QEMUTimer *insert_timer; /* timer for 'changing' sd card. */ QEMUTimer *transfer_timer; @@ -83,8 +84,13 @@ typedef struct SDHCIState { /* Force Event Auto CMD12 Error Interrupt Reg - write only */ /* Force Event Error Interrupt Register- write only */ /* RO Host Controller Version Register always reads as 0x2401 */ + + unsigned long quirks; } SDHCIState; =20 +/* Controller does not provide transfer-complete interrupt when not busy */ +#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) + #define TYPE_PCI_SDHCI "sdhci-pci" #define PCI_SDHCI(obj) OBJECT_CHECK(SDHCIState, (obj), TYPE_PCI_SDHCI) =20 @@ -92,4 +98,6 @@ typedef struct SDHCIState { #define SYSBUS_SDHCI(obj) \ OBJECT_CHECK(SDHCIState, (obj), TYPE_SYSBUS_SDHCI) =20 +#define TYPE_IMX_USDHC "imx-usdhc" + #endif /* SDHCI_H */ --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH 11/17] sdhci: Implement write method of ACMD12ERRSTS register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Peter Maydell Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/sd/sdhci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 73e7910ba9..9249471957 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1139,6 +1139,9 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val= , unsigned size) s->admasysaddr =3D (s->admasysaddr & (0x00000000FFFFFFFFULL | ((uint64_t)mask << 32))) | ((uint64_t)value << 32); break; + case SDHC_ACMD12ERRSTS: + MASKED_WRITE(s->acmd12errsts, mask, value); + break; case SDHC_FEAER: s->acmd12errsts |=3D value; s->errintsts |=3D (value >> 16) & s->errintstsen; --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505765274395139.44324287243; Mon, 18 Sep 2017 13:07:54 -0700 (PDT) Received: from localhost ([::1]:38707 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du2Kf-0003Vu-JM for importer@patchew.org; Mon, 18 Sep 2017 16:07:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37560) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du251-00070z-00 for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1du24z-0006Nh-AL for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:43 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34993) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1du24v-0006K6-Qe; Mon, 18 Sep 2017 15:51:37 -0400 Received: by mail-pg0-x244.google.com with SMTP id j16so775300pga.2; Mon, 18 Sep 2017 12:51:37 -0700 (PDT) Received: from squirtle.westlake.spaceflightindustries.com ([173.226.206.194]) by smtp.gmail.com with ESMTPSA id d186sm200791pfd.117.2017.09.18.12.51.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Sep 2017 12:51:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rNTOyGdpqrp69xWDEXneM3b6FC7W3sCUr5/OAM9bt5w=; b=MB6wIWyec9YzaGm66O4ZIXnhb6rdC6vsSG8tetUh3dtqlI2KKf2zlDE2ZkgWPGsB37 Y1I8jzHbhD8KWRHDCXH5OZh17e8NudnU0FgwHGd4+ZpKLNzJyNw6eiyCE6lZ9WDKMH8n zIZgMBHgu8SuuBhEHdv+UuOUiZLqGHy8t/L0aTykON5bTPuZJ0pYx7/mWj+7qJ3TqB4P HIrg5IJ4iq0+TqvKSTd9HVjc2TJONpQoHGLYYU87K2l39nCj4gjLLBMr066XYh+WDPn0 K4x7q4LB5HqUknoEo9pqNUpZg4knHhDp6JaSKuiMsV8tbit9YUuUduhoBrEIDZlJj0FL 614Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rNTOyGdpqrp69xWDEXneM3b6FC7W3sCUr5/OAM9bt5w=; b=fBn4sayhQdAIfWEvx9rgjzZ/7S4XgAV9xnS7cGx6xGvqRj5RviB6DXPw+Ap2q8mIO+ cLSjhVWe+9jiNiKOtqmKg8sWs9uyoipboe0QJasp8v7BbmGUooKBFizNH4wgp0qt8I1U +luPqflzh38nWEy9Wn30z17IdrDR5azIGXLSm0nbOP9Gk7EC/aUBmNlC3IjdqWU28zhM rsfTJRQFkYdbe7826xcZoSxGQVt82nfnCksgMV0ur0kiDA0iCyiKrwy+hW3vyvPzcNXH 3h3gUmrrdW4YR5wLwbfpBJPPwA2eN6klTEFtTdJmBEzbFYNmuFRM+O0QIwGzbnk03Gj1 44fQ== X-Gm-Message-State: AHPjjUhq5mkZL3kv6NnztvtBUAehzrQnbNXzyr7eUH+KoBqQCxD6vjt9 1yAaURg+mzIvJs6ByDc= X-Google-Smtp-Source: ADKCNb50nJG30hganSkCBTk70wfbySr+rDyPxy6sDC+aB3NwrLM9+VwWEfQOTNn87BlMV4R7Tp/R8A== X-Received: by 10.84.252.130 with SMTP id y2mr35757465pll.68.1505764296589; Mon, 18 Sep 2017 12:51:36 -0700 (PDT) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 18 Sep 2017 12:50:55 -0700 Message-Id: <20170918195100.17593-13-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918195100.17593-1-andrew.smirnov@gmail.com> References: <20170918195100.17593-1-andrew.smirnov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 12/17] i.MX: Add i.MX7 CCM, PMU and ANALOG device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Peter Maydell Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/misc/Makefile.objs | 1 + hw/misc/imx7_ccm.c | 201 +++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/misc/imx7_ccm.h | 76 +++++++++++++++++ 3 files changed, 278 insertions(+) create mode 100644 hw/misc/imx7_ccm.c create mode 100644 include/hw/misc/imx7_ccm.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 29fb922cef..ac1be05a03 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -34,6 +34,7 @@ obj-$(CONFIG_IMX) +=3D imx31_ccm.o obj-$(CONFIG_IMX) +=3D imx25_ccm.o obj-$(CONFIG_IMX) +=3D imx6_ccm.o obj-$(CONFIG_IMX) +=3D imx6_src.o +obj-$(CONFIG_IMX) +=3D imx7_ccm.o obj-$(CONFIG_MILKYMIST) +=3D milkymist-hpdmc.o obj-$(CONFIG_MILKYMIST) +=3D milkymist-pfpu.o obj-$(CONFIG_MAINSTONE) +=3D mst_fpga.o diff --git a/hw/misc/imx7_ccm.c b/hw/misc/imx7_ccm.c new file mode 100644 index 0000000000..418aafe7cc --- /dev/null +++ b/hw/misc/imx7_ccm.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX7 CCM, PMU and ANALOG IP blocks emulation code + * + * Author: Andrey Smirnov + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/sizes.h" +#include "hw/misc/imx7_ccm.h" +#include "qemu/log.h" + +static uint32_t imx7_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk cloc= k) +{ + /* + * This function is "consumed" by GPT emulation code, however on + * i.MX7 each GPT block can have their own clock root. This means + * that this functions needs somehow to know requester's identity + * and the way to pass it: be it via additional IMXClk constants + * or by adding another argument to this method needs to be + * figured out + */ + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Not implemented\n", + TYPE_IMX7_CCM, __func__); + return 0; +} + +static void imx7_ccm_reset(DeviceState *dev) +{ + IMX7CCMState *s =3D IMX7_CCM(dev); + + s->analog[CCM_ANALOG_PLL_ARM] =3D 0x00002042; + s->analog[CCM_ANALOG_PLL_DDR] =3D 0x0060302c; + s->analog[CCM_ANALOG_PLL_DDR_SS] =3D 0x00000000; + s->analog[CCM_ANALOG_PLL_DDR_NUM] =3D 0x06aaac4d; + s->analog[CCM_ANALOG_PLL_DDR_DENOM] =3D 0x100003ec; + s->analog[CCM_ANALOG_PLL_480] =3D 0x00002000; =20 + s->analog[CCM_ANALOG_PLL_480A] =3D 0x52605a56; + s->analog[CCM_ANALOG_PLL_480B] =3D 0x52525216; + s->analog[CCM_ANALOG_PLL_ENET] =3D 0x00001fc0; + s->analog[CCM_ANALOG_PLL_AUDIO] =3D 0x0001301b; + s->analog[CCM_ANALOG_PLL_AUDIO_SS] =3D 0x00000000; + s->analog[CCM_ANALOG_PLL_AUDIO_NUM] =3D 0x05f5e100; + s->analog[CCM_ANALOG_PLL_AUDIO_DENOM] =3D 0x2964619c; + s->analog[CCM_ANALOG_PLL_VIDEO] =3D 0x0008201b; + s->analog[CCM_ANALOG_PLL_VIDEO_SS] =3D 0x00000000; + s->analog[CCM_ANALOG_PLL_VIDEO_NUM] =3D 0x0000f699; + s->analog[CCM_ANALOG_PLL_VIDEO_DENOM] =3D 0x000f4240; + s->analog[CCM_ANALOG_PLL_MISC0] =3D 0x00000000; + + /* all PLLs need to be locked */ + s->analog[CCM_ANALOG_PLL_ARM] |=3D CCM_ANALOG_PLL_LOCK; + s->analog[CCM_ANALOG_PLL_DDR] |=3D CCM_ANALOG_PLL_LOCK; + s->analog[CCM_ANALOG_PLL_480] |=3D CCM_ANALOG_PLL_LOCK; + s->analog[CCM_ANALOG_PLL_480A] |=3D CCM_ANALOG_PLL_LOCK; + s->analog[CCM_ANALOG_PLL_480B] |=3D CCM_ANALOG_PLL_LOCK; + s->analog[CCM_ANALOG_PLL_ENET] |=3D CCM_ANALOG_PLL_LOCK; + s->analog[CCM_ANALOG_PLL_AUDIO] |=3D CCM_ANALOG_PLL_LOCK; + s->analog[CCM_ANALOG_PLL_VIDEO] |=3D CCM_ANALOG_PLL_LOCK; + s->analog[CCM_ANALOG_PLL_MISC0] |=3D CCM_ANALOG_PLL_LOCK; +} + +#define CCM_INDEX(offset) (((offset) & ~(hwaddr)0xF) / sizeof(uint32_t)) +#define CCM_BITOP(offset) ((offset) & (hwaddr)0xF) + +enum { + CCM_BITOP_NONE =3D 0x00, + CCM_BITOP_SET =3D 0x04, + CCM_BITOP_CLR =3D 0x08, + CCM_BITOP_TOG =3D 0x0C, +}; + +static uint64_t imx7_set_clr_tog_read(void *opaque, hwaddr offset, + unsigned size) +{ + const uint32_t *mmio =3D opaque; + + return (uint64_t)mmio[CCM_INDEX(offset)]; +} + +static void imx7_set_clr_tog_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + const uint8_t bitop =3D CCM_BITOP(offset); + const uint32_t index =3D CCM_INDEX(offset); + uint32_t *mmio =3D opaque; + + switch (bitop) { + case CCM_BITOP_NONE: + mmio[index] =3D value; + break; + case CCM_BITOP_SET: + mmio[index] |=3D value; + break; + case CCM_BITOP_CLR: + mmio[index] &=3D ~value; + break; + case CCM_BITOP_TOG: + mmio[index] ^=3D value; + break; + }; +} + +static const struct MemoryRegionOps imx7_set_clr_tog_ops =3D { + .read =3D imx7_set_clr_tog_read, + .write =3D imx7_set_clr_tog_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + /* + * Our device would not work correctly if the guest was doing + * unaligned access. This might not be a limitation on the real + * device but in practice there is no reason for a guest to access + * this device unaligned. + */ + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void imx7_ccm_init(Object *obj) +{ + SysBusDevice *sd =3D SYS_BUS_DEVICE(obj); + IMX7CCMState *s =3D IMX7_CCM(obj); + + memory_region_init(&s->mmio.container, obj, TYPE_IMX7_CCM, + 0x30000); + + memory_region_init_io(&s->mmio.analog, + obj, + &imx7_set_clr_tog_ops, + s->analog, + TYPE_IMX7_CCM ".analog", + sizeof(s->analog)); + + memory_region_add_subregion(&s->mmio.container, + 0x60, &s->mmio.analog); + + memory_region_init_io(&s->mmio.pmu, + obj, + &imx7_set_clr_tog_ops, + s->pmu, + TYPE_IMX7_CCM ".pmu", + sizeof(s->pmu)); + + memory_region_add_subregion(&s->mmio.container, + 0x200, &s->mmio.pmu); + =20 + memory_region_init_io(&s->mmio.ccm, + obj, + &imx7_set_clr_tog_ops, + s->ccm, + TYPE_IMX7_CCM ".ccm", + sizeof(s->ccm)); + + memory_region_add_subregion(&s->mmio.container, + 0x20000, &s->mmio.ccm); + + sysbus_init_mmio(sd, &s->mmio.container); +} + +static const VMStateDescription vmstate_imx7_ccm =3D { + .name =3D TYPE_IMX7_CCM, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(ccm, IMX7CCMState, CCM_MAX), + VMSTATE_UINT32_ARRAY(analog, IMX7CCMState, CCM_ANALOG_MAX), + VMSTATE_END_OF_LIST() + }, +}; + +static void imx7_ccm_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + IMXCCMClass *ccm =3D IMX_CCM_CLASS(klass); + + dc->reset =3D imx7_ccm_reset; + dc->vmsd =3D &vmstate_imx7_ccm; + dc->desc =3D "i.MX7 Clock Control Module"; + + ccm->get_clock_frequency =3D imx7_ccm_get_clock_frequency; +} + +static const TypeInfo imx7_ccm_info =3D { + .name =3D TYPE_IMX7_CCM, + .parent =3D TYPE_IMX_CCM, + .instance_size =3D sizeof(IMX7CCMState), + .instance_init =3D imx7_ccm_init, + .class_init =3D imx7_ccm_class_init, +}; + +static void imx7_ccm_register_type(void) +{ + type_register_static(&imx7_ccm_info); +} +type_init(imx7_ccm_register_type) diff --git a/include/hw/misc/imx7_ccm.h b/include/hw/misc/imx7_ccm.h new file mode 100644 index 0000000000..72ca10a04a --- /dev/null +++ b/include/hw/misc/imx7_ccm.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX7 CCM, PMU and ANALOG IP blocks emulation code + * + * Author: Andrey Smirnov + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef IMX7_CCM_H +#define IMX7_CCM_H + +#include "hw/misc/imx_ccm.h" +#include "qemu/bitops.h" + +#define REG_SET_CLR_TOG(name) name, name##_SET, name##_CLR, name##_TOG + +enum IMX7AnalogRegisters { + REG_SET_CLR_TOG(CCM_ANALOG_PLL_ARM), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_DDR), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_DDR_SS), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_DDR_NUM), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_DDR_DENOM), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_480), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_480A), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_480B), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_ENET), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_AUDIO), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_AUDIO_SS), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_AUDIO_NUM), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_AUDIO_DENOM), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_VIDEO), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_VIDEO_SS), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_VIDEO_NUM), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_VIDEO_DENOM), + REG_SET_CLR_TOG(CCM_ANALOG_PLL_MISC0), + + CCM_ANALOG_MAX, + + CCM_ANALOG_PLL_LOCK =3D BIT(31) +}; + +enum IMX7CCMRegisters { + CCM_MAX =3D 0xBC80 / sizeof(uint32_t), +}; + +enum IMX7PMURegisters { + PMU_MAX =3D 0x140 / sizeof(uint32_t), +}; + +#undef REG_SET_CLR_TOG + +#define TYPE_IMX7_CCM "imx7.ccm" +#define IMX7_CCM(obj) OBJECT_CHECK(IMX7CCMState, (obj), TYPE_IMX7_CCM) + +typedef struct IMX6CCMState { + /* */ + IMXCCMState parent_obj; + + /* */ + struct { + MemoryRegion container; + MemoryRegion ccm; + MemoryRegion pmu; + MemoryRegion analog; + } mmio; + + uint32_t ccm[CCM_MAX]; + uint32_t pmu[PMU_MAX]; + uint32_t analog[CCM_ANALOG_MAX]; + +} IMX7CCMState; + +#endif /* IMX7_CCM_H */ --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505765195841201.91153567895708; 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Mon, 18 Sep 2017 12:51:37 -0700 (PDT) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 18 Sep 2017 12:50:56 -0700 Message-Id: <20170918195100.17593-14-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918195100.17593-1-andrew.smirnov@gmail.com> References: <20170918195100.17593-1-andrew.smirnov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH 13/17] i.MX: Add code to emulate i.MX2 watchdog IP block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add enough code to emulate i.MX2 watchdog IP block so it would be possible to reboot the machine running Linux Guest. Cc: Peter Maydell Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/misc/Makefile.objs | 1 + hw/misc/imx2_wdt.c | 117 +++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/misc/imx2_wdt.h | 36 ++++++++++++++ 3 files changed, 154 insertions(+) create mode 100644 hw/misc/imx2_wdt.c create mode 100644 include/hw/misc/imx2_wdt.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index ac1be05a03..c393a93456 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -35,6 +35,7 @@ obj-$(CONFIG_IMX) +=3D imx25_ccm.o obj-$(CONFIG_IMX) +=3D imx6_ccm.o obj-$(CONFIG_IMX) +=3D imx6_src.o obj-$(CONFIG_IMX) +=3D imx7_ccm.o +obj-$(CONFIG_IMX) +=3D imx2_wdt.o obj-$(CONFIG_MILKYMIST) +=3D milkymist-hpdmc.o obj-$(CONFIG_MILKYMIST) +=3D milkymist-pfpu.o obj-$(CONFIG_MAINSTONE) +=3D mst_fpga.o diff --git a/hw/misc/imx2_wdt.c b/hw/misc/imx2_wdt.c new file mode 100644 index 0000000000..9d97a19511 --- /dev/null +++ b/hw/misc/imx2_wdt.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX2 Watchdog IP block + * + * Author: Andrey Smirnov + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/hw.h" +#include "exec/memory.h" +#include "exec/address-spaces.h" +#include "hw/sysbus.h" +#include "qemu/log.h" +#include "qemu/timer.h" +#include "sysemu/sysemu.h" +#include "sysemu/watchdog.h" +#include "qemu/error-report.h" +#include "qemu/sizes.h" + +#include "hw/misc/imx2_wdt.h" + + +#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */ +#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */ + +static uint64_t imx2_wdt_read(void *opaque, hwaddr addr, + unsigned int size) +{ + IMX2WdtState *s =3D opaque; + const size_t index =3D addr / sizeof(s->reg[0]); + + if (index < ARRAY_SIZE(s->reg)) + return s->reg[index]; + else + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + + return 0xDEADBEEF; +} + +static void imx2_wdt_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + uint16_t value =3D val64; + IMX2WdtState *s =3D opaque; + const size_t index =3D addr / sizeof(s->reg[0]); + + switch (index) { + case IMX2_WDT_WCR: + if (value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS)) + watchdog_perform_action(); + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + } +} + +static const MemoryRegionOps imx2_wdt_ops =3D { + .read =3D imx2_wdt_read, + .write =3D imx2_wdt_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + /* + * Our device would not work correctly if the guest was doing + * unaligned access. This might not be a limitation on the real + * device but in practice there is no reason for a guest to access + * this device unaligned. + */ + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void imx2_wdt_realize(DeviceState *dev, Error **errp) +{ + IMX2WdtState *s =3D IMX2_WDT(dev); + + memory_region_init_io(&s->mmio, OBJECT(dev), + &imx2_wdt_ops, s, + TYPE_IMX2_WDT".mmio", SZ_64K); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); +} + +static void imx2_wdt_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D imx2_wdt_realize; + + set_bit(DEVICE_CATEGORY_MISC, dc->categories); +} + +static const TypeInfo imx2_wdt_info =3D { + .name =3D TYPE_IMX2_WDT, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IMX2WdtState), + .class_init =3D imx2_wdt_class_init, +}; + +static WatchdogTimerModel model =3D { + .wdt_name =3D "imx2-watchdog", + .wdt_description =3D "i.MX2 Watchdog", +}; + +static void imx2_wdt_register_type(void) +{ + watchdog_add_model(&model); + type_register_static(&imx2_wdt_info); +} +type_init(imx2_wdt_register_type) diff --git a/include/hw/misc/imx2_wdt.h b/include/hw/misc/imx2_wdt.h new file mode 100644 index 0000000000..3a30ed1ef8 --- /dev/null +++ b/include/hw/misc/imx2_wdt.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX2 Watchdog IP block + * + * Author: Andrey Smirnov + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef IMX2_WDT_H +#define IMX2_WDT_H + +#include "qemu/bitops.h" +#include "hw/sysbus.h" + +#define TYPE_IMX2_WDT "imx2.wdt" +#define IMX2_WDT(obj) OBJECT_CHECK(IMX2WdtState, (obj), TYPE_IMX2_WDT) + +enum IMX2WdtRegisters { + IMX2_WDT_WCR, + IMX2_WDT_REG_NUM +}; + + +typedef struct IMX2WdtState { + /* */ + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint16_t reg[IMX2_WDT_REG_NUM]; +} IMX2WdtState; + +#endif /* IMX7_SNVS_H */ --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 14/17] i.MX7: Add code to emulate SNVS IP-block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add code to emulate SNVS IP-block. Currently only the bits needed to be able to emulate machine shutdown are implemented. Cc: Peter Maydell Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/misc/Makefile.objs | 1 + hw/misc/imx7_snvs.c | 84 +++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/misc/imx7_snvs.h | 35 +++++++++++++++++++ 3 files changed, 120 insertions(+) create mode 100644 hw/misc/imx7_snvs.c create mode 100644 include/hw/misc/imx7_snvs.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index c393a93456..16cee88e0f 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -36,6 +36,7 @@ obj-$(CONFIG_IMX) +=3D imx6_ccm.o obj-$(CONFIG_IMX) +=3D imx6_src.o obj-$(CONFIG_IMX) +=3D imx7_ccm.o obj-$(CONFIG_IMX) +=3D imx2_wdt.o +obj-$(CONFIG_IMX) +=3D imx7_snvs.o obj-$(CONFIG_MILKYMIST) +=3D milkymist-hpdmc.o obj-$(CONFIG_MILKYMIST) +=3D milkymist-pfpu.o obj-$(CONFIG_MAINSTONE) +=3D mst_fpga.o diff --git a/hw/misc/imx7_snvs.c b/hw/misc/imx7_snvs.c new file mode 100644 index 0000000000..efce0a760f --- /dev/null +++ b/hw/misc/imx7_snvs.c @@ -0,0 +1,84 @@ +/* + * IMX7 Secure Non-Volatile Storage + * + * Copyright (c) 2017, Impinj, Inc. + * + * Author: Andrey Smirnov + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + * Bare minimum emulation code needed to support being able to shut + * down linux guest gracefully. + */ + +#include "qemu/osdep.h" +#include "qemu/sizes.h" +#include "hw/misc/imx7_snvs.h" +#include "qemu/log.h" +#include "sysemu/sysemu.h" + +static uint64_t imx7_snvs_read(void *opaque, hwaddr offset, unsigned size) +{ + return 0; +} + +static void imx7_snvs_write(void *opaque, hwaddr offset, + uint64_t v, unsigned size) +{ + const uint32_t value =3D v; + const uint32_t mask =3D SNVS_LPCR_TOP | SNVS_LPCR_DP_EN; + + if (offset =3D=3D SNVS_LPCR && ((value & mask) =3D=3D mask)) { + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } +} + +static const struct MemoryRegionOps imx7_snvs_ops =3D { + .read =3D imx7_snvs_read, + .write =3D imx7_snvs_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid =3D { + /* + * Our device would not work correctly if the guest was doing + * unaligned access. This might not be a limitation on the real + * device but in practice there is no reason for a guest to access + * this device unaligned. + */ + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void imx7_snvs_init(Object *obj) +{ + SysBusDevice *sd =3D SYS_BUS_DEVICE(obj); + IMX7SNVSState *s =3D IMX7_SNVS(obj); + + memory_region_init_io(&s->mmio, obj, &imx7_snvs_ops, s, + TYPE_IMX7_SNVS, 0x1000); + + sysbus_init_mmio(sd, &s->mmio); +} + +static void imx7_snvs_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "i.MX7 Secure Non-Volatile Storage Module"; +} + +static const TypeInfo imx7_snvs_info =3D { + .name =3D TYPE_IMX7_SNVS, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IMX7SNVSState), + .instance_init =3D imx7_snvs_init, + .class_init =3D imx7_snvs_class_init, +}; + +static void imx7_snvs_register_type(void) +{ + type_register_static(&imx7_snvs_info); +} +type_init(imx7_snvs_register_type) diff --git a/include/hw/misc/imx7_snvs.h b/include/hw/misc/imx7_snvs.h new file mode 100644 index 0000000000..255f8f26f9 --- /dev/null +++ b/include/hw/misc/imx7_snvs.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX7 SNVS block emulation code + * + * Author: Andrey Smirnov + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef IMX7_SNVS_H +#define IMX7_SNVS_H + +#include "qemu/bitops.h" +#include "hw/sysbus.h" + + +enum IMX7SNVSRegisters { + SNVS_LPCR =3D 0x38, + SNVS_LPCR_TOP =3D BIT(6), + SNVS_LPCR_DP_EN =3D BIT(5) +}; + +#define TYPE_IMX7_SNVS "imx7.snvs" +#define IMX7_SNVS(obj) OBJECT_CHECK(IMX7SNVSState, (obj), TYPE_IMX7_SNVS) + +typedef struct IMX7SNVSState { + /* */ + SysBusDevice parent_obj; + + MemoryRegion mmio; +} IMX7SNVSState; + +#endif /* IMX7_SNVS_H */ --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505765029251107.45803821098889; Mon, 18 Sep 2017 13:03:49 -0700 (PDT) Received: from localhost ([::1]:38684 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du2Gi-0000Ok-EP for importer@patchew.org; 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Mon, 18 Sep 2017 12:51:39 -0700 (PDT) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 18 Sep 2017 12:50:58 -0700 Message-Id: <20170918195100.17593-16-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918195100.17593-1-andrew.smirnov@gmail.com> References: <20170918195100.17593-1-andrew.smirnov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH 15/17] include/qemu: Add sizes.h from Linux X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add sizes.h from Linux to have a more readable way of specifying MemoryRegion sizes. Cc: Peter Maydell Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- include/qemu/sizes.h | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 include/qemu/sizes.h diff --git a/include/qemu/sizes.h b/include/qemu/sizes.h new file mode 100644 index 0000000000..9aedb9f8f6 --- /dev/null +++ b/include/qemu/sizes.h @@ -0,0 +1,47 @@ +/* + * Copy of include/linux/sizes.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef SIZES_H +#define SIZES_H + +#define SZ_1 0x00000001 +#define SZ_2 0x00000002 +#define SZ_4 0x00000004 +#define SZ_8 0x00000008 +#define SZ_16 0x00000010 +#define SZ_32 0x00000020 +#define SZ_64 0x00000040 +#define SZ_128 0x00000080 +#define SZ_256 0x00000100 +#define SZ_512 0x00000200 + +#define SZ_1K 0x00000400 +#define SZ_2K 0x00000800 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* SIZES_H */ --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH 16/17] i.MX: Add i.MX7 SOC implementation. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For now we only support the following devices: * up to 2 Cortex A9 cores (SMP works with PSCI) * A7 MPCORE (identical to A15 MPCORE) * 7 i.MX UARTs * 1 CCM device * 2 Ethernet controllers (FEC) * 3 SD controllers (USDHC) * 1 SNVS device * 1 WDT device Cc: Peter Maydell Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- default-configs/arm-softmmu.mak | 1 + hw/arm/Makefile.objs | 2 + hw/arm/fsl-imx7.c | 327 ++++++++++++++++++++++++++++++++++++= ++++ include/hw/arm/fsl-imx7.h | 114 ++++++++++++++ 4 files changed, 444 insertions(+) create mode 100644 hw/arm/fsl-imx7.c create mode 100644 include/hw/arm/fsl-imx7.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index bbdd3c1d8b..98396a3ad2 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -118,6 +118,7 @@ CONFIG_ALLWINNER_A10=3Dy CONFIG_FSL_IMX6=3Dy CONFIG_FSL_IMX31=3Dy CONFIG_FSL_IMX25=3Dy +CONFIG_FSL_IMX7=3Dy =20 CONFIG_IMX_I2C=3Dy =20 diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index a2e56ecaae..33f6051ae3 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -19,3 +19,5 @@ obj-$(CONFIG_FSL_IMX31) +=3D fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) +=3D fsl-imx6.o sabrelite.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_soc.o aspeed.o obj-$(CONFIG_MPS2) +=3D mps2.o +obj-$(CONFIG_FSL_IMX7) +=3D fsl-imx7.o + diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c new file mode 100644 index 0000000000..bd01bb7f59 --- /dev/null +++ b/hw/arm/fsl-imx7.c @@ -0,0 +1,327 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX7 SoC definitions + * + * Author: Andrey Smirnov + * + * Based on hw/arm/fsl-imx6.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/fsl-imx7.h" +#include "sysemu/sysemu.h" +#include "qemu/error-report.h" + +#define NAME_SIZE 20 + +#define for_each_cpu(i) for (i =3D 0; i < smp_cpus; i++) + +static void fsl_imx7_init(Object *obj) +{ + BusState *sysbus =3D sysbus_get_default(); + FslIMX7State *s =3D FSL_IMX7(obj); + char name[NAME_SIZE]; + int i; + + if (smp_cpus > FSL_IMX7_NUM_CPUS) { + error_report("%s: Only %d CPUs are supported (%d requested)", + TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus); + exit(1); + } + + for_each_cpu(i) { + object_initialize(&s->cpu[i], sizeof(s->cpu[i]), + "cortex-a7-" TYPE_ARM_CPU); + snprintf(name, NAME_SIZE, "cpu%d", i); + object_property_add_child(obj, name, OBJECT(&s->cpu[i]), + &error_fatal); + } + + /* + * A7MPCORE + */ + object_initialize(&s->a7mpcore, sizeof(s->a7mpcore), TYPE_A15MPCORE_PR= IV); + qdev_set_parent_bus(DEVICE(&s->a7mpcore), sysbus); + object_property_add_child(obj, "a7mpcore", + OBJECT(&s->a7mpcore), &error_fatal); + + /* + * CCM + */ + object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX7_CCM); + qdev_set_parent_bus(DEVICE(&s->ccm), sysbus); + object_property_add_child(obj, "ccm", OBJECT(&s->ccm), &error_fatal); + + /* + * UART + */ + for (i =3D 0; i < FSL_IMX7_NUM_UARTS; i++) { + object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SE= RIAL); + qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus); + snprintf(name, NAME_SIZE, "uart%d", i); + object_property_add_child(obj, name, OBJECT(&s->uart[i]), + &error_fatal); + } + + /* + * Ethernet + */ + for (i =3D 0; i < FSL_IMX7_NUM_ETHS; i++) { + object_initialize(&s->eth[i], sizeof(s->eth[i]), TYPE_IMX_ENET= ); + qdev_set_parent_bus(DEVICE(&s->eth[i]), sysbus); + snprintf(name, NAME_SIZE, "eth%d", i); + object_property_add_child(obj, name, OBJECT(&s->eth[i]), + &error_fatal); + } + + /* + * SDHCI + */ + for (i =3D 0; i < FSL_IMX7_NUM_USDHCS; i++) { + object_initialize(&s->usdhc[i], sizeof(s->usdhc[i]), + TYPE_IMX_USDHC); + qdev_set_parent_bus(DEVICE(&s->usdhc[i]), sysbus); + snprintf(name, NAME_SIZE, "usdhc%d", i); + object_property_add_child(obj, name, OBJECT(&s->usdhc[i]), + &error_fatal); + } + + /* + * SNVS + */ + object_initialize(&s->snvs, sizeof(s->snvs), TYPE_IMX7_SNVS); + qdev_set_parent_bus(DEVICE(&s->snvs), sysbus); + object_property_add_child(obj, "snvs", OBJECT(&s->snvs), &error_fatal); + + /* + * Watchdog + */ + for (i =3D 0; i < FSL_IMX7_NUM_WDTS; i++) { + object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_IMX2_WDT= ); + qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus); + snprintf(name, NAME_SIZE, "wdt%d", i); + object_property_add_child(obj, name, OBJECT(&s->wdt[i]), + &error_fatal); + } +} + +static void fsl_imx7_realize(DeviceState *dev, Error **errp) +{ + FslIMX7State *s =3D FSL_IMX7(dev); + Object *o; + int i; + qemu_irq irq; + + for_each_cpu(i) { + o =3D OBJECT(&s->cpu[i]); + + object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC, + "psci-conduit", &error_abort); + + object_property_set_bool(o, false, "has_el3", &error_abort); + + /* On uniprocessor, the CBAR is set to 0 */ + if (smp_cpus > 1) { + object_property_set_int(o, FSL_IMX7_A7MPCORE_ADDR, + "reset-cbar", &error_abort); + } + + if (i) { + /* Secondary CPUs start in PSCI powered-down state */ + object_property_set_bool(o, true, + "start-powered-off", &error_abort); + } + + object_property_set_bool(o, true, "realized", &error_abort); + } + + /* + * A7MPCORE + */ + object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu", + &error_abort); + object_property_set_int(OBJECT(&s->a7mpcore), + FSL_IMX7_MAX_IRQ + GIC_INTERNAL, + "num-irq", &error_abort); + + object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", + &error_abort); + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADD= R); + + for_each_cpu(i) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->a7mpcore); + DeviceState *d =3D DEVICE(qemu_get_cpu(i)); + + irq =3D qdev_get_gpio_in(d, ARM_CPU_IRQ); + sysbus_connect_irq(sbd, i, irq); + irq =3D qdev_get_gpio_in(d, ARM_CPU_FIQ); + sysbus_connect_irq(sbd, i + smp_cpus, irq); + } + + /* + * CCM + */ + object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abo= rt); + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR); + + /* + * UART + */ + for (i =3D 0; i < FSL_IMX7_NUM_UARTS; i++) { + static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] =3D { + FSL_IMX7_UART1_ADDR, + FSL_IMX7_UART2_ADDR, + FSL_IMX7_UART3_ADDR, + FSL_IMX7_UART4_ADDR, + FSL_IMX7_UART5_ADDR, + FSL_IMX7_UART6_ADDR, + FSL_IMX7_UART7_ADDR, + }; + + static const int FSL_IMX7_UARTn_IRQ[FSL_IMX7_NUM_UARTS] =3D { + FSL_IMX7_UART1_IRQ, + FSL_IMX7_UART2_IRQ, + FSL_IMX7_UART3_IRQ, + FSL_IMX7_UART4_IRQ, + FSL_IMX7_UART5_IRQ, + FSL_IMX7_UART6_IRQ, + FSL_IMX7_UART7_IRQ, + }; + + + if (i < MAX_SERIAL_PORTS) { + Chardev *chr; + chr =3D serial_hds[i]; + + if (!chr) { + char *label =3D g_strdup_printf("imx7.uart%d", i + 1); + chr =3D qemu_chr_new(label, "null"); + g_free(label); + serial_hds[i] =3D chr; + } + + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); + } + + object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", + &error_abort); + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADD= R[i]); + + irq =3D qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[= i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq); + } + + /* + * Etherenet + */ + for (i =3D 0; i < FSL_IMX7_NUM_ETHS; i++) { + static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] =3D { + FSL_IMX7_ENET1_ADDR, + FSL_IMX7_ENET2_ADDR, + }; + + qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); + object_property_set_bool(OBJECT(&s->eth[i]), true, "realized", + &error_abort); + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR= [i]); + + irq =3D qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i= , 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq); + irq =3D qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i= , 3)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq); + } + + /* + * USDHC + */ + for (i =3D 0; i < FSL_IMX7_NUM_USDHCS; i++) { + static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] =3D { + FSL_IMX7_USDHC1_ADDR, + FSL_IMX7_USDHC2_ADDR, + FSL_IMX7_USDHC3_ADDR, + }; + + static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] =3D { + FSL_IMX7_USDHC1_IRQ, + FSL_IMX7_USDHC2_IRQ, + FSL_IMX7_USDHC3_IRQ, + }; + + object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized", + &error_abort); + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, + FSL_IMX7_USDHCn_ADDR[i]); + + irq =3D qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ= [i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq); + } + + /* + * SNVS + */ + object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_ab= ort); + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR); + + /* + * Watchdog + */ + for (i =3D 0; i < FSL_IMX7_NUM_WDTS; i++) { + static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] =3D { + FSL_IMX7_WDOG1_ADDR, + FSL_IMX7_WDOG2_ADDR, + FSL_IMX7_WDOG3_ADDR, + FSL_IMX7_WDOG4_ADDR, + }; + + object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", + &error_abort); + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR= [i]); + } +} + +static void fsl_imx7_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D fsl_imx7_realize; + + /* + * Reason: creates an ARM CPU, thus use after free(), see + * arm_cpu_class_init() + */ + dc->user_creatable =3D false; + dc->desc =3D "i.MX7 SOC"; +} + +static const TypeInfo fsl_imx7_type_info =3D { + .name =3D TYPE_FSL_IMX7, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(FslIMX7State), + .instance_init =3D fsl_imx7_init, + .class_init =3D fsl_imx7_class_init, +}; + +static void fsl_imx7_register_types(void) +{ + type_register_static(&fsl_imx7_type_info); +} +type_init(fsl_imx7_register_types) diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h new file mode 100644 index 0000000000..0f3d43e379 --- /dev/null +++ b/include/hw/arm/fsl-imx7.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * i.MX7 SoC definitions + * + * Author: Andrey Smirnov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef FSL_IMX7_H +#define FSL_IMX7_H + +#include "hw/arm/arm.h" +#include "hw/cpu/a15mpcore.h" +#include "hw/misc/imx7_ccm.h" +#include "hw/misc/imx7_snvs.h" +#include "hw/misc/imx6_src.h" +#include "hw/misc/imx2_wdt.h" +#include "hw/char/imx_serial.h" +#include "hw/timer/imx_gpt.h" +#include "hw/timer/imx_epit.h" +#include "hw/i2c/imx_i2c.h" +#include "hw/gpio/imx_gpio.h" +#include "hw/sd/sdhci.h" +#include "hw/ssi/imx_spi.h" +#include "hw/net/imx_fec.h" +#include "exec/memory.h" +#include "cpu.h" +#include "qemu/sizes.h" + +#define TYPE_FSL_IMX7 "fsl,imx7" +#define FSL_IMX7(obj) OBJECT_CHECK(FslIMX7State, (obj), TYPE_FSL_IMX7) + +enum FslIMX7Configuration { + FSL_IMX7_NUM_CPUS =3D 2, + FSL_IMX7_NUM_UARTS =3D 7, + FSL_IMX7_NUM_ETHS =3D 2, + FSL_IMX7_NUM_USDHCS =3D 3, + FSL_IMX7_NUM_WDTS =3D 4, +}; + +typedef struct FslIMX7State { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + ARMCPU cpu[FSL_IMX7_NUM_CPUS]; + A15MPPrivState a7mpcore; + IMX7CCMState ccm; + IMX7SNVSState snvs; + IMXSerialState uart[FSL_IMX7_NUM_UARTS]; + IMXFECState eth[FSL_IMX7_NUM_ETHS]; + SDHCIState usdhc[FSL_IMX7_NUM_USDHCS]; + IMX2WdtState wdt[FSL_IMX7_NUM_WDTS]; +} FslIMX7State; + +enum FslIMX7MemoryMap { + FSL_IMX7_MMDC_ADDR =3D 0x80000000, + FSL_IMX7_MMDC_SIZE =3D SZ_2G, + + FSL_IMX7_WDOG1_ADDR =3D 0x30280000, + FSL_IMX7_WDOG2_ADDR =3D 0x30290000, + FSL_IMX7_WDOG3_ADDR =3D 0x302A0000, + FSL_IMX7_WDOG4_ADDR =3D 0x302B0000, + + FSL_IMX7_CCM_ADDR =3D 0x30360000, + FSL_IMX7_SNVS_ADDR =3D 0x30370000, + + FSL_IMX7_UART1_ADDR =3D 0x30860000, + FSL_IMX7_UART2_ADDR =3D 0x30870000, + FSL_IMX7_UART3_ADDR =3D 0x30880000, + FSL_IMX7_UART4_ADDR =3D 0x30A60000, + FSL_IMX7_UART5_ADDR =3D 0x30A70000, + FSL_IMX7_UART6_ADDR =3D 0x30A80000, + FSL_IMX7_UART7_ADDR =3D 0x30A90000, + + FSL_IMX7_ENET1_ADDR =3D 0x30BE0000, + FSL_IMX7_ENET2_ADDR =3D 0x30BF0000, + + FSL_IMX7_USDHC1_ADDR =3D 0x30B40000, + FSL_IMX7_USDHC2_ADDR =3D 0x30B50000, + FSL_IMX7_USDHC3_ADDR =3D 0x30B60000, + + FSL_IMX7_A7MPCORE_ADDR =3D 0x31000000, +}; + +enum FslIMX7IRQs { + + FSL_IMX7_USDHC1_IRQ =3D 22, + FSL_IMX7_USDHC2_IRQ =3D 23, + FSL_IMX7_USDHC3_IRQ =3D 24, + + FSL_IMX7_UART1_IRQ =3D 26, + FSL_IMX7_UART2_IRQ =3D 27, + FSL_IMX7_UART3_IRQ =3D 28, + FSL_IMX7_UART4_IRQ =3D 29, + FSL_IMX7_UART5_IRQ =3D 30, + FSL_IMX7_UART6_IRQ =3D 16, + FSL_IMX7_UART7_IRQ =3D 126, + +#define FSL_IMX7_ENET_IRQ(i, n) ((n) + ((i) ? 100 : 118)) + + FSL_IMX7_MAX_IRQ =3D 128, +}; + +#endif /* FSL_IMX7_H */ --=20 2.13.5 From nobody Mon Nov 3 18:25:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505764784839765.9662992362314; Mon, 18 Sep 2017 12:59:44 -0700 (PDT) Received: from localhost ([::1]:38656 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du2Cm-0005Ix-3m for importer@patchew.org; Mon, 18 Sep 2017 15:59:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37641) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1du256-0007Bk-DK for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1du253-0006RW-6f for qemu-devel@nongnu.org; Mon, 18 Sep 2017 15:51:48 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:33830) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1du250-0006Oo-GF; Mon, 18 Sep 2017 15:51:42 -0400 Received: by mail-pg0-x243.google.com with SMTP id u18so658895pgo.1; Mon, 18 Sep 2017 12:51:42 -0700 (PDT) Received: from squirtle.westlake.spaceflightindustries.com ([173.226.206.194]) by smtp.gmail.com with ESMTPSA id d186sm200791pfd.117.2017.09.18.12.51.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Sep 2017 12:51:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N9QB2DN+EchfJsJbXlsKbcMgz3nhojo1joW5GYmvljw=; b=pNN2Pz6eBhFo5dnTKDBacvMdW9pyBeCD7lfFR499jdJZJBclOmYgVxWO/m+nZM88Ak 2CO8nVqD+PXFil/SL3pMLazkNXqPrqJh8BqAgBNtabUqvkUT8UPn3eW+kKo1sNcXZ5fL CM6Vigw6V/sGJitEB+z95JyayWC7CaX0KhzNuhsASCbQhc4AguuSMViD8N2u6DDzbuTM JawI4cTREKvbviu+mTQvDHjY6XzUyWHZHsSVL9ktZ/xhnqchY4EerjOd97pqAkaSm308 SZrZvlCksR6YxVmFvGwTD6u4Md+JCPH8smK4uDh7e80TC8g2kEDqFi421TlYXTdsr9Kc cP6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N9QB2DN+EchfJsJbXlsKbcMgz3nhojo1joW5GYmvljw=; b=mu5nsCdNQj+j0xTQ6EYbmSOBaXhP4rq06coXyhld0lyJCpkAxjloGJ/JC7Aw/b4oyw y/vGZx8tDenIUQB6JXJ4X5C4dvI5gRa+J94INiJP+j4x5TdW6lV8HumIYrN0gW9h+jhe JbYBbkimvounhk8CkvGkmSzaynzCzfS0pNaJMI6wJd0XdxmRuO2eWO9zHz9Us4QeTswE GMYZYHiWKhvQ71v2iAobox2RFjcNGK0T79ItFGryXQrfl1lbH1AhmHPAkNs46iyPbDba 4WEbLUgtXjadWA1ofLouk5ODt4Rx6pUE7nKGRxGdRLFawLxDfVgG71uDkKu3qnm9W9op 4HKQ== X-Gm-Message-State: AHPjjUjvLpKUK/klLKXAnS8NzQWfQ8pRx/ljifQJ58Y4CwnJ5Y7qQHiX 5b6sgbPvq5ws5Vw5wsA= X-Google-Smtp-Source: ADKCNb71/N8mEGUIss7vGWJiC8l7fsoA99/eCHBbM1Hiwyh8Fl38sH/DRGfxTBj+/kdrvcEw/h8ESg== X-Received: by 10.101.86.79 with SMTP id m15mr32906450pgs.157.1505764301248; Mon, 18 Sep 2017 12:51:41 -0700 (PDT) From: Andrey Smirnov To: qemu-arm@nongnu.org Date: Mon, 18 Sep 2017 12:51:00 -0700 Message-Id: <20170918195100.17593-18-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918195100.17593-1-andrew.smirnov@gmail.com> References: <20170918195100.17593-1-andrew.smirnov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH 17/17] Implement support for i.MX7 Sabre board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Maydell , qemu-devel@nongnu.org, yurovsky@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: Peter Maydell Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov --- hw/arm/Makefile.objs | 2 +- hw/arm/mcimx7d-sabre.c | 100 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 hw/arm/mcimx7d-sabre.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 33f6051ae3..fc4a963de8 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -19,5 +19,5 @@ obj-$(CONFIG_FSL_IMX31) +=3D fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) +=3D fsl-imx6.o sabrelite.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_soc.o aspeed.o obj-$(CONFIG_MPS2) +=3D mps2.o -obj-$(CONFIG_FSL_IMX7) +=3D fsl-imx7.o +obj-$(CONFIG_FSL_IMX7) +=3D fsl-imx7.o mcimx7d-sabre.o =20 diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c new file mode 100644 index 0000000000..34e3933db8 --- /dev/null +++ b/hw/arm/mcimx7d-sabre.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2017, Impinj, Inc. + * + * MCIMX7D_SABRE Board System emulation. + * + * Author: Andrey Smirnov + * + * This code is licensed under the GPL, version 2 or later. + * See the file `COPYING' in the top level directory. + * + * It (partially) emulates a mcimx7d_sabre board, with a Freescale + * i.MX7 SoC + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/fsl-imx7.h" +#include "hw/boards.h" +#include "sysemu/sysemu.h" +#include "sysemu/device_tree.h" +#include "qemu/error-report.h" +#include "sysemu/qtest.h" +#include "net/net.h" + +typedef struct { + FslIMX7State soc; + MemoryRegion ram; +} MCIMX7Sabre; + +static void mcimx7d_add_psci_node(const struct arm_boot_info *boot_info, v= oid *fdt) +{ + const char comp[] =3D "arm,psci-0.2\0arm,psci"; + + qemu_fdt_add_subnode(fdt, "/psci"); + qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp)); + qemu_fdt_setprop_string(fdt, "/psci", "method", "smc"); +} + +static void mcimx7d_sabre_init(MachineState *machine) +{ + static struct arm_boot_info boot_info; + MCIMX7Sabre *s =3D g_new0(MCIMX7Sabre, 1); + Object *soc; + int i; + + if (machine->ram_size > FSL_IMX7_MMDC_SIZE) { + error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)= ", + machine->ram_size, FSL_IMX7_MMDC_SIZE); + exit(1); + } + + boot_info =3D (struct arm_boot_info) { + .loader_start =3D FSL_IMX7_MMDC_ADDR, + .board_id =3D -1, + .ram_size =3D machine->ram_size, + .kernel_filename =3D machine->kernel_filename, + .kernel_cmdline =3D machine->kernel_cmdline, + .initrd_filename =3D machine->initrd_filename, + .nb_cpus =3D smp_cpus, + .modify_dtb =3D mcimx7d_add_psci_node, + }; + + object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX7); + soc =3D OBJECT(&s->soc); + object_property_add_child(OBJECT(machine), "soc", soc, &error_fatal); + object_property_set_bool(soc, true, "realized", &error_fatal); + + memory_region_allocate_system_memory(&s->ram, NULL, "mcimx7d-sabre.ram= ", + machine->ram_size); + memory_region_add_subregion(get_system_memory(), + FSL_IMX7_MMDC_ADDR, &s->ram); + + for (i =3D 0; i < FSL_IMX7_NUM_USDHCS; i++) { + BusState *bus; + DeviceState *carddev; + DriveInfo *di; + BlockBackend *blk; + + di =3D drive_get_next(IF_SD); + blk =3D di ? blk_by_legacy_dinfo(di) : NULL; + bus =3D qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus"); + carddev =3D qdev_create(bus, TYPE_SD_CARD); + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); + object_property_set_bool(OBJECT(carddev), true, "realized", &error= _fatal); + } + + if (!qtest_enabled()) { + arm_load_kernel(&s->soc.cpu[0], &boot_info); + } +} + +static void mcimx7d_sabre_machine_init(MachineClass *mc) +{ + mc->desc =3D "Freescale i.MX7 DUAL SABRE (Cortex A7)"; + mc->init =3D mcimx7d_sabre_init; + mc->max_cpus =3D FSL_IMX7_NUM_CPUS; + mc->ignore_memory_transaction_failures =3D true; +} +DEFINE_MACHINE("mcimx7d-sabre", mcimx7d_sabre_machine_init) --=20 2.13.5