From nobody Tue Feb 10 20:07:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505661453045781.8013693073632; Sun, 17 Sep 2017 08:17:33 -0700 (PDT) Received: from localhost ([::1]:60953 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtbK8-0000q3-4F for importer@patchew.org; Sun, 17 Sep 2017 11:17:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52733) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dtb98-00089F-31 for qemu-devel@nongnu.org; Sun, 17 Sep 2017 11:06:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dtb93-0008Ix-OG for qemu-devel@nongnu.org; Sun, 17 Sep 2017 11:06:10 -0400 Received: from mail-oi0-x236.google.com ([2607:f8b0:4003:c06::236]:54223) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dtb93-0008IV-I6 for qemu-devel@nongnu.org; Sun, 17 Sep 2017 11:06:05 -0400 Received: by mail-oi0-x236.google.com with SMTP id 137so1350426oie.10 for ; Sun, 17 Sep 2017 08:06:05 -0700 (PDT) Received: from bigtime.twiddle.net (162.189-204-159.bestel.com.mx. [189.204.159.162]) by smtp.gmail.com with ESMTPSA id j2sm5348789oia.20.2017.09.17.08.06.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 Sep 2017 08:06:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xoE7SrDbdj8n+cP+EGiEPf88s5faiTZehfkmyeHF4Sg=; b=SczUwUXNWeIki9ZbhZLEZQvEjD0mnbi+w0qw0lbdTdl+15QY8hoMBOVwRCK0sHSXQz hmYPap9zbFc94dEvEIztmyuSPmz5UyiOP0fcUdgOceDSxdlAAV1zB/9tVt/+UyXwMOKb fLa6KDWUUR3xotwF/qEkn5rDbed8+DDKmoazc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xoE7SrDbdj8n+cP+EGiEPf88s5faiTZehfkmyeHF4Sg=; b=MG3PSh3xNRchzitSngE/wMoKnVq1MB913V7swT5lmbeUgs/utTV4w22A4r9xLxExec h1yI9cH+ftGmQvIKfVuGywNOzsoR+tCbWXpR5Y7mro4c8XrbkVZHDcFEbEGIUTsJdz9B 5yCGGismYx/6oGC8bNOjAIU5dcWOnBAYqIF5k0anCJbQYj4v/k4phoHgH4fWqVlb+lcx m/JhDJLB75YnhxoDXrQqvw4HP1DxVWXq9vsBQo8N0dSuH2Iok+6dhyKMpthFgGlcDK/r z7uhjd2sYBGbytg6Bb4jdwHvaHGnJPeaXLqGP+yEtC/3sNPoFSJ6v3LLdNLODyGvgCaa ZalA== X-Gm-Message-State: AHPjjUjtvPge+/i8EtAQXIYTlfia0DGxk5DtrceLmoDlf24JoFt65I07 PaDXKvaaBKEm7AqbY9jgtg== X-Google-Smtp-Source: AOwi7QAXuKZkyqW9gphf2ItOhOVnLq9T9WertwvC9XzcMMZWBhSN1xj8VXZdL2oboNejYjg6zMTiXw== X-Received: by 10.202.236.131 with SMTP id k125mr8759784oih.313.1505660764639; Sun, 17 Sep 2017 08:06:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 17 Sep 2017 08:05:32 -0700 Message-Id: <20170917150535.8284-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170917150535.8284-1-richard.henderson@linaro.org> References: <20170917150535.8284-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::236 Subject: [Qemu-devel] [PULL 14/17] tcg/arm: Fully convert tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 186 +++++++++++++++++++++++++++----------------= ---- 1 file changed, 107 insertions(+), 79 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 14599a8685..98a12535a5 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -2060,91 +2060,119 @@ static inline void tcg_out_op(TCGContext *s, TCGOp= code opc, } } =20 -static const TCGTargetOpDef arm_op_defs[] =3D { - { INDEX_op_exit_tb, { } }, - { INDEX_op_goto_tb, { } }, - { INDEX_op_br, { } }, - { INDEX_op_goto_ptr, { "r" } }, - - { INDEX_op_ld8u_i32, { "r", "r" } }, - { INDEX_op_ld8s_i32, { "r", "r" } }, - { INDEX_op_ld16u_i32, { "r", "r" } }, - { INDEX_op_ld16s_i32, { "r", "r" } }, - { INDEX_op_ld_i32, { "r", "r" } }, - { INDEX_op_st8_i32, { "r", "r" } }, - { INDEX_op_st16_i32, { "r", "r" } }, - { INDEX_op_st_i32, { "r", "r" } }, - - /* TODO: "r", "r", "ri" */ - { INDEX_op_add_i32, { "r", "r", "rIN" } }, - { INDEX_op_sub_i32, { "r", "rI", "rIN" } }, - { INDEX_op_mul_i32, { "r", "r", "r" } }, - { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, - { INDEX_op_muls2_i32, { "r", "r", "r", "r" } }, - { INDEX_op_and_i32, { "r", "r", "rIK" } }, - { INDEX_op_andc_i32, { "r", "r", "rIK" } }, - { INDEX_op_or_i32, { "r", "r", "rI" } }, - { INDEX_op_xor_i32, { "r", "r", "rI" } }, - { INDEX_op_neg_i32, { "r", "r" } }, - { INDEX_op_not_i32, { "r", "r" } }, - - { INDEX_op_shl_i32, { "r", "r", "ri" } }, - { INDEX_op_shr_i32, { "r", "r", "ri" } }, - { INDEX_op_sar_i32, { "r", "r", "ri" } }, - { INDEX_op_rotl_i32, { "r", "r", "ri" } }, - { INDEX_op_rotr_i32, { "r", "r", "ri" } }, - { INDEX_op_clz_i32, { "r", "r", "rIK" } }, - { INDEX_op_ctz_i32, { "r", "r", "rIK" } }, - - { INDEX_op_brcond_i32, { "r", "rIN" } }, - { INDEX_op_setcond_i32, { "r", "r", "rIN" } }, - { INDEX_op_movcond_i32, { "r", "r", "rIN", "rIK", "0" } }, - - { INDEX_op_add2_i32, { "r", "r", "r", "r", "rIN", "rIK" } }, - { INDEX_op_sub2_i32, { "r", "r", "rI", "rI", "rIN", "rIK" } }, - { INDEX_op_brcond2_i32, { "r", "r", "rIN", "rIN" } }, - { INDEX_op_setcond2_i32, { "r", "r", "r", "rIN", "rIN" } }, - -#if TARGET_LONG_BITS =3D=3D 32 - { INDEX_op_qemu_ld_i32, { "r", "l" } }, - { INDEX_op_qemu_ld_i64, { "r", "r", "l" } }, - { INDEX_op_qemu_st_i32, { "s", "s" } }, - { INDEX_op_qemu_st_i64, { "s", "s", "s" } }, -#else - { INDEX_op_qemu_ld_i32, { "r", "l", "l" } }, - { INDEX_op_qemu_ld_i64, { "r", "r", "l", "l" } }, - { INDEX_op_qemu_st_i32, { "s", "s", "s" } }, - { INDEX_op_qemu_st_i64, { "s", "s", "s", "s" } }, -#endif - - { INDEX_op_bswap16_i32, { "r", "r" } }, - { INDEX_op_bswap32_i32, { "r", "r" } }, - - { INDEX_op_ext8s_i32, { "r", "r" } }, - { INDEX_op_ext16s_i32, { "r", "r" } }, - { INDEX_op_ext16u_i32, { "r", "r" } }, +static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +{ + static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; + static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; + static const TCGTargetOpDef s_s =3D { .args_ct_str =3D { "s", "s" } }; + static const TCGTargetOpDef r_l =3D { .args_ct_str =3D { "r", "l" } }; + static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; + static const TCGTargetOpDef r_r_l =3D { .args_ct_str =3D { "r", "r", "= l" } }; + static const TCGTargetOpDef r_l_l =3D { .args_ct_str =3D { "r", "l", "= l" } }; + static const TCGTargetOpDef s_s_s =3D { .args_ct_str =3D { "s", "s", "= s" } }; + static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; + static const TCGTargetOpDef r_r_rI =3D { .args_ct_str =3D { "r", "r", = "rI" } }; + static const TCGTargetOpDef r_r_rIN + =3D { .args_ct_str =3D { "r", "r", "rIN" } }; + static const TCGTargetOpDef r_r_rIK + =3D { .args_ct_str =3D { "r", "r", "rIK" } }; + static const TCGTargetOpDef r_r_r_r + =3D { .args_ct_str =3D { "r", "r", "r", "r" } }; + static const TCGTargetOpDef r_r_l_l + =3D { .args_ct_str =3D { "r", "r", "l", "l" } }; + static const TCGTargetOpDef s_s_s_s + =3D { .args_ct_str =3D { "s", "s", "s", "s" } }; + static const TCGTargetOpDef br + =3D { .args_ct_str =3D { "r", "rIN" } }; + static const TCGTargetOpDef dep + =3D { .args_ct_str =3D { "r", "0", "rZ" } }; + static const TCGTargetOpDef movc + =3D { .args_ct_str =3D { "r", "r", "rIN", "rIK", "0" } }; + static const TCGTargetOpDef add2 + =3D { .args_ct_str =3D { "r", "r", "r", "r", "rIN", "rIK" } }; + static const TCGTargetOpDef sub2 + =3D { .args_ct_str =3D { "r", "r", "rI", "rI", "rIN", "rIK" } }; + static const TCGTargetOpDef br2 + =3D { .args_ct_str =3D { "r", "r", "rIN", "rIN" } }; + static const TCGTargetOpDef setc2 + =3D { .args_ct_str =3D { "r", "r", "r", "rIN", "rIN" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; =20 - { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, - { INDEX_op_extract_i32, { "r", "r" } }, - { INDEX_op_sextract_i32, { "r", "r" } }, + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_neg_i32: + case INDEX_op_not_i32: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap32_i32: + case INDEX_op_ext8s_i32: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16u_i32: + case INDEX_op_extract_i32: + case INDEX_op_sextract_i32: + return &r_r; =20 - { INDEX_op_div_i32, { "r", "r", "r" } }, - { INDEX_op_divu_i32, { "r", "r", "r" } }, + case INDEX_op_add_i32: + case INDEX_op_sub_i32: + case INDEX_op_setcond_i32: + return &r_r_rIN; + case INDEX_op_and_i32: + case INDEX_op_andc_i32: + case INDEX_op_clz_i32: + case INDEX_op_ctz_i32: + return &r_r_rIK; + case INDEX_op_mul_i32: + case INDEX_op_div_i32: + case INDEX_op_divu_i32: + return &r_r_r; + case INDEX_op_mulu2_i32: + case INDEX_op_muls2_i32: + return &r_r_r_r; + case INDEX_op_or_i32: + case INDEX_op_xor_i32: + return &r_r_rI; + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_rotl_i32: + case INDEX_op_rotr_i32: + return &r_r_ri; =20 - { INDEX_op_mb, { } }, - { -1 }, -}; + case INDEX_op_brcond_i32: + return &br; + case INDEX_op_deposit_i32: + return &dep; + case INDEX_op_movcond_i32: + return &movc; + case INDEX_op_add2_i32: + return &add2; + case INDEX_op_sub2_i32: + return &sub2; + case INDEX_op_brcond2_i32: + return &br2; + case INDEX_op_setcond2_i32: + return &setc2; =20 -static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) -{ - int i, n =3D ARRAY_SIZE(arm_op_defs); + case INDEX_op_qemu_ld_i32: + return TARGET_LONG_BITS =3D=3D 32 ? &r_l : &r_l_l; + case INDEX_op_qemu_ld_i64: + return TARGET_LONG_BITS =3D=3D 32 ? &r_r_l : &r_r_l_l; + case INDEX_op_qemu_st_i32: + return TARGET_LONG_BITS =3D=3D 32 ? &s_s : &s_s_s; + case INDEX_op_qemu_st_i64: + return TARGET_LONG_BITS =3D=3D 32 ? &s_s_s : &s_s_s_s; =20 - for (i =3D 0; i < n; ++i) { - if (arm_op_defs[i].op =3D=3D op) { - return &arm_op_defs[i]; - } + default: + return NULL; } - return NULL; } =20 static void tcg_target_init(TCGContext *s) --=20 2.13.5