From nobody Thu May 2 22:49:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505488212264675.9905132223981; Fri, 15 Sep 2017 08:10:12 -0700 (PDT) Received: from localhost ([::1]:53750 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dssFv-0000rb-93 for importer@patchew.org; Fri, 15 Sep 2017 11:10:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44590) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dssEn-0000Js-MJ for qemu-devel@nongnu.org; Fri, 15 Sep 2017 11:09:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dssEf-0004AX-97 for qemu-devel@nongnu.org; Fri, 15 Sep 2017 11:09:01 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37392) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dssEe-00049q-Ml; Fri, 15 Sep 2017 11:08:53 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]) by orth.archaic.org.uk with esmtp (Exim 4.89) (envelope-from ) id 1dssEb-0007Ts-7M; Fri, 15 Sep 2017 16:08:49 +0100 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dssEb-00068c-69; Fri, 15 Sep 2017 16:08:49 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 15 Sep 2017 16:08:49 +0100 Message-Id: <20170915150849.23557-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.11.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH] target/arm: Remove out of date ARM ARM section references in A64 decoder X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In the A64 decoder, we have a lot of references to section numbers from version A.a of the v8A ARM ARM (DDI0487). This version of the document is now long obsolete (we are currently on revision B.a), and various intervening versions renumbered all the sections. The most recent B.a version of the document doesn't assign section numbers at all to the individual instruction classes in the way that the various A.x versions did. The simplest thing to do is just to delete all the out of date C.x.x references. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- Definitely a Friday afternoon kind of a patch... target/arm/translate-a64.c | 227 +++++++++++++++++++++++------------------= ---- 1 file changed, 114 insertions(+), 113 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9017e30510..e04007376c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1203,12 +1203,14 @@ static inline AArch64DecodeFn *lookup_disas_fn(cons= t AArch64DecodeTable *table, } =20 /* - * the instruction disassembly implemented here matches - * the instruction encoding classifications in chapter 3 (C3) - * of the ARM Architecture Reference Manual (DDI0487A_a) + * The instruction disassembly implemented here matches + * the instruction encoding classifications in chapter C4 + * of the ARM Architecture Reference Manual (DDI0487B_a); + * classification names and decode diagrams here should generally + * match up with those in the manual. */ =20 -/* C3.2.7 Unconditional branch (immediate) +/* Unconditional branch (immediate) * 31 30 26 25 0 * +----+-----------+-------------------------------------+ * | op | 0 0 1 0 1 | imm26 | @@ -1219,15 +1221,15 @@ static void disas_uncond_b_imm(DisasContext *s, uin= t32_t insn) uint64_t addr =3D s->pc + sextract32(insn, 0, 26) * 4 - 4; =20 if (insn & (1U << 31)) { - /* C5.6.26 BL Branch with link */ + /* BL Branch with link */ tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); } =20 - /* C5.6.20 B Branch / C5.6.26 BL Branch with link */ + /* B Branch / BL Branch with link */ gen_goto_tb(s, 0, addr); } =20 -/* C3.2.1 Compare & branch (immediate) +/* Compare and branch (immediate) * 31 30 25 24 23 5 4 0 * +----+-------------+----+---------------------+--------+ * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | @@ -1256,7 +1258,7 @@ static void disas_comp_b_imm(DisasContext *s, uint32_= t insn) gen_goto_tb(s, 1, addr); } =20 -/* C3.2.5 Test & branch (immediate) +/* Test and branch (immediate) * 31 30 25 24 23 19 18 5 4 0 * +----+-------------+----+-------+-------------+------+ * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | @@ -1285,7 +1287,7 @@ static void disas_test_b_imm(DisasContext *s, uint32_= t insn) gen_goto_tb(s, 1, addr); } =20 -/* C3.2.2 / C5.6.19 Conditional branch (immediate) +/* Conditional branch (immediate) * 31 25 24 23 5 4 3 0 * +---------------+----+---------------------+----+------+ * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | @@ -1316,7 +1318,7 @@ static void disas_cond_b_imm(DisasContext *s, uint32_= t insn) } } =20 -/* C5.6.68 HINT */ +/* HINT instruction group, including various allocated HINTs */ static void handle_hint(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int c= rm) { @@ -1401,7 +1403,7 @@ static void handle_sync(DisasContext *s, uint32_t ins= n, } } =20 -/* C5.6.130 MSR (immediate) - move immediate to processor state field */ +/* MSR (immediate) - move immediate to processor state field */ static void handle_msr_i(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int = crm) { @@ -1477,10 +1479,10 @@ static void gen_set_nzcv(TCGv_i64 tcg_rt) tcg_temp_free_i32(nzcv); } =20 -/* C5.6.129 MRS - move from system register - * C5.6.131 MSR (register) - move to system register - * C5.6.204 SYS - * C5.6.205 SYSL +/* MRS - move from system register + * MSR (register) - move to system register + * SYS + * SYSL * These are all essentially the same insn in 'read' and 'write' * versions, with varying op0 fields. */ @@ -1603,7 +1605,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, } } =20 -/* C3.2.4 System +/* System * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 * +---------------------+---+-----+-----+-------+-------+-----+------+ * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | @@ -1626,13 +1628,13 @@ static void disas_system(DisasContext *s, uint32_t = insn) return; } switch (crn) { - case 2: /* C5.6.68 HINT */ + case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */ handle_hint(s, insn, op1, op2, crm); break; case 3: /* CLREX, DSB, DMB, ISB */ handle_sync(s, insn, op1, op2, crm); break; - case 4: /* C5.6.130 MSR (immediate) */ + case 4: /* MSR (immediate) */ handle_msr_i(s, insn, op1, op2, crm); break; default: @@ -1644,7 +1646,7 @@ static void disas_system(DisasContext *s, uint32_t in= sn) handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); } =20 -/* C3.2.3 Exception generation +/* Exception generation * * 31 24 23 21 20 5 4 2 1 0 * +-----------------+-----+------------------------+-----+----+ @@ -1751,7 +1753,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) } } =20 -/* C3.2.7 Unconditional branch (register) +/* Unconditional branch (register) * 31 25 24 21 20 16 15 10 9 5 4 0 * +---------------+-------+-------+-------+------+-------+ * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | @@ -1806,7 +1808,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) s->base.is_jmp =3D DISAS_JUMP; } =20 -/* C3.2 Branches, exception generating and system instructions */ +/* Branches, exception generating and system instructions */ static void disas_b_exc_sys(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 7)) { @@ -1974,7 +1976,7 @@ static bool disas_ldst_compute_iss_sf(int size, bool = is_signed, int opc) return regsize =3D=3D 64; } =20 -/* C3.3.6 Load/store exclusive +/* Load/store exclusive * * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 * +-----+-------------+----+---+----+------+----+-------+------+------+ @@ -2051,7 +2053,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) } =20 /* - * C3.3.5 Load register (literal) + * Load register (literal) * * 31 30 29 27 26 25 24 23 5 4 0 * +-----+-------+---+-----+-------------------+-------+ @@ -2107,15 +2109,15 @@ static void disas_ld_lit(DisasContext *s, uint32_t = insn) } =20 /* - * C5.6.80 LDNP (Load Pair - non-temporal hint) - * C5.6.81 LDP (Load Pair - non vector) - * C5.6.82 LDPSW (Load Pair Signed Word - non vector) - * C5.6.176 STNP (Store Pair - non-temporal hint) - * C5.6.177 STP (Store Pair - non vector) - * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint) - * C6.3.165 LDP (Load Pair of SIMD&FP) - * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint) - * C6.3.284 STP (Store Pair of SIMD&FP) + * LDNP (Load Pair - non-temporal hint) + * LDP (Load Pair - non vector) + * LDPSW (Load Pair Signed Word - non vector) + * STNP (Store Pair - non-temporal hint) + * STP (Store Pair - non vector) + * LDNP (Load Pair of SIMD&FP - non-temporal hint) + * LDP (Load Pair of SIMD&FP) + * STNP (Store Pair of SIMD&FP - non-temporal hint) + * STP (Store Pair of SIMD&FP) * * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 * +-----+-------+---+---+-------+---+-----------------------------+ @@ -2261,9 +2263,9 @@ static void disas_ldst_pair(DisasContext *s, uint32_t= insn) } =20 /* - * C3.3.8 Load/store (immediate post-indexed) - * C3.3.9 Load/store (immediate pre-indexed) - * C3.3.12 Load/store (unscaled immediate) + * Load/store (immediate post-indexed) + * Load/store (immediate pre-indexed) + * Load/store (unscaled immediate) * * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 * +----+-------+---+-----+-----+---+--------+-----+------+------+ @@ -2379,7 +2381,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, } =20 /* - * C3.3.10 Load/store (register offset) + * Load/store (register offset) * * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ @@ -2476,7 +2478,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, } =20 /* - * C3.3.13 Load/store (unsigned immediate) + * Load/store (unsigned immediate) * * 31 30 29 27 26 25 24 23 22 21 10 9 5 * +----+-------+---+-----+-----+------------+-------+------+ @@ -2587,14 +2589,14 @@ static void disas_ldst_reg(DisasContext *s, uint32_= t insn) } } =20 -/* C3.3.1 AdvSIMD load/store multiple structures +/* AdvSIMD load/store multiple structures * * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 * +---+---+---------------+---+-------------+--------+------+------+-----= -+ * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt = | * +---+---+---------------+---+-------------+--------+------+------+-----= -+ * - * C3.3.2 AdvSIMD load/store multiple structures (post-indexed) + * AdvSIMD load/store multiple structures (post-indexed) * * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 * +---+---+---------------+---+---+---------+--------+------+------+-----= -+ @@ -2719,14 +2721,14 @@ static void disas_ldst_multiple_struct(DisasContext= *s, uint32_t insn) tcg_temp_free_i64(tcg_addr); } =20 -/* C3.3.3 AdvSIMD load/store single structure +/* AdvSIMD load/store single structure * * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 = 0 * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt= | * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ * - * C3.3.4 AdvSIMD load/store single structure (post-indexed) + * AdvSIMD load/store single structure (post-indexed) * * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 = 0 * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ @@ -2869,7 +2871,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) tcg_temp_free_i64(tcg_addr); } =20 -/* C3.3 Loads and stores */ +/* Loads and stores */ static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { @@ -2899,7 +2901,7 @@ static void disas_ldst(DisasContext *s, uint32_t insn) } } =20 -/* C3.4.6 PC-rel. addressing +/* PC-rel. addressing * 31 30 29 28 24 23 5 4 0 * +----+-------+-----------+-------------------+------+ * | op | immlo | 1 0 0 0 0 | immhi | Rd | @@ -2928,7 +2930,7 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_= t insn) } =20 /* - * C3.4.1 Add/subtract (immediate) + * Add/subtract (immediate) * * 31 30 29 28 24 23 22 21 10 9 5 4 0 * +--+--+--+-----------+-----+-------------+-----+-----+ @@ -3078,7 +3080,7 @@ static bool logic_imm_decode_wmask(uint64_t *result, = unsigned int immn, return true; } =20 -/* C3.4.4 Logical (immediate) +/* Logical (immediate) * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 * +----+-----+-------------+---+------+------+------+------+ * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd | @@ -3151,7 +3153,7 @@ static void disas_logic_imm(DisasContext *s, uint32_t= insn) } =20 /* - * C3.4.5 Move wide (immediate) + * Move wide (immediate) * * 31 30 29 28 23 22 21 20 5 4 0 * +--+-----+-------------+-----+----------------+------+ @@ -3203,7 +3205,7 @@ static void disas_movw_imm(DisasContext *s, uint32_t = insn) } } =20 -/* C3.4.2 Bitfield +/* Bitfield * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 * +----+-----+-------------+---+------+------+------+------+ * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd | @@ -3281,7 +3283,7 @@ static void disas_bitfield(DisasContext *s, uint32_t = insn) } } =20 -/* C3.4.3 Extract +/* Extract * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0 * +----+------+-------------+---+----+------+--------+------+------+ * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd | @@ -3341,7 +3343,7 @@ static void disas_extract(DisasContext *s, uint32_t i= nsn) } } =20 -/* C3.4 Data processing - immediate */ +/* Data processing - immediate */ static void disas_data_proc_imm(DisasContext *s, uint32_t insn) { switch (extract32(insn, 23, 6)) { @@ -3435,7 +3437,7 @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src,= int sf, } } =20 -/* C3.5.10 Logical (shifted register) +/* Logical (shifted register) * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 * +----+-----+-----------+-------+---+------+--------+------+------+ * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd | @@ -3526,7 +3528,7 @@ static void disas_logic_reg(DisasContext *s, uint32_t= insn) } =20 /* - * C3.5.1 Add/subtract (extended register) + * Add/subtract (extended register) * * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0| * +--+--+--+-----------+-----+--+-------+------+------+----+----+ @@ -3599,7 +3601,7 @@ static void disas_add_sub_ext_reg(DisasContext *s, ui= nt32_t insn) } =20 /* - * C3.5.2 Add/subtract (shifted register) + * Add/subtract (shifted register) * * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0 * +--+--+--+-----------+-----+--+-------+---------+------+------+ @@ -3662,13 +3664,12 @@ static void disas_add_sub_reg(DisasContext *s, uint= 32_t insn) tcg_temp_free_i64(tcg_result); } =20 -/* C3.5.9 Data-processing (3 source) - - 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0 - +--+------+-----------+------+------+----+------+------+------+ - |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd | - +--+------+-----------+------+------+----+------+------+------+ - +/* Data-processing (3 source) + * + * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0 + * +--+------+-----------+------+------+----+------+------+------+ + * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd | + * +--+------+-----------+------+------+----+------+------+------+ */ static void disas_data_proc_3src(DisasContext *s, uint32_t insn) { @@ -3761,7 +3762,7 @@ static void disas_data_proc_3src(DisasContext *s, uin= t32_t insn) tcg_temp_free_i64(tcg_tmp); } =20 -/* C3.5.3 - Add/subtract (with carry) +/* Add/subtract (with carry) * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 * +--+--+--+------------------------+------+---------+------+-----+ * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd | @@ -3803,7 +3804,7 @@ static void disas_adc_sbc(DisasContext *s, uint32_t i= nsn) } } =20 -/* C3.5.4 - C3.5.5 Conditional compare (immediate / register) +/* Conditional compare (immediate / register) * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 = 0 * +--+--+--+------------------------+--------+------+----+--+------+--+--= ---+ * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nz= cv | @@ -3908,7 +3909,7 @@ static void disas_cc(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tcg_t2); } =20 -/* C3.5.6 Conditional select +/* Conditional select * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0 * +----+----+---+-----------------+------+------+-----+------+------+ * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd | @@ -4019,7 +4020,7 @@ static void handle_rbit(DisasContext *s, unsigned int= sf, } } =20 -/* C5.6.149 REV with sf=3D=3D1, opcode=3D=3D3 ("REV64") */ +/* REV with sf=3D=3D1, opcode=3D=3D3 ("REV64") */ static void handle_rev64(DisasContext *s, unsigned int sf, unsigned int rn, unsigned int rd) { @@ -4030,8 +4031,8 @@ static void handle_rev64(DisasContext *s, unsigned in= t sf, tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn)); } =20 -/* C5.6.149 REV with sf=3D=3D0, opcode=3D=3D2 - * C5.6.151 REV32 (sf=3D=3D1, opcode=3D=3D2) +/* REV with sf=3D=3D0, opcode=3D=3D2 + * REV32 (sf=3D=3D1, opcode=3D=3D2) */ static void handle_rev32(DisasContext *s, unsigned int sf, unsigned int rn, unsigned int rd) @@ -4056,7 +4057,7 @@ static void handle_rev32(DisasContext *s, unsigned in= t sf, } } =20 -/* C5.6.150 REV16 (opcode=3D=3D1) */ +/* REV16 (opcode=3D=3D1) */ static void handle_rev16(DisasContext *s, unsigned int sf, unsigned int rn, unsigned int rd) { @@ -4075,7 +4076,7 @@ static void handle_rev16(DisasContext *s, unsigned in= t sf, tcg_temp_free_i64(tcg_tmp); } =20 -/* C3.5.7 Data-processing (1 source) +/* Data-processing (1 source) * 31 30 29 28 21 20 16 15 10 9 5 4 0 * +----+---+---+-----------------+---------+--------+------+------+ * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd | @@ -4144,7 +4145,7 @@ static void handle_div(DisasContext *s, bool is_signe= d, unsigned int sf, } } =20 -/* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */ +/* LSLV, LSRV, ASRV, RORV */ static void handle_shift_reg(DisasContext *s, enum a64_shift_type shift_type, unsigned int = sf, unsigned int rm, unsigned int rn, unsigned in= t rd) @@ -4206,7 +4207,7 @@ static void handle_crc32(DisasContext *s, tcg_temp_free_i32(tcg_bytes); } =20 -/* C3.5.8 Data-processing (2 source) +/* Data-processing (2 source) * 31 30 29 28 21 20 16 15 10 9 5 4 0 * +----+---+---+-----------------+------+--------+------+------+ * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd | @@ -4265,7 +4266,7 @@ static void disas_data_proc_2src(DisasContext *s, uin= t32_t insn) } } =20 -/* C3.5 Data processing - register */ +/* Data processing - register */ static void disas_data_proc_reg(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 5)) { @@ -4359,7 +4360,7 @@ static void handle_fp_compare(DisasContext *s, bool i= s_double, tcg_temp_free_i64(tcg_flags); } =20 -/* C3.6.22 Floating point compare +/* Floating point compare * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 = 0 * +---+---+---+-----------+------+---+------+-----+---------+------+-----= --+ * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2= | @@ -4389,7 +4390,7 @@ static void disas_fp_compare(DisasContext *s, uint32_= t insn) handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2); } =20 -/* C3.6.23 Floating point conditional compare +/* Floating point conditional compare * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 = 0 * +---+---+---+-----------+------+---+------+------+-----+------+----+---= ---+ * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nz= cv | @@ -4437,7 +4438,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t = insn) } } =20 -/* C3.6.24 Floating point conditional select +/* Floating point conditional select * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+------+-----+------+------+ * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd | @@ -4484,7 +4485,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t i= nsn) tcg_temp_free_i64(t_true); } =20 -/* C3.6.25 Floating-point data-processing (1 source) - single precision */ +/* Floating-point data-processing (1 source) - single precision */ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int= rn) { TCGv_ptr fpst; @@ -4540,7 +4541,7 @@ static void handle_fp_1src_single(DisasContext *s, in= t opcode, int rd, int rn) tcg_temp_free_i32(tcg_res); } =20 -/* C3.6.25 Floating-point data-processing (1 source) - double precision */ +/* Floating-point data-processing (1 source) - double precision */ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int= rn) { TCGv_ptr fpst; @@ -4662,7 +4663,7 @@ static void handle_fp_fcvt(DisasContext *s, int opcod= e, } } =20 -/* C3.6.25 Floating point data-processing (1 source) +/* Floating point data-processing (1 source) * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0 * +---+---+---+-----------+------+---+--------+-----------+------+------+ * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd | @@ -4720,7 +4721,7 @@ static void disas_fp_1src(DisasContext *s, uint32_t i= nsn) } } =20 -/* C3.6.26 Floating-point data-processing (2 source) - single precision */ +/* Floating-point data-processing (2 source) - single precision */ static void handle_fp_2src_single(DisasContext *s, int opcode, int rd, int rn, int rm) { @@ -4773,7 +4774,7 @@ static void handle_fp_2src_single(DisasContext *s, in= t opcode, tcg_temp_free_i32(tcg_res); } =20 -/* C3.6.26 Floating-point data-processing (2 source) - double precision */ +/* Floating-point data-processing (2 source) - double precision */ static void handle_fp_2src_double(DisasContext *s, int opcode, int rd, int rn, int rm) { @@ -4826,7 +4827,7 @@ static void handle_fp_2src_double(DisasContext *s, in= t opcode, tcg_temp_free_i64(tcg_res); } =20 -/* C3.6.26 Floating point data-processing (2 source) +/* Floating point data-processing (2 source) * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+--------+-----+------+------+ * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd | @@ -4863,7 +4864,7 @@ static void disas_fp_2src(DisasContext *s, uint32_t i= nsn) } } =20 -/* C3.6.27 Floating-point data-processing (3 source) - single precision */ +/* Floating-point data-processing (3 source) - single precision */ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1, int rd, int rn, int rm, int ra) { @@ -4901,7 +4902,7 @@ static void handle_fp_3src_single(DisasContext *s, bo= ol o0, bool o1, tcg_temp_free_i32(tcg_res); } =20 -/* C3.6.27 Floating-point data-processing (3 source) - double precision */ +/* Floating-point data-processing (3 source) - double precision */ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, int rd, int rn, int rm, int ra) { @@ -4939,7 +4940,7 @@ static void handle_fp_3src_double(DisasContext *s, bo= ol o0, bool o1, tcg_temp_free_i64(tcg_res); } =20 -/* C3.6.27 Floating point data-processing (3 source) +/* Floating point data-processing (3 source) * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0 * +---+---+---+-----------+------+----+------+----+------+------+------+ * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd | @@ -4973,7 +4974,7 @@ static void disas_fp_3src(DisasContext *s, uint32_t i= nsn) } } =20 -/* C3.6.28 Floating point immediate +/* Floating point immediate * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0 * +---+---+---+-----------+------+---+------------+-------+------+------+ * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd | @@ -5144,7 +5145,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, tcg_temp_free_i32(tcg_shift); } =20 -/* C3.6.29 Floating point <-> fixed point conversions +/* Floating point <-> fixed point conversions * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 = 0 * +----+---+---+-----------+------+---+-------+--------+-------+------+--= ----+ * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | = Rd | @@ -5244,7 +5245,7 @@ static void handle_fmov(DisasContext *s, int rd, int = rn, int type, bool itof) } } =20 -/* C3.6.30 Floating point <-> integer conversions +/* Floating point <-> integer conversions * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4= 0 * +----+---+---+-----------+------+---+-------+-----+-------------+----+-= ---+ * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | = Rd | @@ -5379,7 +5380,7 @@ static void do_ext64(DisasContext *s, TCGv_i64 tcg_le= ft, TCGv_i64 tcg_right, tcg_temp_free_i64(tcg_tmp); } =20 -/* C3.6.1 EXT +/* EXT * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0 * +---+---+-------------+-----+---+------+---+------+---+------+------+ * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd | @@ -5452,7 +5453,7 @@ static void disas_simd_ext(DisasContext *s, uint32_t = insn) tcg_temp_free_i64(tcg_resh); } =20 -/* C3.6.2 TBL/TBX +/* BL/TBX * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 = 0 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+---= ---+ * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | R= d | @@ -5520,7 +5521,7 @@ static void disas_simd_tb(DisasContext *s, uint32_t i= nsn) tcg_temp_free_i64(tcg_resh); } =20 -/* C3.6.3 ZIP/UZP/TRN +/* ZIP/UZP/TRN * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 * +---+---+-------------+------+---+------+---+------------------+------+ * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd | @@ -5632,7 +5633,7 @@ static void do_minmaxop(DisasContext *s, TCGv_i32 tcg= _elt1, TCGv_i32 tcg_elt2, } } =20 -/* C3.6.4 AdvSIMD across lanes +/* AdvSIMD across lanes * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 * +---+---+---+-----------+------+-----------+--------+-----+------+-----= -+ * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd = | @@ -5799,7 +5800,7 @@ static void disas_simd_across_lanes(DisasContext *s, = uint32_t insn) tcg_temp_free_i64(tcg_res); } =20 -/* C6.3.31 DUP (Element, Vector) +/* DUP (Element, Vector) * * 31 30 29 21 20 16 15 10 9 5 4 0 * +---+---+-------------------+--------+-------------+------+------+ @@ -5842,7 +5843,7 @@ static void handle_simd_dupe(DisasContext *s, int is_= q, int rd, int rn, tcg_temp_free_i64(tmp); } =20 -/* C6.3.31 DUP (element, scalar) +/* DUP (element, scalar) * 31 21 20 16 15 10 9 5 4 0 * +-----------------------+--------+-------------+------+------+ * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd | @@ -5875,7 +5876,7 @@ static void handle_simd_dupes(DisasContext *s, int rd= , int rn, tcg_temp_free_i64(tmp); } =20 -/* C6.3.32 DUP (General) +/* DUP (General) * * 31 30 29 21 20 16 15 10 9 5 4 0 * +---+---+-------------------+--------+-------------+------+------+ @@ -5909,7 +5910,7 @@ static void handle_simd_dupg(DisasContext *s, int is_= q, int rd, int rn, } } =20 -/* C6.3.150 INS (Element) +/* INS (Element) * * 31 21 20 16 15 14 11 10 9 5 4 0 * +-----------------------+--------+------------+---+------+------+ @@ -5947,7 +5948,7 @@ static void handle_simd_inse(DisasContext *s, int rd,= int rn, } =20 =20 -/* C6.3.151 INS (General) +/* INS (General) * * 31 21 20 16 15 10 9 5 4 0 * +-----------------------+--------+-------------+------+------+ @@ -5976,8 +5977,8 @@ static void handle_simd_insg(DisasContext *s, int rd,= int rn, int imm5) } =20 /* - * C6.3.321 UMOV (General) - * C6.3.237 SMOV (General) + * UMOV (General) + * SMOV (General) * * 31 30 29 21 20 16 15 12 10 9 5 4 0 * +---+---+-------------------+--------+-------------+------+------+ @@ -6022,7 +6023,7 @@ static void handle_simd_umov_smov(DisasContext *s, in= t is_q, int is_signed, } } =20 -/* C3.6.5 AdvSIMD copy +/* AdvSIMD copy * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 * +---+---+----+-----------------+------+---+------+---+------+------+ * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | @@ -6074,7 +6075,7 @@ static void disas_simd_copy(DisasContext *s, uint32_t= insn) } } =20 -/* C3.6.6 AdvSIMD modified immediate +/* AdvSIMD modified immediate * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 = 0 * +---+---+----+---------------------+-----+-------+----+---+-------+----= --+ * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd= | @@ -6207,7 +6208,7 @@ static void disas_simd_mod_imm(DisasContext *s, uint3= 2_t insn) tcg_temp_free_i64(tcg_imm); } =20 -/* C3.6.7 AdvSIMD scalar copy +/* AdvSIMD scalar copy * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0 * +-----+----+-----------------+------+---+------+---+------+------+ * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd | @@ -6230,7 +6231,7 @@ static void disas_simd_scalar_copy(DisasContext *s, u= int32_t insn) handle_simd_dupes(s, rd, rn, imm5); } =20 -/* C3.6.8 AdvSIMD scalar pairwise +/* AdvSIMD scalar pairwise * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 * +-----+---+-----------+------+-----------+--------+-----+------+------+ * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd | @@ -6956,7 +6957,7 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, tcg_temp_free_i32(tcg_rmode); } =20 -/* C3.6.9 AdvSIMD scalar shift by immediate +/* AdvSIMD scalar shift by immediate * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 * +-----+---+-------------+------+------+--------+---+------+------+ * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | @@ -7031,7 +7032,7 @@ static void disas_simd_scalar_shift_imm(DisasContext = *s, uint32_t insn) } } =20 -/* C3.6.10 AdvSIMD scalar three different +/* AdvSIMD scalar three different * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * +-----+---+-----------+------+---+------+--------+-----+------+------+ * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | @@ -7418,7 +7419,7 @@ static void handle_3same_float(DisasContext *s, int s= ize, int elements, } } =20 -/* C3.6.11 AdvSIMD scalar three same +/* AdvSIMD scalar three same * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 * +-----+---+-----------+------+---+------+--------+---+------+------+ * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | @@ -8087,7 +8088,7 @@ static void handle_2misc_satacc(DisasContext *s, bool= is_scalar, bool is_u, } } =20 -/* C3.6.12 AdvSIMD scalar two reg misc +/* AdvSIMD scalar two reg misc * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 * +-----+---+-----------+------+-----------+--------+-----+------+------+ * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd | @@ -8515,7 +8516,7 @@ static void handle_vec_simd_shrn(DisasContext *s, boo= l is_q, } =20 =20 -/* C3.6.14 AdvSIMD shift by immediate +/* AdvSIMD shift by immediate * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0 * +---+---+---+-------------+------+------+--------+---+------+------+ * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd | @@ -8934,7 +8935,7 @@ static void handle_pmull_64(DisasContext *s, int is_q= , int rd, int rn, int rm) tcg_temp_free_i64(tcg_res); } =20 -/* C3.6.15 AdvSIMD three different +/* AdvSIMD three different * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+--------+-----+------+------+ * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd | @@ -9671,7 +9672,7 @@ static void disas_simd_3same_int(DisasContext *s, uin= t32_t insn) } } =20 -/* C3.6.16 AdvSIMD three same +/* AdvSIMD three same * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+--------+---+------+------+ * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd | @@ -9940,7 +9941,7 @@ static void handle_shll(DisasContext *s, bool is_q, i= nt size, int rn, int rd) } } =20 -/* C3.6.17 AdvSIMD two reg misc +/* AdvSIMD two reg misc * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 * +---+---+---+-----------+------+-----------+--------+-----+------+-----= -+ * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd = | @@ -10452,12 +10453,12 @@ static void disas_simd_two_reg_misc(DisasContext = *s, uint32_t insn) } } =20 -/* C3.6.13 AdvSIMD scalar x indexed element +/* AdvSIMD scalar x indexed element * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 * +-----+---+-----------+------+---+---+------+-----+---+---+------+-----= -+ * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd = | * +-----+---+-----------+------+---+---+------+-----+---+---+------+-----= -+ - * C3.6.18 AdvSIMD vector x indexed element + * AdvSIMD vector x indexed element * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 = 0 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+---= ---+ * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | R= d | @@ -10907,7 +10908,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } } =20 -/* C3.6.19 Crypto AES +/* Crypto AES * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 * +-----------------+------+-----------+--------+-----+------+------+ * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | @@ -10970,7 +10971,7 @@ static void disas_crypto_aes(DisasContext *s, uint3= 2_t insn) tcg_temp_free_i32(tcg_decrypt); } =20 -/* C3.6.20 Crypto three-reg SHA +/* Crypto three-reg SHA * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0 * +-----------------+------+---+------+---+--------+-----+------+------+ * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd | @@ -11042,7 +11043,7 @@ static void disas_crypto_three_reg_sha(DisasContext= *s, uint32_t insn) tcg_temp_free_i32(tcg_rm_regno); } =20 -/* C3.6.21 Crypto two-reg SHA +/* Crypto two-reg SHA * 31 24 23 22 21 17 16 12 11 10 9 5 4 0 * +-----------------+------+-----------+--------+-----+------+------+ * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd | --=20 2.11.0