From nobody Tue Feb 10 12:42:08 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505415947725428.4362705917432; Thu, 14 Sep 2017 12:05:47 -0700 (PDT) Received: from localhost ([::1]:49580 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsZSM-0008GO-RS for importer@patchew.org; Thu, 14 Sep 2017 15:05:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37771) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsZNm-0003cI-45 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 15:01:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsZNk-0006Jx-Lb for qemu-devel@nongnu.org; Thu, 14 Sep 2017 15:01:02 -0400 Received: from mail-pg0-x22b.google.com ([2607:f8b0:400e:c05::22b]:54968) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dsZNk-0006JS-Dy for qemu-devel@nongnu.org; Thu, 14 Sep 2017 15:01:00 -0400 Received: by mail-pg0-x22b.google.com with SMTP id c137so150373pga.11 for ; Thu, 14 Sep 2017 12:01:00 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net. [97.126.103.167]) by smtp.gmail.com with ESMTPSA id m24sm32941520pfj.28.2017.09.14.12.00.57 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Sep 2017 12:00:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=4rZyKs/GWZfs3YCKshTEwyDwjwjtnOjAo7MVORuE57k=; b=aWtErZhg5qfvA6Xz/MQqlmGdMjmzZ3tK0zPdBbYQSKIp1NFpvRz4cr396ThXVct6ku /wk4ZsTEfK1+K+3xrxiCn2RONj74oi2sHOLK/TSqWYjD/VSam3Jp7AO18zZiudMqiaIz G4fMuRszb6HP514qf2aTzB4kGnTpU+CwnashE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=4rZyKs/GWZfs3YCKshTEwyDwjwjtnOjAo7MVORuE57k=; b=PVC7EHQQRzK75E5t1nRLppGpF5Jq00DnHvlqrgJjszdlaIlWLL/MXV5ZLgul4mzRFc SM1VkoUbA0LddXdDTdVlyFwQt2aDYvWAkYVG2QVfD3eZiltxdvQgTjezZjfhOJT0f4sv apBl35xhGxbO989focvoOHMFfvcgLCI90ij87yWf7S1qnJcRRRTcQqslgfFm1Wr7WUXn hlrDOADiA12o4JVvp4wpt28KawZs5VYxPnkSI9v2APVXEYLnYea0fl0KwJIkeDgyh4aO aImfG2yL/ztxPKVUR1UuynDu2XkcFo1Y/etSN80Ec8gdCda6c+o5YuA0UOLqIx1jCCJs pjGA== X-Gm-Message-State: AHPjjUgvq0slDgxSEX6APlu6R20qOSWTPsfOWuravDIemSuzS0BoyTAT HAcxJbHOO0ftVl7ZyTd8CQ== X-Google-Smtp-Source: AOwi7QCl2awPLe1+mZUSZ5EdYcO0e6T7BXmTSrOpQcXH4ql5OwLI2/2WnVXAfxDKkTUL/dgVFusrBg== X-Received: by 10.84.253.145 with SMTP id a17mr3359784plm.116.1505415659017; Thu, 14 Sep 2017 12:00:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 12:00:52 -0700 Message-Id: <20170914190053.27625-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170914190053.27625-1-richard.henderson@linaro.org> References: <20170914190053.27625-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22b Subject: [Qemu-devel] [PATCH 3/4] tcg/sparc: Fully convert tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.inc.c | 239 ++++++++++++++++++++++++++---------------= ---- 1 file changed, 137 insertions(+), 102 deletions(-) diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 1da4debbaf..bc673bd8c6 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -1632,112 +1632,147 @@ static void tcg_out_op(TCGContext *s, TCGOpcode o= pc, } } =20 -static const TCGTargetOpDef sparc_op_defs[] =3D { - { INDEX_op_exit_tb, { } }, - { INDEX_op_goto_tb, { } }, - { INDEX_op_br, { } }, - { INDEX_op_goto_ptr, { "r" } }, - - { INDEX_op_ld8u_i32, { "r", "r" } }, - { INDEX_op_ld8s_i32, { "r", "r" } }, - { INDEX_op_ld16u_i32, { "r", "r" } }, - { INDEX_op_ld16s_i32, { "r", "r" } }, - { INDEX_op_ld_i32, { "r", "r" } }, - { INDEX_op_st8_i32, { "rZ", "r" } }, - { INDEX_op_st16_i32, { "rZ", "r" } }, - { INDEX_op_st_i32, { "rZ", "r" } }, - - { INDEX_op_add_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_mul_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_div_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_divu_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_sub_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_and_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_andc_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_or_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_orc_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_xor_i32, { "r", "rZ", "rJ" } }, - - { INDEX_op_shl_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_shr_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_sar_i32, { "r", "rZ", "rJ" } }, - - { INDEX_op_neg_i32, { "r", "rJ" } }, - { INDEX_op_not_i32, { "r", "rJ" } }, - - { INDEX_op_brcond_i32, { "rZ", "rJ" } }, - { INDEX_op_setcond_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_movcond_i32, { "r", "rZ", "rJ", "rI", "0" } }, - - { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } }, - { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } }, - { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rJ" } }, - { INDEX_op_muls2_i32, { "r", "r", "rZ", "rJ" } }, - - { INDEX_op_ld8u_i64, { "R", "r" } }, - { INDEX_op_ld8s_i64, { "R", "r" } }, - { INDEX_op_ld16u_i64, { "R", "r" } }, - { INDEX_op_ld16s_i64, { "R", "r" } }, - { INDEX_op_ld32u_i64, { "R", "r" } }, - { INDEX_op_ld32s_i64, { "R", "r" } }, - { INDEX_op_ld_i64, { "R", "r" } }, - { INDEX_op_st8_i64, { "RZ", "r" } }, - { INDEX_op_st16_i64, { "RZ", "r" } }, - { INDEX_op_st32_i64, { "RZ", "r" } }, - { INDEX_op_st_i64, { "RZ", "r" } }, - - { INDEX_op_add_i64, { "R", "RZ", "RJ" } }, - { INDEX_op_mul_i64, { "R", "RZ", "RJ" } }, - { INDEX_op_div_i64, { "R", "RZ", "RJ" } }, - { INDEX_op_divu_i64, { "R", "RZ", "RJ" } }, - { INDEX_op_sub_i64, { "R", "RZ", "RJ" } }, - { INDEX_op_and_i64, { "R", "RZ", "RJ" } }, - { INDEX_op_andc_i64, { "R", "RZ", "RJ" } }, - { INDEX_op_or_i64, { "R", "RZ", "RJ" } }, - { INDEX_op_orc_i64, { "R", "RZ", "RJ" } }, - { INDEX_op_xor_i64, { "R", "RZ", "RJ" } }, - - { INDEX_op_shl_i64, { "R", "RZ", "RJ" } }, - { INDEX_op_shr_i64, { "R", "RZ", "RJ" } }, - { INDEX_op_sar_i64, { "R", "RZ", "RJ" } }, - - { INDEX_op_neg_i64, { "R", "RJ" } }, - { INDEX_op_not_i64, { "R", "RJ" } }, - - { INDEX_op_ext32s_i64, { "R", "R" } }, - { INDEX_op_ext32u_i64, { "R", "R" } }, - { INDEX_op_ext_i32_i64, { "R", "r" } }, - { INDEX_op_extu_i32_i64, { "R", "r" } }, - { INDEX_op_extrl_i64_i32, { "r", "R" } }, - { INDEX_op_extrh_i64_i32, { "r", "R" } }, - - { INDEX_op_brcond_i64, { "RZ", "RJ" } }, - { INDEX_op_setcond_i64, { "R", "RZ", "RJ" } }, - { INDEX_op_movcond_i64, { "R", "RZ", "RJ", "RI", "0" } }, - - { INDEX_op_add2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } }, - { INDEX_op_sub2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } }, - { INDEX_op_muluh_i64, { "R", "RZ", "RZ" } }, - - { INDEX_op_qemu_ld_i32, { "r", "A" } }, - { INDEX_op_qemu_ld_i64, { "R", "A" } }, - { INDEX_op_qemu_st_i32, { "sZ", "A" } }, - { INDEX_op_qemu_st_i64, { "SZ", "A" } }, - - { INDEX_op_mb, { } }, - { -1 }, -}; - static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - int i, n =3D ARRAY_SIZE(sparc_op_defs); + static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; + static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; + static const TCGTargetOpDef R_r =3D { .args_ct_str =3D { "R", "r" } }; + static const TCGTargetOpDef r_R =3D { .args_ct_str =3D { "r", "R" } }; + static const TCGTargetOpDef R_R =3D { .args_ct_str =3D { "R", "R" } }; + static const TCGTargetOpDef r_A =3D { .args_ct_str =3D { "r", "A" } }; + static const TCGTargetOpDef R_A =3D { .args_ct_str =3D { "R", "A" } }; + static const TCGTargetOpDef rZ_r =3D { .args_ct_str =3D { "rZ", "r" } = }; + static const TCGTargetOpDef RZ_r =3D { .args_ct_str =3D { "RZ", "r" } = }; + static const TCGTargetOpDef sZ_A =3D { .args_ct_str =3D { "sZ", "A" } = }; + static const TCGTargetOpDef SZ_A =3D { .args_ct_str =3D { "SZ", "A" } = }; + static const TCGTargetOpDef rZ_rJ =3D { .args_ct_str =3D { "rZ", "rJ" = } }; + static const TCGTargetOpDef RZ_RJ =3D { .args_ct_str =3D { "RZ", "RJ" = } }; + static const TCGTargetOpDef R_R_R =3D { .args_ct_str =3D { "R", "R", "= R" } }; + static const TCGTargetOpDef r_rZ_rJ + =3D { .args_ct_str =3D { "r", "rZ", "rJ" } }; + static const TCGTargetOpDef R_RZ_RJ + =3D { .args_ct_str =3D { "R", "RZ", "RJ" } }; + static const TCGTargetOpDef r_r_rZ_rJ + =3D { .args_ct_str =3D { "r", "r", "rZ", "rJ" } }; + static const TCGTargetOpDef movc_32 + =3D { .args_ct_str =3D { "r", "rZ", "rJ", "rI", "0" } }; + static const TCGTargetOpDef movc_64 + =3D { .args_ct_str =3D { "R", "RZ", "RJ", "RI", "0" } }; + static const TCGTargetOpDef add2_32 + =3D { .args_ct_str =3D { "r", "r", "rZ", "rZ", "rJ", "rJ" } }; + static const TCGTargetOpDef add2_64 + =3D { .args_ct_str =3D { "R", "R", "RZ", "RZ", "RJ", "RI" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; =20 - for (i =3D 0; i < n; ++i) { - if (sparc_op_defs[i].op =3D=3D op) { - return &sparc_op_defs[i]; - } + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_neg_i32: + case INDEX_op_not_i32: + return &r_r; + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + return &rZ_r; + + case INDEX_op_add_i32: + case INDEX_op_mul_i32: + case INDEX_op_div_i32: + case INDEX_op_divu_i32: + case INDEX_op_sub_i32: + case INDEX_op_and_i32: + case INDEX_op_andc_i32: + case INDEX_op_or_i32: + case INDEX_op_orc_i32: + case INDEX_op_xor_i32: + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_setcond_i32: + return &r_rZ_rJ; + + case INDEX_op_brcond_i32: + return &rZ_rJ; + case INDEX_op_movcond_i32: + return &movc_32; + case INDEX_op_add2_i32: + case INDEX_op_sub2_i32: + return &add2_32; + case INDEX_op_mulu2_i32: + case INDEX_op_muls2_i32: + return &r_r_rZ_rJ; + + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + return &R_r; + + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return &RZ_r; + + case INDEX_op_add_i64: + case INDEX_op_mul_i64: + case INDEX_op_div_i64: + case INDEX_op_divu_i64: + case INDEX_op_sub_i64: + case INDEX_op_and_i64: + case INDEX_op_andc_i64: + case INDEX_op_or_i64: + case INDEX_op_orc_i64: + case INDEX_op_xor_i64: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_setcond_i64: + return &R_RZ_RJ; + + case INDEX_op_neg_i64: + case INDEX_op_not_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + return &R_R; + + case INDEX_op_extrl_i64_i32: + case INDEX_op_extrh_i64_i32: + return &r_R; + + case INDEX_op_brcond_i64: + return &RZ_RJ; + case INDEX_op_movcond_i64: + return &movc_64; + case INDEX_op_add2_i64: + case INDEX_op_sub2_i64: + return &add2_64; + case INDEX_op_muluh_i64: + return &R_R_R; + + case INDEX_op_qemu_ld_i32: + return &r_A; + case INDEX_op_qemu_ld_i64: + return &R_A; + case INDEX_op_qemu_st_i32: + return &sZ_A; + case INDEX_op_qemu_st_i64: + return &SZ_A; + + default: + return NULL; } - return NULL; } =20 static void tcg_target_init(TCGContext *s) --=20 2.13.5