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X-Received-From: 2607:f8b0:400c:c05::241 Subject: [Qemu-devel] [PATCH v4 13/14] hvf: refactor event injection code for hvf X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sergio Andres Gomez Del Real , pbonzini@redhat.com, stefanha@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch refactors the event-injection code for hvf by using the appropriate fields already provided by CPUX86State. At vmexit, it fills these fields so that hvf_inject_interrupts can just retrieve them without calling into hvf. Signed-off-by: Sergio Andres Gomez Del Real --- target/i386/cpu.c | 3 ++ target/i386/cpu.h | 1 + target/i386/hvf-all.c | 57 ++++++++++++++++++++++++++++++++---- target/i386/hvf-utils/vmcs.h | 3 ++ target/i386/hvf-utils/vmx.h | 8 ++++++ target/i386/hvf-utils/x86hvf.c | 65 ++++++++++++++++++++------------------= ---- target/i386/kvm.c | 2 -- 7 files changed, 98 insertions(+), 41 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2bf8c0ce0f..76bfcc23f3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3247,6 +3247,9 @@ static void x86_cpu_reset(CPUState *s) memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); =20 + env->interrupt_injected =3D -1; + env->exception_injected =3D -1; + env->nmi_injected =3D false; #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ apic_designate_bsp(cpu->apic_state, s->cpu_index =3D=3D 0); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 630a4c2c0a..81e3f511a6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1188,6 +1188,7 @@ typedef struct CPUX86State { int32_t interrupt_injected; uint8_t soft_interrupt; uint8_t has_error_code; + uint32_t ins_len; uint32_t sipi_vector; bool tsc_valid; int64_t tsc_khz; diff --git a/target/i386/hvf-all.c b/target/i386/hvf-all.c index e8466e6f47..105a63ad4f 100644 --- a/target/i386/hvf-all.c +++ b/target/i386/hvf-all.c @@ -589,6 +589,55 @@ void hvf_disable(int shouldDisable) hvf_disabled =3D shouldDisable; } =20 +static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idt= vec_info) +{ + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; + + env->exception_injected =3D -1; + env->interrupt_injected =3D -1; + env->nmi_injected =3D false; + if (idtvec_info & VMCS_IDT_VEC_VALID) { + switch (idtvec_info & VMCS_IDT_VEC_TYPE) { + case VMCS_IDT_VEC_HWINTR: + case VMCS_IDT_VEC_SWINTR: + env->interrupt_injected =3D idtvec_info & VMCS_IDT_VEC_VECNUM; + break; + case VMCS_IDT_VEC_NMI: + env->nmi_injected =3D true; + break; + case VMCS_IDT_VEC_HWEXCEPTION: + case VMCS_IDT_VEC_SWEXCEPTION: + env->exception_injected =3D idtvec_info & VMCS_IDT_VEC_VECNUM; + break; + case VMCS_IDT_VEC_PRIV_SWEXCEPTION: + default: + abort(); + } + if ((idtvec_info & VMCS_IDT_VEC_TYPE) =3D=3D VMCS_IDT_VEC_SWEXCEPT= ION || + (idtvec_info & VMCS_IDT_VEC_TYPE) =3D=3D VMCS_IDT_VEC_SWINTR) { + env->ins_len =3D ins_len; + } + if (idtvec_info & VMCS_INTR_DEL_ERRCODE) { + env->has_error_code =3D true; + env->error_code =3D rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_ERRO= R); + } + } + if ((rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) & + VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) { + env->hflags2 |=3D HF2_NMI_MASK; + } else { + env->hflags2 &=3D ~HF2_NMI_MASK; + } + if (rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) & + (VMCS_INTERRUPTIBILITY_STI_BLOCKING | + VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) { + env->hflags |=3D HF_INHIBIT_IRQ_MASK; + } else { + env->hflags &=3D ~HF_INHIBIT_IRQ_MASK; + } +} + int hvf_vcpu_exec(CPUState *cpu) { X86CPU *x86_cpu =3D X86_CPU(cpu); @@ -608,11 +657,6 @@ int hvf_vcpu_exec(CPUState *cpu) cpu->vcpu_dirty =3D false; } =20 - env->hvf_emul->interruptable =3D - !(rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) & - (VMCS_INTERRUPTIBILITY_STI_BLOCKING | - VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)); - hvf_inject_interrupts(cpu); vmx_update_tpr(cpu); =20 @@ -631,7 +675,10 @@ int hvf_vcpu_exec(CPUState *cpu) uint64_t exit_qual =3D rvmcs(cpu->hvf_fd, VMCS_EXIT_QUALIFICATION); uint32_t ins_len =3D (uint32_t)rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH); + uint64_t idtvec_info =3D rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INF= O); + + hvf_store_events(cpu, ins_len, idtvec_info); rip =3D rreg(cpu->hvf_fd, HV_X86_RIP); RFLAGS(env) =3D rreg(cpu->hvf_fd, HV_X86_RFLAGS); env->eflags =3D RFLAGS(env); diff --git a/target/i386/hvf-utils/vmcs.h b/target/i386/hvf-utils/vmcs.h index c410dcfaaa..0fae73dce5 100644 --- a/target/i386/hvf-utils/vmcs.h +++ b/target/i386/hvf-utils/vmcs.h @@ -299,6 +299,7 @@ /* * VMCS IDT-Vectoring information fields */ +#define VMCS_IDT_VEC_VECNUM 0xFF #define VMCS_IDT_VEC_VALID (1U << 31) #define VMCS_IDT_VEC_TYPE 0x700 #define VMCS_IDT_VEC_ERRCODE_VALID (1U << 11) @@ -306,6 +307,8 @@ #define VMCS_IDT_VEC_NMI (2 << 8) #define VMCS_IDT_VEC_HWEXCEPTION (3 << 8) #define VMCS_IDT_VEC_SWINTR (4 << 8) +#define VMCS_IDT_VEC_PRIV_SWEXCEPTION (5 << 8) +#define VMCS_IDT_VEC_SWEXCEPTION (6 << 8) =20 /* * VMCS Guest interruptibility field diff --git a/target/i386/hvf-utils/vmx.h b/target/i386/hvf-utils/vmx.h index 44a5c6d554..102075d0d4 100644 --- a/target/i386/hvf-utils/vmx.h +++ b/target/i386/hvf-utils/vmx.h @@ -181,6 +181,10 @@ static inline void macvm_set_rip(CPUState *cpu, uint64= _t rip) =20 static inline void vmx_clear_nmi_blocking(CPUState *cpu) { + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; + + env->hflags2 &=3D ~HF2_NMI_MASK; uint32_t gi =3D (uint32_t) rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBIL= ITY); gi &=3D ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING; wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi); @@ -188,6 +192,10 @@ static inline void vmx_clear_nmi_blocking(CPUState *cp= u) =20 static inline void vmx_set_nmi_blocking(CPUState *cpu) { + X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; + + env->hflags2 |=3D HF2_NMI_MASK; uint32_t gi =3D (uint32_t)rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILI= TY); gi |=3D VMCS_INTERRUPTIBILITY_NMI_BLOCKING; wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi); diff --git a/target/i386/hvf-utils/x86hvf.c b/target/i386/hvf-utils/x86hvf.c index dd0710d056..83eb3be065 100644 --- a/target/i386/hvf-utils/x86hvf.c +++ b/target/i386/hvf-utils/x86hvf.c @@ -356,50 +356,47 @@ void vmx_clear_int_window_exiting(CPUState *cpu) =20 void hvf_inject_interrupts(CPUState *cpu_state) { - int allow_nmi =3D !(rvmcs(cpu_state->hvf_fd, VMCS_GUEST_INTERRUPTIBILI= TY) & - VMCS_INTERRUPTIBILITY_NMI_BLOCKING); X86CPU *x86cpu =3D X86_CPU(cpu_state); CPUX86State *env =3D &x86cpu->env; =20 - uint64_t idt_info =3D rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_INFO= ); + uint8_t vector; + uint64_t intr_type; + bool have_event =3D true; + if (env->interrupt_injected !=3D -1) { + vector =3D env->interrupt_injected; + intr_type =3D VMCS_INTR_T_SWINTR; + } else if (env->exception_injected !=3D -1) { + vector =3D env->exception_injected; + if (vector =3D=3D EXCP03_INT3 || vector =3D=3D EXCP04_INTO) { + intr_type =3D VMCS_INTR_T_SWEXCEPTION; + } else { + intr_type =3D VMCS_INTR_T_HWEXCEPTION; + } + } else if (env->nmi_injected) { + vector =3D NMI_VEC; + intr_type =3D VMCS_INTR_T_NMI; + } else { + have_event =3D false; + } + uint64_t info =3D 0; - =20 - if (idt_info & VMCS_IDT_VEC_VALID) { - uint8_t vector =3D idt_info & 0xff; - uint64_t intr_type =3D idt_info & VMCS_INTR_T_MASK; - info =3D idt_info; - =20 + if (have_event) { + info =3D vector | intr_type | VMCS_INTR_VALID; uint64_t reason =3D rvmcs(cpu_state->hvf_fd, VMCS_EXIT_REASON); - if (intr_type =3D=3D VMCS_INTR_T_NMI && reason !=3D EXIT_REASON_TA= SK_SWITCH) { - allow_nmi =3D 1; + if (env->nmi_injected && reason !=3D EXIT_REASON_TASK_SWITCH) { vmx_clear_nmi_blocking(cpu_state); } - =20 - if ((allow_nmi || intr_type !=3D VMCS_INTR_T_NMI)) { + + if (!(env->hflags2 & HF2_NMI_MASK) || intr_type !=3D VMCS_INTR_T_N= MI) { info &=3D ~(1 << 12); /* clear undefined bit */ if (intr_type =3D=3D VMCS_INTR_T_SWINTR || - intr_type =3D=3D VMCS_INTR_T_PRIV_SWEXCEPTION || intr_type =3D=3D VMCS_INTR_T_SWEXCEPTION) { - uint64_t ins_len =3D rvmcs(cpu_state->hvf_fd, - VMCS_EXIT_INSTRUCTION_LENGTH); - wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len); - } - if (vector =3D=3D EXCEPTION_BP || vector =3D=3D EXCEPTION_OF) { - /* - * VT-x requires #BP and #OF to be injected as software - * exceptions. - */ - info &=3D ~VMCS_INTR_T_MASK; - info |=3D VMCS_INTR_T_SWEXCEPTION; - uint64_t ins_len =3D rvmcs(cpu_state->hvf_fd, - VMCS_EXIT_INSTRUCTION_LENGTH); - wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len); + wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, env->ins_= len); } =20 - uint64_t err =3D 0; - if (idt_info & VMCS_INTR_DEL_ERRCODE) { - err =3D rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_ERROR); - wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_EXCEPTION_ERROR, err); + if (env->has_error_code) { + wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_EXCEPTION_ERROR, + env->error_code); } /*printf("reinject %lx err %d\n", info, err);*/ wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info); @@ -407,7 +404,7 @@ void hvf_inject_interrupts(CPUState *cpu_state) } =20 if (cpu_state->interrupt_request & CPU_INTERRUPT_NMI) { - if (allow_nmi && !(info & VMCS_INTR_VALID)) { + if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) { cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_NMI; info =3D VMCS_INTR_VALID | VMCS_INTR_T_NMI | NMI_VEC; wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info); @@ -416,7 +413,7 @@ void hvf_inject_interrupts(CPUState *cpu_state) } } =20 - if (env->hvf_emul->interruptable && + if (!(env->hflags & HF_INHIBIT_IRQ_MASK) && (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) && (EFLAGS(env) & IF_MASK) && !(info & VMCS_INTR_VALID)) { int line =3D cpu_get_pic_interrupt(&x86cpu->env); diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 6db7783edc..a695b8cd4e 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1030,8 +1030,6 @@ void kvm_arch_reset_vcpu(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; =20 - env->exception_injected =3D -1; - env->interrupt_injected =3D -1; env->xcr0 =3D 1; if (kvm_irqchip_in_kernel()) { env->mp_state =3D cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE : --=20 2.14.1