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[97.126.103.167]) by smtp.gmail.com with ESMTPSA id b22sm20382140pfh.175.2017.09.12.09.25.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 09:25:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aQ1XEDQsc9UTqPTlSfnW1xqLW4406WUrga5mz4xOARE=; b=OGpsMp9zZrAOm6qRqALCWvQyYUZrREH3kRaiCPBEwdY6pdVh4TOM4KXhKY55FVOjH3 pwiCWEcsSCoQDwqiYUsOoGBXFBxRsAlzQNZFlfCEBiE1Zw5GA37kxn2xnnuLSB4WLaJa 4eG4QPwE+Dyj1W0xiM/wDVmsjkwNCEK1xFy+g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aQ1XEDQsc9UTqPTlSfnW1xqLW4406WUrga5mz4xOARE=; b=d1Wrzny1fDiByVbYO5PQ8lK75ocatarw4ElAC5V/Mkkvggny/kglbWUCKwtoBJayz/ KMX+wJh+ubosvAUHbTehXVvV8kt0tvMga7WIzO2Xy/Iv3//RBErQIanPjNPZCwtZ6ALl wJRgeG9i0vxgix/uNLDURQVvcanwGZenyKLQOTd20xzBclD5wyxvAdP4TP2Gk/GhqMpf iSK0rEFR9f0Hmi7lNrntGgqy/TLOHkSfttUaSeQ8Nn9/LVP0/ONJcQe6xSonivyx2VfK Nm8jqMtmKXgIiFoEh70UK9Y28uO5GSx2zxuTzf7rRxCuWzWe6TkfBWr6tdvCNQgc7+j/ Blow== X-Gm-Message-State: AHPjjUgbFtMvp03+BbYLL+gkXc7IWGqKtE7r0QNRzmHPW4xLFbKdUfc9 fp/fhVVPXHiiGGNgogr9hw== X-Google-Smtp-Source: ADKCNb7My5r3x2nfMYppPtOPr/uqcwQIFa4KSdg6+3a26uqkgB0Jq2j3wYk38NFH7M2NTrsqmkqVkA== X-Received: by 10.99.62.142 with SMTP id l136mr15273941pga.130.1505233517540; Tue, 12 Sep 2017 09:25:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Sep 2017 09:24:58 -0700 Message-Id: <20170912162513.21694-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170912162513.21694-1-richard.henderson@linaro.org> References: <20170912162513.21694-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::231 Subject: [Qemu-devel] [PATCH v2 01/16] tcg: Add expanders for out-of-line vector helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a minimum extraction from a full generic vector patchset in order to support simultaneous development in target/arm. Signed-off-by: Richard Henderson --- Makefile.target | 5 +-- tcg/tcg-gvec-desc.h | 49 ++++++++++++++++++++++++++++ tcg/tcg-op-gvec.h | 43 +++++++++++++++++++++++++ tcg/tcg-op-gvec.c | 93 +++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 188 insertions(+), 2 deletions(-) create mode 100644 tcg/tcg-gvec-desc.h create mode 100644 tcg/tcg-op-gvec.h create mode 100644 tcg/tcg-op-gvec.c diff --git a/Makefile.target b/Makefile.target index 7f42c45db8..e647b6e2cb 100644 --- a/Makefile.target +++ b/Makefile.target @@ -93,8 +93,9 @@ all: $(PROGS) stap # cpu emulator library obj-y +=3D exec.o obj-y +=3D accel/ -obj-$(CONFIG_TCG) +=3D tcg/tcg.o tcg/tcg-op.o tcg/optimize.o -obj-$(CONFIG_TCG) +=3D tcg/tcg-common.o tcg/tcg-runtime.o +obj-$(CONFIG_TCG) +=3D tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-gvec.o +obj-$(CONFIG_TCG) +=3D tcg/optimize.o tcg/tcg-common.o +obj-$(CONFIG_TCG) +=3D tcg/tcg-runtime.o obj-$(CONFIG_TCG_INTERPRETER) +=3D tcg/tci.o obj-$(CONFIG_TCG_INTERPRETER) +=3D disas/tci.o obj-y +=3D fpu/softfloat.o diff --git a/tcg/tcg-gvec-desc.h b/tcg/tcg-gvec-desc.h new file mode 100644 index 0000000000..8ba9a8168d --- /dev/null +++ b/tcg/tcg-gvec-desc.h @@ -0,0 +1,49 @@ +/* + * Generic vector operation descriptor + * + * Copyright (c) 2017 Linaro + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vector= s. */ +#define SIMD_OPRSZ_SHIFT 0 +#define SIMD_OPRSZ_BITS 5 + +#define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS) +#define SIMD_MAXSZ_BITS 5 + +#define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS) +#define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT) + +/* Create a descriptor from components. */ +uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data); + +/* Extract the operation size from a descriptor. */ +static inline intptr_t simd_oprsz(uint32_t desc) +{ + return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8; +} + +/* Extract the max vector size from a descriptor. */ +static inline intptr_t simd_maxsz(uint32_t desc) +{ + return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8; +} + +/* Extract the operation-specific data from a descriptor. */ +static inline int32_t simd_data(uint32_t desc) +{ + return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS); +} diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h new file mode 100644 index 0000000000..affb7c2e89 --- /dev/null +++ b/tcg/tcg-op-gvec.h @@ -0,0 +1,43 @@ +/* + * Generic vector operation expansion + * + * Copyright (c) 2017 Linaro + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* + * "Generic" vectors. All operands are given as offsets from ENV, + * and therefore cannot also be allocated via tcg_global_mem_new_*. + * OPRSZ is the byte size of the vector upon which the operation is perfor= med. + * MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleare= d. + * + * All sizes must be 8 or any multiple of 16. + * When OPRSZ is 8, the alignment may be 8, otherwise must be 16. + * Operands may completely, but not partially, overlap. + */ + +/* Expand a call to a gvec-stype helper, with pointers to three vector + operands, and a descriptor (see tcg-gvec-desc.h). */ +typedef void (gen_helper_gvec_3)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz, uint32_t data, + gen_helper_gvec_3 *fn); + +/* Similarly, passing an extra pointer (e.g. env or float_status). */ +typedef void (gen_helper_gvec_3_ptr)(TCGv_ptr, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, + TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, + uint32_t data, gen_helper_gvec_3_ptr *fn); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c new file mode 100644 index 0000000000..f48415020d --- /dev/null +++ b/tcg/tcg-op-gvec.c @@ -0,0 +1,93 @@ +/* + * Generic vector operation expansion + * + * Copyright (c) 2017 Linaro + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "tcg.h" +#include "tcg-op.h" +#include "tcg-op-gvec.h" +#include "tcg-gvec-desc.h" + + +/* Create a descriptor from components. */ +uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data) +{ + uint32_t desc =3D 0; + + assert(oprsz % 8 =3D=3D 0 && oprsz <=3D (8 << SIMD_OPRSZ_BITS)); + assert(maxsz % 8 =3D=3D 0 && maxsz <=3D (8 << SIMD_MAXSZ_BITS)); + assert(data =3D=3D sextract32(data, 0, SIMD_DATA_BITS)); + + oprsz =3D (oprsz / 8) - 1; + maxsz =3D (maxsz / 8) - 1; + desc =3D deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz); + desc =3D deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz); + desc =3D deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data); + + return desc; +} + +/* Generate a call to a gvec-style helper with three vector operands. */ +void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz, uint32_t data, + gen_helper_gvec_3 *fn) +{ + TCGv_ptr a0, a1, a2; + TCGv_i32 desc =3D tcg_const_i32(simd_desc(oprsz, maxsz, data)); + + a0 =3D tcg_temp_new_ptr(); + a1 =3D tcg_temp_new_ptr(); + a2 =3D tcg_temp_new_ptr(); + + tcg_gen_addi_ptr(a0, tcg_ctx.tcg_env, dofs); + tcg_gen_addi_ptr(a1, tcg_ctx.tcg_env, aofs); + tcg_gen_addi_ptr(a2, tcg_ctx.tcg_env, bofs); + + fn(a0, a1, a2, desc); + + tcg_temp_free_ptr(a0); + tcg_temp_free_ptr(a1); + tcg_temp_free_ptr(a2); + tcg_temp_free_i32(desc); +} + +/* Generate a call to a gvec-style helper with three vector operands + and an extra pointer operand. */ +void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, + TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, + uint32_t data, gen_helper_gvec_3_ptr *fn) +{ + TCGv_ptr a0, a1, a2; + TCGv_i32 desc =3D tcg_const_i32(simd_desc(oprsz, maxsz, data)); + + a0 =3D tcg_temp_new_ptr(); + a1 =3D tcg_temp_new_ptr(); + a2 =3D tcg_temp_new_ptr(); + + tcg_gen_addi_ptr(a0, tcg_ctx.tcg_env, dofs); + tcg_gen_addi_ptr(a1, tcg_ctx.tcg_env, aofs); + tcg_gen_addi_ptr(a2, tcg_ctx.tcg_env, bofs); + + fn(a0, a1, a2, ptr, desc); + + tcg_temp_free_ptr(a0); + tcg_temp_free_ptr(a1); + tcg_temp_free_ptr(a2); + tcg_temp_free_i32(desc); +} --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505233632437773.9097727351049; Tue, 12 Sep 2017 09:27:12 -0700 (PDT) Received: from localhost ([::1]:36890 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro1n-0002yN-34 for importer@patchew.org; Tue, 12 Sep 2017 12:27:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37799) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro02-0001dG-47 for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dro00-0006yL-GF for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:22 -0400 Received: from mail-pg0-x232.google.com ([2607:f8b0:400e:c05::232]:35937) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dro00-0006xy-AX for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:20 -0400 Received: by mail-pg0-x232.google.com with SMTP id i130so14869212pgc.3 for ; Tue, 12 Sep 2017 09:25:20 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net. [97.126.103.167]) by smtp.gmail.com with ESMTPSA id b22sm20382140pfh.175.2017.09.12.09.25.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 09:25:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oWluCzfErekNM0P6PesQBlMo2sMHFtlmX5OXtZiRM/Y=; b=FnCOKfa6JKVEQp9YtXnfopTVVX8J5nxFMmylmcw1dY/TXzuiJb8vLkeYeKaQ46YZbN VdxbjOkBymH5wNcYcafHOjObZwTmB8chf42txkP7wdhop7Po3QppoSIDyVt4xK2YczBc pKx04l6P8yH+JIyZmsuyEw2bpHfuPizM7plMk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oWluCzfErekNM0P6PesQBlMo2sMHFtlmX5OXtZiRM/Y=; b=PXX6Ypd5dlwvd9gl8VCCOmLU4QdniFnSvLRxTHbXg6YgpjijGQt7hDVOZn7Pc44T3s hGGWHv9hwzieEf+A/2e/iTbsC017A+p+rIOQeDqr/LX2J1hY3FWd+yceXHimNEo3MZw2 VxA1gaZNBfjw6uJsxK/rN9jgNFuuHPqupK/rcqWHpM0P3A9kHQFtiDkGegKImd4X8xcG ysEZMtD8GiU8m7BKAvrmQMdYlxBDt4aWQkZCn5xKoBScIDC5XbzIRN5aFDwHNVyOQjY8 k22Q+V1NFQSm7kHrf5vWYh+P4aOUnt81QOXP5o8jrpoTgLu+YU/oYliIZgDMdTUUEbn7 ktxw== X-Gm-Message-State: AHPjjUiJ+bNO9xWrhy9HECjQL52Ifv/t9NKi5mk+I0FICG5IlzgmqtH0 tnEC3c3Exe3Dx41cPxHSGA== X-Google-Smtp-Source: ADKCNb4c8VjliWVRDI/6g8/A8wzB57W8vjutty1JKOjkOYqBQlC+anx04Td7bfk8r5RacQMylO+qoA== X-Received: by 10.99.121.135 with SMTP id u129mr15188409pgc.250.1505233519009; Tue, 12 Sep 2017 09:25:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Sep 2017 09:24:59 -0700 Message-Id: <20170912162513.21694-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170912162513.21694-1-richard.henderson@linaro.org> References: <20170912162513.21694-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::232 Subject: [Qemu-devel] [PATCH v2 02/16] tcg: Add types for host vectors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Nothing uses or enables them yet. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg.h | 5 +++++ tcg/tcg.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index ac94133870..f56ddac31d 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -256,6 +256,11 @@ typedef struct TCGPool { typedef enum TCGType { TCG_TYPE_I32, TCG_TYPE_I64, + + TCG_TYPE_V64, + TCG_TYPE_V128, + TCG_TYPE_V256, + TCG_TYPE_COUNT, /* number of different types */ =20 /* An alias for the size of the host register. */ diff --git a/tcg/tcg.c b/tcg/tcg.c index fd8a3dfe93..bc65d01618 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -116,7 +116,7 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, static bool tcg_out_ldst_finalize(TCGContext *s); #endif =20 -static TCGRegSet tcg_target_available_regs[2]; +static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; static TCGRegSet tcg_target_call_clobber_regs; =20 #if TCG_TARGET_INSN_UNIT_SIZE =3D=3D 1 --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505233708050469.64383058550436; Tue, 12 Sep 2017 09:28:28 -0700 (PDT) Received: from localhost ([::1]:36893 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro31-0004NX-58 for importer@patchew.org; Tue, 12 Sep 2017 12:28:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37841) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro03-0001eZ-GY for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dro01-0006zX-V2 for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:23 -0400 Received: from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:34139) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dro01-0006z1-OI for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:21 -0400 Received: by mail-pf0-x22a.google.com with SMTP id e1so19440286pfk.1 for ; Tue, 12 Sep 2017 09:25:21 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PATCH v2 03/16] tcg: Add operations for host vectors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Nothing uses or implements them yet. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg-opc.h | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ tcg/tcg.h | 24 ++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 956fb1e9f3..edfdbf8798 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -206,6 +206,95 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, =20 #undef TLADDR_ARGS #undef DATA64_ARGS + +/* Host integer vector operations. */ +/* These opcodes are required whenever the base vector size is enabled. */ + +DEF(mov_v64, 1, 1, 0, TCG_OPF_NOT_PRESENT) +DEF(mov_v128, 1, 1, 0, TCG_OPF_NOT_PRESENT) +DEF(mov_v256, 1, 1, 0, TCG_OPF_NOT_PRESENT) + +DEF(movi_v64, 1, 0, 1, TCG_OPF_NOT_PRESENT) +DEF(movi_v128, 1, 0, 1, TCG_OPF_NOT_PRESENT) +DEF(movi_v256, 1, 0, 1, TCG_OPF_NOT_PRESENT) + +DEF(ld_v64, 1, 1, 1, IMPL(TCG_TARGET_HAS_v64)) +DEF(ld_v128, 1, 1, 1, IMPL(TCG_TARGET_HAS_v128)) +DEF(ld_v256, 1, 1, 1, IMPL(TCG_TARGET_HAS_v256)) + +DEF(st_v64, 0, 2, 1, IMPL(TCG_TARGET_HAS_v64)) +DEF(st_v128, 0, 2, 1, IMPL(TCG_TARGET_HAS_v128)) +DEF(st_v256, 0, 2, 1, IMPL(TCG_TARGET_HAS_v256)) + +DEF(and_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(and_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(and_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +DEF(or_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(or_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(or_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +DEF(xor_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(xor_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(xor_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +DEF(add8_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(add16_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(add32_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) + +DEF(add8_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(add16_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(add32_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(add64_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) + +DEF(add8_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(add16_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(add32_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(add64_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +DEF(sub8_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(sub16_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) +DEF(sub32_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_v64)) + +DEF(sub8_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(sub16_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(sub32_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) +DEF(sub64_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_v128)) + +DEF(sub8_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(sub16_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(sub32_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) +DEF(sub64_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_v256)) + +/* These opcodes are optional. + All element counts must be supported if any are. */ + +DEF(not_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v64)) +DEF(not_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v128)) +DEF(not_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_v256)) + +DEF(andc_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v64)) +DEF(andc_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v128)) +DEF(andc_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_v256)) + +DEF(orc_v64, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v64)) +DEF(orc_v128, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v128)) +DEF(orc_v256, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_v256)) + +DEF(neg8_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64)) +DEF(neg16_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64)) +DEF(neg32_v64, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v64)) + +DEF(neg8_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) +DEF(neg16_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) +DEF(neg32_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) +DEF(neg64_v128, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v128)) + +DEF(neg8_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) +DEF(neg16_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) +DEF(neg32_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) +DEF(neg64_v256, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_v256)) + #undef IMPL #undef IMPL64 #undef DEF diff --git a/tcg/tcg.h b/tcg/tcg.h index f56ddac31d..69b1fdf457 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -166,6 +166,30 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_rem_i64 0 #endif =20 +#ifndef TCG_TARGET_HAS_v64 +#define TCG_TARGET_HAS_v64 0 +#define TCG_TARGET_HAS_andc_v64 0 +#define TCG_TARGET_HAS_orc_v64 0 +#define TCG_TARGET_HAS_not_v64 0 +#define TCG_TARGET_HAS_neg_v64 0 +#endif + +#ifndef TCG_TARGET_HAS_v128 +#define TCG_TARGET_HAS_v128 0 +#define TCG_TARGET_HAS_andc_v128 0 +#define TCG_TARGET_HAS_orc_v128 0 +#define TCG_TARGET_HAS_not_v128 0 +#define TCG_TARGET_HAS_neg_v128 0 +#endif + +#ifndef TCG_TARGET_HAS_v256 +#define TCG_TARGET_HAS_v256 0 +#define TCG_TARGET_HAS_andc_v256 0 +#define TCG_TARGET_HAS_orc_v256 0 +#define TCG_TARGET_HAS_not_v256 0 +#define TCG_TARGET_HAS_neg_v256 0 +#endif + /* For 32-bit targets, some sort of unsigned widening multiply is required= . */ #if TCG_TARGET_REG_BITS =3D=3D 32 \ && !(defined(TCG_TARGET_HAS_mulu2_i32) \ --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c05::234 Subject: [Qemu-devel] [PATCH v2 04/16] tcg: Add tcg_op_supported X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg.h | 2 + tcg/tcg.c | 310 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 312 insertions(+) diff --git a/tcg/tcg.h b/tcg/tcg.h index 69b1fdf457..b81c67a754 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -961,6 +961,8 @@ do {\ #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T)) #endif =20 +bool tcg_op_supported(TCGOpcode op); + void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret, int nargs, TCGArg *args); =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index bc65d01618..9aea00d9b4 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -749,6 +749,316 @@ int tcg_check_temp_count(void) } #endif =20 +/* Return true if OP may appear in the opcode stream. + Test the runtime variable that controls each opcode. */ +bool tcg_op_supported(TCGOpcode op) +{ + switch (op) { + case INDEX_op_discard: + case INDEX_op_set_label: + case INDEX_op_call: + case INDEX_op_br: + case INDEX_op_mb: + case INDEX_op_insn_start: + case INDEX_op_exit_tb: + case INDEX_op_goto_tb: + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_ld_i64: + case INDEX_op_qemu_st_i64: + return true; + + case INDEX_op_goto_ptr: + return TCG_TARGET_HAS_goto_ptr; + + case INDEX_op_mov_i32: + case INDEX_op_movi_i32: + case INDEX_op_setcond_i32: + case INDEX_op_brcond_i32: + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_add_i32: + case INDEX_op_sub_i32: + case INDEX_op_mul_i32: + case INDEX_op_and_i32: + case INDEX_op_or_i32: + case INDEX_op_xor_i32: + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + return true; + + case INDEX_op_movcond_i32: + return TCG_TARGET_HAS_movcond_i32; + case INDEX_op_div_i32: + case INDEX_op_divu_i32: + return TCG_TARGET_HAS_div_i32; + case INDEX_op_rem_i32: + case INDEX_op_remu_i32: + return TCG_TARGET_HAS_rem_i32; + case INDEX_op_div2_i32: + case INDEX_op_divu2_i32: + return TCG_TARGET_HAS_div2_i32; + case INDEX_op_rotl_i32: + case INDEX_op_rotr_i32: + return TCG_TARGET_HAS_rot_i32; + case INDEX_op_deposit_i32: + return TCG_TARGET_HAS_deposit_i32; + case INDEX_op_extract_i32: + return TCG_TARGET_HAS_extract_i32; + case INDEX_op_sextract_i32: + return TCG_TARGET_HAS_sextract_i32; + case INDEX_op_add2_i32: + return TCG_TARGET_HAS_add2_i32; + case INDEX_op_sub2_i32: + return TCG_TARGET_HAS_sub2_i32; + case INDEX_op_mulu2_i32: + return TCG_TARGET_HAS_mulu2_i32; + case INDEX_op_muls2_i32: + return TCG_TARGET_HAS_muls2_i32; + case INDEX_op_muluh_i32: + return TCG_TARGET_HAS_muluh_i32; + case INDEX_op_mulsh_i32: + return TCG_TARGET_HAS_mulsh_i32; + case INDEX_op_ext8s_i32: + return TCG_TARGET_HAS_ext8s_i32; + case INDEX_op_ext16s_i32: + return TCG_TARGET_HAS_ext16s_i32; + case INDEX_op_ext8u_i32: + return TCG_TARGET_HAS_ext8u_i32; + case INDEX_op_ext16u_i32: + return TCG_TARGET_HAS_ext16u_i32; + case INDEX_op_bswap16_i32: + return TCG_TARGET_HAS_bswap16_i32; + case INDEX_op_bswap32_i32: + return TCG_TARGET_HAS_bswap32_i32; + case INDEX_op_not_i32: + return TCG_TARGET_HAS_not_i32; + case INDEX_op_neg_i32: + return TCG_TARGET_HAS_neg_i32; + case INDEX_op_andc_i32: + return TCG_TARGET_HAS_andc_i32; + case INDEX_op_orc_i32: + return TCG_TARGET_HAS_orc_i32; + case INDEX_op_eqv_i32: + return TCG_TARGET_HAS_eqv_i32; + case INDEX_op_nand_i32: + return TCG_TARGET_HAS_nand_i32; + case INDEX_op_nor_i32: + return TCG_TARGET_HAS_nor_i32; + case INDEX_op_clz_i32: + return TCG_TARGET_HAS_clz_i32; + case INDEX_op_ctz_i32: + return TCG_TARGET_HAS_ctz_i32; + case INDEX_op_ctpop_i32: + return TCG_TARGET_HAS_ctpop_i32; + + case INDEX_op_brcond2_i32: + case INDEX_op_setcond2_i32: + return TCG_TARGET_REG_BITS =3D=3D 32; + + case INDEX_op_mov_i64: + case INDEX_op_movi_i64: + case INDEX_op_setcond_i64: + case INDEX_op_brcond_i64: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + case INDEX_op_add_i64: + case INDEX_op_sub_i64: + case INDEX_op_mul_i64: + case INDEX_op_and_i64: + case INDEX_op_or_i64: + case INDEX_op_xor_i64: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + return TCG_TARGET_REG_BITS =3D=3D 64; + + case INDEX_op_movcond_i64: + return TCG_TARGET_HAS_movcond_i64; + case INDEX_op_div_i64: + case INDEX_op_divu_i64: + return TCG_TARGET_HAS_div_i64; + case INDEX_op_rem_i64: + case INDEX_op_remu_i64: + return TCG_TARGET_HAS_rem_i64; + case INDEX_op_div2_i64: + case INDEX_op_divu2_i64: + return TCG_TARGET_HAS_div2_i64; + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i64: + return TCG_TARGET_HAS_rot_i64; + case INDEX_op_deposit_i64: + return TCG_TARGET_HAS_deposit_i64; + case INDEX_op_extract_i64: + return TCG_TARGET_HAS_extract_i64; + case INDEX_op_sextract_i64: + return TCG_TARGET_HAS_sextract_i64; + case INDEX_op_extrl_i64_i32: + return TCG_TARGET_HAS_extrl_i64_i32; + case INDEX_op_extrh_i64_i32: + return TCG_TARGET_HAS_extrh_i64_i32; + case INDEX_op_ext8s_i64: + return TCG_TARGET_HAS_ext8s_i64; + case INDEX_op_ext16s_i64: + return TCG_TARGET_HAS_ext16s_i64; + case INDEX_op_ext32s_i64: + return TCG_TARGET_HAS_ext32s_i64; + case INDEX_op_ext8u_i64: + return TCG_TARGET_HAS_ext8u_i64; + case INDEX_op_ext16u_i64: + return TCG_TARGET_HAS_ext16u_i64; + case INDEX_op_ext32u_i64: + return TCG_TARGET_HAS_ext32u_i64; + case INDEX_op_bswap16_i64: + return TCG_TARGET_HAS_bswap16_i64; + case INDEX_op_bswap32_i64: + return TCG_TARGET_HAS_bswap32_i64; + case INDEX_op_bswap64_i64: + return TCG_TARGET_HAS_bswap64_i64; + case INDEX_op_not_i64: + return TCG_TARGET_HAS_not_i64; + case INDEX_op_neg_i64: + return TCG_TARGET_HAS_neg_i64; + case INDEX_op_andc_i64: + return TCG_TARGET_HAS_andc_i64; + case INDEX_op_orc_i64: + return TCG_TARGET_HAS_orc_i64; + case INDEX_op_eqv_i64: + return TCG_TARGET_HAS_eqv_i64; + case INDEX_op_nand_i64: + return TCG_TARGET_HAS_nand_i64; + case INDEX_op_nor_i64: + return TCG_TARGET_HAS_nor_i64; + case INDEX_op_clz_i64: + return TCG_TARGET_HAS_clz_i64; + case INDEX_op_ctz_i64: + return TCG_TARGET_HAS_ctz_i64; + case INDEX_op_ctpop_i64: + return TCG_TARGET_HAS_ctpop_i64; + case INDEX_op_add2_i64: + return TCG_TARGET_HAS_add2_i64; + case INDEX_op_sub2_i64: + return TCG_TARGET_HAS_sub2_i64; + case INDEX_op_mulu2_i64: + return TCG_TARGET_HAS_mulu2_i64; + case INDEX_op_muls2_i64: + return TCG_TARGET_HAS_muls2_i64; + case INDEX_op_muluh_i64: + return TCG_TARGET_HAS_muluh_i64; + case INDEX_op_mulsh_i64: + return TCG_TARGET_HAS_mulsh_i64; + + case INDEX_op_mov_v64: + case INDEX_op_movi_v64: + case INDEX_op_ld_v64: + case INDEX_op_st_v64: + case INDEX_op_and_v64: + case INDEX_op_or_v64: + case INDEX_op_xor_v64: + case INDEX_op_add8_v64: + case INDEX_op_add16_v64: + case INDEX_op_add32_v64: + case INDEX_op_sub8_v64: + case INDEX_op_sub16_v64: + case INDEX_op_sub32_v64: + return TCG_TARGET_HAS_v64; + + case INDEX_op_mov_v128: + case INDEX_op_movi_v128: + case INDEX_op_ld_v128: + case INDEX_op_st_v128: + case INDEX_op_and_v128: + case INDEX_op_or_v128: + case INDEX_op_xor_v128: + case INDEX_op_add8_v128: + case INDEX_op_add16_v128: + case INDEX_op_add32_v128: + case INDEX_op_add64_v128: + case INDEX_op_sub8_v128: + case INDEX_op_sub16_v128: + case INDEX_op_sub32_v128: + case INDEX_op_sub64_v128: + return TCG_TARGET_HAS_v128; + + case INDEX_op_mov_v256: + case INDEX_op_movi_v256: + case INDEX_op_ld_v256: + case INDEX_op_st_v256: + case INDEX_op_and_v256: + case INDEX_op_or_v256: + case INDEX_op_xor_v256: + case INDEX_op_add8_v256: + case INDEX_op_add16_v256: + case INDEX_op_add32_v256: + case INDEX_op_add64_v256: + case INDEX_op_sub8_v256: + case INDEX_op_sub16_v256: + case INDEX_op_sub32_v256: + case INDEX_op_sub64_v256: + return TCG_TARGET_HAS_v256; + + case INDEX_op_not_v64: + return TCG_TARGET_HAS_not_v64; + case INDEX_op_not_v128: + return TCG_TARGET_HAS_not_v128; + case INDEX_op_not_v256: + return TCG_TARGET_HAS_not_v256; + + case INDEX_op_andc_v64: + return TCG_TARGET_HAS_andc_v64; + case INDEX_op_andc_v128: + return TCG_TARGET_HAS_andc_v128; + case INDEX_op_andc_v256: + return TCG_TARGET_HAS_andc_v256; + + case INDEX_op_orc_v64: + return TCG_TARGET_HAS_orc_v64; + case INDEX_op_orc_v128: + return TCG_TARGET_HAS_orc_v128; + case INDEX_op_orc_v256: + return TCG_TARGET_HAS_orc_v256; + + case INDEX_op_neg8_v64: + case INDEX_op_neg16_v64: + case INDEX_op_neg32_v64: + return TCG_TARGET_HAS_neg_v64; + + case INDEX_op_neg8_v128: + case INDEX_op_neg16_v128: + case INDEX_op_neg32_v128: + case INDEX_op_neg64_v128: + return TCG_TARGET_HAS_neg_v128; + + case INDEX_op_neg8_v256: + case INDEX_op_neg16_v256: + case INDEX_op_neg32_v256: + case INDEX_op_neg64_v256: + return TCG_TARGET_HAS_neg_v256; + + case NB_OPS: + break; + } + g_assert_not_reached(); +} + /* Note: we convert the 64 bit args to 32 bit and do some alignment and endian swap. Maybe it would be better to do the alignment and endian swap in tcg_reg_alloc_call(). */ --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150523401198826.27917991770937; Tue, 12 Sep 2017 09:33:31 -0700 (PDT) Received: from localhost ([::1]:36916 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro7v-0000vn-80 for importer@patchew.org; Tue, 12 Sep 2017 12:33:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37882) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro05-0001fs-77 for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dro04-00071M-Br for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:25 -0400 Received: from mail-pg0-x232.google.com ([2607:f8b0:400e:c05::232]:37513) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dro04-000713-69 for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:24 -0400 Received: by mail-pg0-x232.google.com with SMTP id d8so22188704pgt.4 for ; Tue, 12 Sep 2017 09:25:24 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::232 Subject: [Qemu-devel] [PATCH v2 05/16] tcg: Add INDEX_op_invalid X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Add with value 0 so that structure zero initialization can indicate that the field is not present. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg-opc.h | 2 ++ tcg/tcg.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index edfdbf8798..b84cd584fb 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -26,6 +26,8 @@ * DEF(name, oargs, iargs, cargs, flags) */ =20 +DEF(invalid, 0, 0, 0, TCG_OPF_NOT_PRESENT) + /* predefined ops */ DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT) DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) diff --git a/tcg/tcg.c b/tcg/tcg.c index 9aea00d9b4..8fca202bec 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -754,6 +754,9 @@ int tcg_check_temp_count(void) bool tcg_op_supported(TCGOpcode op) { switch (op) { + case INDEX_op_invalid: + return false; + case INDEX_op_discard: case INDEX_op_set_label: case INDEX_op_call: --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505233868808650.5865177688557; Tue, 12 Sep 2017 09:31:08 -0700 (PDT) Received: from localhost ([::1]:36906 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro5b-0007Af-Q4 for importer@patchew.org; Tue, 12 Sep 2017 12:31:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37947) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro09-0001kT-7j for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dro06-00072Z-4d for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:29 -0400 Received: from mail-pf0-x236.google.com ([2607:f8b0:400e:c00::236]:33034) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dro05-000722-QC for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:26 -0400 Received: by mail-pf0-x236.google.com with SMTP id y29so18668673pff.0 for ; Tue, 12 Sep 2017 09:25:25 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net. [97.126.103.167]) by smtp.gmail.com with ESMTPSA id b22sm20382140pfh.175.2017.09.12.09.25.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 09:25:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0JcS9EA47A/X+tvVNHzf7WGLdo5Pi/Td5FVLvgIbWrg=; b=M7+F76lkVtlzvLmbfmBSCr0lPcyK4xeh8aezYb9W9O0aK0lOV2rkJ0TzxhtNGTjx9e AbIFASZSaN44kmo4XUY9w7LekjbtG/+ErYL/clxlih852xYcrkQH3bwOnaoNINTbRUZP uZHb+MmztNbk3cxDi/dBD956gMZi9BlGCVlmQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0JcS9EA47A/X+tvVNHzf7WGLdo5Pi/Td5FVLvgIbWrg=; b=ltGoiNdtkULhpjTVcFo4vswCOk2fVG7OaIqOvYmA42gCUPbuhFjoQCEmy4mORxwgNe ZxHS7GFEHdI8Yb6d4KJZ1chNK+GYS6sSeqQsjOYTZBN8d2d5C/RpnvrxLmW78G460aeN dla0SQ+PcN3sao0+8bzoqBRPD0h4XAepuRqzodYJtafkwj1G34kNkhuaV1QSerceScXa htgq3waoG7jmYP8qh2WSfcWf5Qeg5BGkiFfhDTHIPoz0VJz7xUQNh/B1OAVSJMQA3BPL /YXS87mOyAXlgCOWVSC43OT9P2THqFW0yGfHY8T8sInwBU/HsDTC8VVjw9GfvxF4bzTD ezVA== X-Gm-Message-State: AHPjjUi54S0nJ6NY+q+Gm3xpfUAV1RGMczokQtJvTPF3C6fXl/9EgftW ukgjcLtSQrzHaI4iebku2Q== X-Google-Smtp-Source: ADKCNb6Cl2/cmQ/FvWWU3ZZi619ZtYBI900nVUH62HuJYG0JfNRFX+vJwlf67/A4AkEn+gFR74hmUw== X-Received: by 10.98.155.220 with SMTP id e89mr16134570pfk.120.1505233524206; Tue, 12 Sep 2017 09:25:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Sep 2017 09:25:03 -0700 Message-Id: <20170912162513.21694-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170912162513.21694-1-richard.henderson@linaro.org> References: <20170912162513.21694-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PATCH v2 06/16] tcg: Add vector infrastructure and ops for add/sub/logic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- Makefile.target | 2 +- tcg/tcg-op-gvec.h | 61 ++++++ tcg/tcg-runtime.h | 16 ++ tcg/tcg.h | 2 + tcg/tcg-op-gvec.c | 489 +++++++++++++++++++++++++++++++++++++++++++++= ++++ tcg/tcg-runtime-gvec.c | 192 +++++++++++++++++++ tcg/tcg.c | 4 +- 7 files changed, 763 insertions(+), 3 deletions(-) create mode 100644 tcg/tcg-runtime-gvec.c diff --git a/Makefile.target b/Makefile.target index e647b6e2cb..9eefe7cbd7 100644 --- a/Makefile.target +++ b/Makefile.target @@ -95,7 +95,7 @@ obj-y +=3D exec.o obj-y +=3D accel/ obj-$(CONFIG_TCG) +=3D tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-gvec.o obj-$(CONFIG_TCG) +=3D tcg/optimize.o tcg/tcg-common.o -obj-$(CONFIG_TCG) +=3D tcg/tcg-runtime.o +obj-$(CONFIG_TCG) +=3D tcg/tcg-runtime.o tcg/tcg-runtime-gvec.o obj-$(CONFIG_TCG_INTERPRETER) +=3D tcg/tci.o obj-$(CONFIG_TCG_INTERPRETER) +=3D disas/tci.o obj-y +=3D fpu/softfloat.o diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index affb7c2e89..11d04342b6 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -41,3 +41,64 @@ typedef void (gen_helper_gvec_3_ptr)(TCGv_ptr, TCGv_ptr,= TCGv_ptr, void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, uint32_t data, gen_helper_gvec_3_ptr *fn); + +/* Expand a gvec operation. Either inline or out-of-line depending on + the actual vector size and the operations supported by the host. */ +typedef struct { + /* "Small" sizes: expand inline as a 64-bit or 32-bit lane. + Only one of these will be non-NULL. */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); + /* Larger sizes: expand out-of-line helper w/descriptor. */ + gen_helper_gvec_3 *fno; + /* Host vector operations. */ + TCGOpcode op_v64; + TCGOpcode op_v128; + TCGOpcode op_v256; +} GVecGen3; + +void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz, const GVecGen3 *); + +/* Expand a specific vector operation. */ + +#define DEF(X) \ + void tcg_gen_gvec_##X(uint32_t dofs, uint32_t aofs, uint32_t bofs, \ + uint32_t opsz, uint32_t clsz) + +DEF(add8); +DEF(add16); +DEF(add32); +DEF(add64); + +DEF(sub8); +DEF(sub16); +DEF(sub32); +DEF(sub64); + +DEF(and); +DEF(or); +DEF(xor); +DEF(andc); +DEF(orc); + +#undef DEF + +/* + * 64-bit vector operations. Use these when the register has been allocat= ed + * with tcg_global_mem_new_i64, and so we cannot also address it via point= er. + * OPRSZ =3D MAXSZ =3D 8. + */ + +#define DEF(X) \ + void tcg_gen_vec_##X(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) + +DEF(add8); +DEF(add16); +DEF(add32); + +DEF(sub8); +DEF(sub16); +DEF(sub32); + +#undef DEF diff --git a/tcg/tcg-runtime.h b/tcg/tcg-runtime.h index c41d38a557..befb0fa659 100644 --- a/tcg/tcg-runtime.h +++ b/tcg/tcg-runtime.h @@ -134,3 +134,19 @@ GEN_ATOMIC_HELPERS(xor_fetch) GEN_ATOMIC_HELPERS(xchg) =20 #undef GEN_ATOMIC_HELPERS + +DEF_HELPER_FLAGS_4(gvec_add8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_add16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_add32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_add64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_sub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_and, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_xor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_andc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_orc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/tcg/tcg.h b/tcg/tcg.h index b81c67a754..37ad9fddab 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -824,9 +824,11 @@ int tcg_global_mem_new_internal(TCGType, TCGv_ptr, int= ptr_t, const char *); TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name); TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name); =20 +int tcg_temp_new_internal(TCGType type, int temp_local); TCGv_i32 tcg_temp_new_internal_i32(int temp_local); TCGv_i64 tcg_temp_new_internal_i64(int temp_local); =20 +void tcg_temp_free_internal(int idx); void tcg_temp_free_i32(TCGv_i32 arg); void tcg_temp_free_i64(TCGv_i64 arg); =20 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index f48415020d..4b39617682 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -24,6 +24,30 @@ #include "tcg-op-gvec.h" #include "tcg-gvec-desc.h" =20 +#define REP8(x) ((x) * 0x0101010101010101ull) +#define REP16(x) ((x) * 0x0001000100010001ull) + +#define MAX_UNROLL 4 + +/* Verify vector size and alignment rules. OFS should be the OR of all + of the operand offsets so that we can check them all at once. */ +static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs) +{ + uint32_t align =3D maxsz > 16 || oprsz >=3D 16 ? 15 : 7; + tcg_debug_assert(oprsz > 0); + tcg_debug_assert(oprsz <=3D maxsz); + tcg_debug_assert((oprsz & align) =3D=3D 0); + tcg_debug_assert((maxsz & align) =3D=3D 0); + tcg_debug_assert((ofs & align) =3D=3D 0); +} + +/* Verify vector overlap rules for three operands. */ +static void check_overlap_3(uint32_t d, uint32_t a, uint32_t b, uint32_t s) +{ + tcg_debug_assert(d =3D=3D a || d + s <=3D a || a + s <=3D d); + tcg_debug_assert(d =3D=3D b || d + s <=3D b || b + s <=3D d); + tcg_debug_assert(a =3D=3D b || a + s <=3D b || b + s <=3D a); +} =20 /* Create a descriptor from components. */ uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data) @@ -91,3 +115,468 @@ void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, = uint32_t bofs, tcg_temp_free_ptr(a2); tcg_temp_free_i32(desc); } + +/* Return true if we want to implement something of OPRSZ bytes + in units of LNSZ. This limits the expansion of inline code. */ +static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz) +{ + uint32_t lnct =3D oprsz / lnsz; + return lnct >=3D 1 && lnct <=3D MAX_UNROLL; +} + +/* Clear MAXSZ bytes at DOFS using elements of TYPE. LNSZ =3D sizeof(TYPE= ); + OPC_MV is the opcode that zeros; OPC_ST is the opcode that stores. */ +static void expand_clr_v(uint32_t dofs, uint32_t maxsz, uint32_t lnsz, + TCGType type, TCGOpcode opc_mv, TCGOpcode opc_st) +{ + TCGArg t0 =3D tcg_temp_new_internal(type, 0); + TCGArg env =3D GET_TCGV_PTR(tcg_ctx.tcg_env); + uint32_t i; + + tcg_gen_op2(&tcg_ctx, opc_mv, t0, 0); + for (i =3D 0; i < maxsz; i +=3D lnsz) { + tcg_gen_op3(&tcg_ctx, opc_st, t0, env, dofs + i); + } + tcg_temp_free_internal(t0); +} + +/* Clear MAXSZ bytes at DOFS. */ +static void expand_clr(uint32_t dofs, uint32_t maxsz) +{ + if (maxsz >=3D 32 && TCG_TARGET_HAS_v256) { + uint32_t done =3D QEMU_ALIGN_DOWN(maxsz, 32); + expand_clr_v(dofs, done, 32, TCG_TYPE_V256, + INDEX_op_movi_v256, INDEX_op_st_v256); + dofs +=3D done; + maxsz -=3D done; + } + + if (maxsz >=3D 16 && TCG_TARGET_HAS_v128) { + uint16_t done =3D QEMU_ALIGN_DOWN(maxsz, 16); + expand_clr_v(dofs, done, 16, TCG_TYPE_V128, + INDEX_op_movi_v128, INDEX_op_st_v128); + dofs +=3D done; + maxsz -=3D done; + } + + if (TCG_TARGET_REG_BITS =3D=3D 64) { + expand_clr_v(dofs, maxsz, 8, TCG_TYPE_I64, + INDEX_op_movi_i64, INDEX_op_st_i64); + } else if (TCG_TARGET_HAS_v64) { + expand_clr_v(dofs, maxsz, 8, TCG_TYPE_V64, + INDEX_op_movi_v64, INDEX_op_st_v64); + } else { + expand_clr_v(dofs, maxsz, 4, TCG_TYPE_I32, + INDEX_op_movi_i32, INDEX_op_st_i32); + } +} + +/* Expand OPSZ bytes worth of three-operand operations using i32 elements.= */ +static void expand_3x4(uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t opsz, + void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 t0 =3D tcg_temp_new_i32(); + TCGv_i32 t1 =3D tcg_temp_new_i32(); + uint32_t i; + + for (i =3D 0; i < opsz; i +=3D 4) { + tcg_gen_ld_i32(t0, tcg_ctx.tcg_env, aofs + i); + tcg_gen_ld_i32(t1, tcg_ctx.tcg_env, bofs + i); + fni(t0, t0, t1); + tcg_gen_st_i32(t0, tcg_ctx.tcg_env, dofs + i); + } + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t0); +} + +/* Expand OPSZ bytes worth of three-operand operations using i64 elements.= */ +static void expand_3x8(uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t opsz, + void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + uint32_t i; + + for (i =3D 0; i < opsz; i +=3D 8) { + tcg_gen_ld_i64(t0, tcg_ctx.tcg_env, aofs + i); + tcg_gen_ld_i64(t1, tcg_ctx.tcg_env, bofs + i); + fni(t0, t0, t1); + tcg_gen_st_i64(t0, tcg_ctx.tcg_env, dofs + i); + } + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t0); +} + +/* Expand OPSZ bytes worth of three-operand operations using vector elemen= ts. + OPC_OP is the operation, OPC_LD is the load, OPC_ST is the store. */ +static void expand_3_v(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t lnsz, TCGType type, + TCGOpcode opc_op, TCGOpcode opc_ld, TCGOpcode opc_s= t) +{ + TCGArg t0 =3D tcg_temp_new_internal(type, 0); + TCGArg env =3D GET_TCGV_PTR(tcg_ctx.tcg_env); + uint32_t i; + + if (aofs =3D=3D bofs) { + for (i =3D 0; i < oprsz; i +=3D lnsz) { + tcg_gen_op3(&tcg_ctx, opc_ld, t0, env, aofs + i); + tcg_gen_op3(&tcg_ctx, opc_op, t0, t0, t0); + tcg_gen_op3(&tcg_ctx, opc_st, t0, env, dofs + i); + } + } else { + TCGArg t1 =3D tcg_temp_new_internal(type, 0); + for (i =3D 0; i < oprsz; i +=3D lnsz) { + tcg_gen_op3(&tcg_ctx, opc_ld, t0, env, aofs + i); + tcg_gen_op3(&tcg_ctx, opc_ld, t1, env, bofs + i); + tcg_gen_op3(&tcg_ctx, opc_op, t0, t0, t1); + tcg_gen_op3(&tcg_ctx, opc_st, t0, env, dofs + i); + } + tcg_temp_free_internal(t1); + } + tcg_temp_free_internal(t0); +} + +/* Expand a vector three-operand operation. */ +void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g) +{ + check_size_align(oprsz, maxsz, dofs | aofs | bofs); + check_overlap_3(dofs, aofs, bofs, maxsz); + + /* Quick check for sizes we won't support inline. */ + if (oprsz > MAX_UNROLL * 32 || maxsz > MAX_UNROLL * 32) { + goto do_ool; + } + + /* Recall that ARM SVE allows vector sizes that are not a power of 2. + Expand with successively smaller host vector sizes. The intent is + that e.g. oprsz =3D=3D 80 would be expanded with 2x32 + 1x16. */ + /* ??? For maxsz > oprsz, the host may be able to use an op-sized + operation, zeroing the balance of the register. We can then + use a cl-sized store to implement the clearing without an extra + store operation. This is true for aarch64 and x86_64 hosts. */ + + if (check_size_impl(oprsz, 32) && tcg_op_supported(g->op_v256)) { + uint32_t done =3D QEMU_ALIGN_DOWN(oprsz, 32); + expand_3_v(dofs, aofs, bofs, done, 32, TCG_TYPE_V256, + g->op_v256, INDEX_op_ld_v256, INDEX_op_st_v256); + dofs +=3D done; + aofs +=3D done; + bofs +=3D done; + oprsz -=3D done; + maxsz -=3D done; + } + + if (check_size_impl(oprsz, 16) && tcg_op_supported(g->op_v128)) { + uint32_t done =3D QEMU_ALIGN_DOWN(oprsz, 16); + expand_3_v(dofs, aofs, bofs, done, 16, TCG_TYPE_V128, + g->op_v128, INDEX_op_ld_v128, INDEX_op_st_v128); + dofs +=3D done; + aofs +=3D done; + bofs +=3D done; + oprsz -=3D done; + maxsz -=3D done; + } + + if (check_size_impl(oprsz, 8)) { + uint32_t done =3D QEMU_ALIGN_DOWN(oprsz, 8); + if (tcg_op_supported(g->op_v64)) { + expand_3_v(dofs, aofs, bofs, done, 8, TCG_TYPE_V64, + g->op_v64, INDEX_op_ld_v64, INDEX_op_st_v64); + } else if (g->fni8) { + expand_3x8(dofs, aofs, bofs, done, g->fni8); + } else { + done =3D 0; + } + dofs +=3D done; + aofs +=3D done; + bofs +=3D done; + oprsz -=3D done; + maxsz -=3D done; + } + + if (check_size_impl(oprsz, 4)) { + uint32_t done =3D QEMU_ALIGN_DOWN(oprsz, 4); + expand_3x4(dofs, aofs, bofs, done, g->fni4); + dofs +=3D done; + aofs +=3D done; + bofs +=3D done; + oprsz -=3D done; + maxsz -=3D done; + } + + if (oprsz =3D=3D 0) { + if (maxsz !=3D 0) { + expand_clr(dofs, maxsz); + } + return; + } + + do_ool: + tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, g->fno); +} + +/* + * Expand specific vector operations. + */ + +static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) +{ + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2 =3D tcg_temp_new_i64(); + TCGv_i64 t3 =3D tcg_temp_new_i64(); + + tcg_gen_andc_i64(t1, a, m); + tcg_gen_andc_i64(t2, b, m); + tcg_gen_xor_i64(t3, a, b); + tcg_gen_add_i64(d, t1, t2); + tcg_gen_and_i64(t3, t3, m); + tcg_gen_xor_i64(d, d, t3); + + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + tcg_temp_free_i64(t3); +} + +void tcg_gen_vec_add8(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 m =3D tcg_const_i64(REP8(0x80)); + gen_addv_mask(d, a, b, m); + tcg_temp_free_i64(m); +} + +void tcg_gen_vec_add16(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 m =3D tcg_const_i64(REP16(0x8000)); + gen_addv_mask(d, a, b, m); + tcg_temp_free_i64(m); +} + +void tcg_gen_vec_add32(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2 =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(t1, a, ~0xffffffffull); + tcg_gen_add_i64(t2, a, b); + tcg_gen_add_i64(t1, t1, b); + tcg_gen_deposit_i64(d, t1, t2, 0, 32); + + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); +} + +void tcg_gen_gvec_add8(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_vec_add8, + .fno =3D gen_helper_gvec_add8, + .op_v64 =3D INDEX_op_add8_v64, + .op_v128 =3D INDEX_op_add8_v128, + .op_v256 =3D INDEX_op_add8_v256, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_add16(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_vec_add16, + .fno =3D gen_helper_gvec_add16, + .op_v64 =3D INDEX_op_add16_v64, + .op_v128 =3D INDEX_op_add16_v128, + .op_v256 =3D INDEX_op_add16_v256, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_add32(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g =3D { + .fni4 =3D tcg_gen_add_i32, + .fno =3D gen_helper_gvec_add32, + .op_v64 =3D INDEX_op_add32_v64, + .op_v128 =3D INDEX_op_add32_v128, + .op_v256 =3D INDEX_op_add32_v256, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_add64(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_add_i64, + .fno =3D gen_helper_gvec_add64, + .op_v128 =3D INDEX_op_add64_v128, + .op_v256 =3D INDEX_op_add64_v256, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m) +{ + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2 =3D tcg_temp_new_i64(); + TCGv_i64 t3 =3D tcg_temp_new_i64(); + + tcg_gen_or_i64(t1, a, m); + tcg_gen_andc_i64(t2, b, m); + tcg_gen_eqv_i64(t3, a, b); + tcg_gen_sub_i64(d, t1, t2); + tcg_gen_and_i64(t3, t3, m); + tcg_gen_xor_i64(d, d, t3); + + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + tcg_temp_free_i64(t3); +} + +void tcg_gen_vec_sub8(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 m =3D tcg_const_i64(REP8(0x80)); + gen_subv_mask(d, a, b, m); + tcg_temp_free_i64(m); +} + +void tcg_gen_vec_sub16(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 m =3D tcg_const_i64(REP16(0x8000)); + gen_subv_mask(d, a, b, m); + tcg_temp_free_i64(m); +} + +void tcg_gen_vec_sub32(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2 =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(t1, b, ~0xffffffffull); + tcg_gen_sub_i64(t2, a, b); + tcg_gen_sub_i64(t1, a, t1); + tcg_gen_deposit_i64(d, t1, t2, 0, 32); + + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); +} + +void tcg_gen_gvec_sub8(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_vec_sub8, + .fno =3D gen_helper_gvec_sub8, + .op_v64 =3D INDEX_op_sub8_v64, + .op_v128 =3D INDEX_op_sub8_v128, + .op_v256 =3D INDEX_op_sub8_v256, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_sub16(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_vec_sub16, + .fno =3D gen_helper_gvec_sub16, + .op_v64 =3D INDEX_op_sub16_v64, + .op_v128 =3D INDEX_op_sub16_v128, + .op_v256 =3D INDEX_op_sub16_v256, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_sub32(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g =3D { + .fni4 =3D tcg_gen_sub_i32, + .fno =3D gen_helper_gvec_sub32, + .op_v64 =3D INDEX_op_sub32_v64, + .op_v128 =3D INDEX_op_sub32_v128, + .op_v256 =3D INDEX_op_sub32_v256, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_sub64(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_sub_i64, + .fno =3D gen_helper_gvec_sub64, + .op_v128 =3D INDEX_op_sub64_v128, + .op_v256 =3D INDEX_op_sub64_v256, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_and(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_and_i64, + .fno =3D gen_helper_gvec_and, + .op_v64 =3D INDEX_op_and_v64, + .op_v128 =3D INDEX_op_and_v128, + .op_v256 =3D INDEX_op_and_v256, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_or(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_or_i64, + .fno =3D gen_helper_gvec_or, + .op_v64 =3D INDEX_op_or_v64, + .op_v128 =3D INDEX_op_or_v128, + .op_v256 =3D INDEX_op_or_v256, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_xor(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_xor_i64, + .fno =3D gen_helper_gvec_xor, + .op_v64 =3D INDEX_op_xor_v64, + .op_v128 =3D INDEX_op_xor_v128, + .op_v256 =3D INDEX_op_xor_v256, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_andc(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_andc_i64, + .fno =3D gen_helper_gvec_andc, + .op_v64 =3D INDEX_op_andc_v64, + .op_v128 =3D INDEX_op_andc_v128, + .op_v256 =3D INDEX_op_andc_v256, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} + +void tcg_gen_gvec_orc(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t opsz, uint32_t clsz) +{ + static const GVecGen3 g =3D { + .fni8 =3D tcg_gen_orc_i64, + .fno =3D gen_helper_gvec_orc, + .op_v64 =3D INDEX_op_orc_v64, + .op_v128 =3D INDEX_op_orc_v128, + .op_v256 =3D INDEX_op_orc_v256, + }; + tcg_gen_gvec_3(dofs, aofs, bofs, opsz, clsz, &g); +} diff --git a/tcg/tcg-runtime-gvec.c b/tcg/tcg-runtime-gvec.c new file mode 100644 index 0000000000..ff0f896629 --- /dev/null +++ b/tcg/tcg-runtime-gvec.c @@ -0,0 +1,192 @@ +/* + * Generic vectorized operation runtime + * + * Copyright (c) 2017 Linaro + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "tcg-gvec-desc.h" + + +/* Virtually all hosts support 16-byte vectors. Those that don't can emul= ate + them via GCC's generic vector extension. This turns out to be simpler = and + more reliable than getting the compiler to autovectorize. + + In tcg-op-gvec.c, we asserted that both the size and alignment + of the data are multiples of 16. */ + +typedef uint8_t vec8 __attribute__((vector_size(16))); +typedef uint16_t vec16 __attribute__((vector_size(16))); +typedef uint32_t vec32 __attribute__((vector_size(16))); +typedef uint64_t vec64 __attribute__((vector_size(16))); + +static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc) +{ + intptr_t maxsz =3D simd_maxsz(desc); + intptr_t i; + + if (unlikely(maxsz > oprsz)) { + for (i =3D oprsz; i < maxsz; i +=3D sizeof(vec64)) { + *(vec64 *)(d + i) =3D (vec64){ 0 }; + } + } +} + +void HELPER(gvec_add8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec8)) { + *(vec8 *)(d + i) =3D *(vec8 *)(a + i) + *(vec8 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_add16)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec16)) { + *(vec16 *)(d + i) =3D *(vec16 *)(a + i) + *(vec16 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_add32)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec32)) { + *(vec32 *)(d + i) =3D *(vec32 *)(a + i) + *(vec32 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec64)) { + *(vec64 *)(d + i) =3D *(vec64 *)(a + i) + *(vec64 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sub8)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec8)) { + *(vec8 *)(d + i) =3D *(vec8 *)(a + i) - *(vec8 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sub16)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec16)) { + *(vec16 *)(d + i) =3D *(vec16 *)(a + i) - *(vec16 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sub32)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec32)) { + *(vec32 *)(d + i) =3D *(vec32 *)(a + i) - *(vec32 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec64)) { + *(vec64 *)(d + i) =3D *(vec64 *)(a + i) - *(vec64 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_and)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec64)) { + *(vec64 *)(d + i) =3D *(vec64 *)(a + i) & *(vec64 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_or)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec64)) { + *(vec64 *)(d + i) =3D *(vec64 *)(a + i) | *(vec64 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_xor)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec64)) { + *(vec64 *)(d + i) =3D *(vec64 *)(a + i) ^ *(vec64 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_andc)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec64)) { + *(vec64 *)(d + i) =3D *(vec64 *)(a + i) &~ *(vec64 *)(b + i); + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz =3D simd_oprsz(desc); + intptr_t i; + + for (i =3D 0; i < oprsz; i +=3D sizeof(vec64)) { + *(vec64 *)(d + i) =3D *(vec64 *)(a + i) |~ *(vec64 *)(b + i); + } + clear_high(d, oprsz, desc); +} diff --git a/tcg/tcg.c b/tcg/tcg.c index 8fca202bec..240bcaa8d5 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -602,7 +602,7 @@ int tcg_global_mem_new_internal(TCGType type, TCGv_ptr = base, return temp_idx(s, ts); } =20 -static int tcg_temp_new_internal(TCGType type, int temp_local) +int tcg_temp_new_internal(TCGType type, int temp_local) { TCGContext *s =3D &tcg_ctx; TCGTemp *ts; @@ -664,7 +664,7 @@ TCGv_i64 tcg_temp_new_internal_i64(int temp_local) return MAKE_TCGV_I64(idx); } =20 -static void tcg_temp_free_internal(int idx) +void tcg_temp_free_internal(int idx) { TCGContext *s =3D &tcg_ctx; TCGTemp *ts; --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505233799240976.0341992653593; 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X-Received-From: 2607:f8b0:400e:c05::229 Subject: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 98b9b26fd3..419f008277 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -486,7 +486,7 @@ typedef struct CPUARMState { * the two execution states, and means we do not need to explicitly * map these registers when changing states. */ - float64 regs[64]; + float64 regs[64] __attribute__((aligned(16))); =20 uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505234035348340.9436104587767; Tue, 12 Sep 2017 09:33:55 -0700 (PDT) Received: from localhost ([::1]:36917 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro8H-0001H0-DN for importer@patchew.org; Tue, 12 Sep 2017 12:33:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro0C-0001nm-Hf for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dro08-00073U-67 for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:32 -0400 Received: from mail-pg0-x234.google.com ([2607:f8b0:400e:c05::234]:35938) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dro07-000738-Th for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:28 -0400 Received: by mail-pg0-x234.google.com with SMTP id i130so14869833pgc.3 for ; Tue, 12 Sep 2017 09:25:27 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net. [97.126.103.167]) by smtp.gmail.com with ESMTPSA id b22sm20382140pfh.175.2017.09.12.09.25.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 09:25:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ByRv4yStlmXXTgaHEqSXUghKE6M2Phz6mSRs5MIlqMI=; b=JjckUlqUa3Dm5sgp5Kl3HgfPDimwFR8OkZXk+WPTz94ChclLftuiIizhJHm7crQ3zl hCrcvifmmZ6XtpU+9BsUDLhOUh3/081WYpw4CMHx8HzF4xQloQ3anWe09NTMUnsh1eky wEcqYY41M1jk879/Q2Q8Ejgf0Fky9KM68M9kA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ByRv4yStlmXXTgaHEqSXUghKE6M2Phz6mSRs5MIlqMI=; b=XyAU5GNWX8kwSdniLYsXEimNP+x066IILIQgJbLhKKnzrVDV7kXFW/MnGE9Sayf8WC SVAs+UXrbj7rPqShE7RrVlXoRN+yDsIQ9Mu3U4++fXuXbQwIdVVLrBsvkQ+T1O2HqmU1 lkECZ7ITZp3FPHjJy0SQvKTMVTiGIKiztWQBL2aauLRFKwJrZ0/G0fk2UYba9+YykmWr zu8m8mNLV8cXSaS98KlFWWusFLEC6hGhrxkDO+y+DN7kHE7SSYfzuAMKrCpox1W0nA4Z HUZwxbB1zCsAsRKipbH7U4z0E0SO382DwujrB8Mks2E9jAIk4YpjMrJPX9+bhY2vDH8S zzMA== X-Gm-Message-State: AHPjjUhuNP3DC7lkAgx/l3U/uukAX+C0isgaleJt4ol8D9xtbVz6wk18 rkxG6v7Jh1TRASdam7onHA== X-Google-Smtp-Source: ADKCNb7kgCtZdLA5dBfqVxOr1McilTdyDslPlLZ5b8DP7yErMBioWS9tgOc0kgmZiHTA2zfnIHcx1g== X-Received: by 10.98.211.72 with SMTP id q69mr15458989pfg.308.1505233526743; Tue, 12 Sep 2017 09:25:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Sep 2017 09:25:05 -0700 Message-Id: <20170912162513.21694-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170912162513.21694-1-richard.henderson@linaro.org> References: <20170912162513.21694-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::234 Subject: [Qemu-devel] [PATCH v2 08/16] target/arm: Use vector infrastructure for aa64 add/sub/logic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 137 ++++++++++++++++++++++++++++-------------= ---- 1 file changed, 87 insertions(+), 50 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9017e30510..d01a180fba 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "tcg-op.h" +#include "tcg-op-gvec.h" #include "qemu/log.h" #include "arm_ldst.h" #include "translate.h" @@ -82,6 +83,7 @@ typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCG= v_i64, TCGv_ptr); typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32); typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); +typedef void GVecGenTwoFn(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t= ); =20 /* initialize TCG globals. */ void a64_translate_init(void) @@ -537,6 +539,21 @@ static inline int vec_reg_offset(DisasContext *s, int = regno, return offs; } =20 +/* Return the offset info CPUARMState of the "whole" vector register Qn. = */ +static inline int vec_full_reg_offset(DisasContext *s, int regno) +{ + assert_fp_access_checked(s); + return offsetof(CPUARMState, vfp.regs[regno * 2]); +} + +/* Return the byte size of the "whole" vector register, VL / 8. */ +static inline int vec_full_reg_size(DisasContext *s) +{ + /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags. + In the meantime this is just the AdvSIMD length of 128. */ + return 128 / 8; +} + /* Return the offset into CPUARMState of a slice (from * the least significant end) of FP register Qn (ie * Dn, Sn, Hn or Bn). @@ -9047,11 +9064,38 @@ static void disas_simd_3same_logic(DisasContext *s,= uint32_t insn) bool is_q =3D extract32(insn, 30, 1); TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; int pass; + GVecGenTwoFn *gvec_op; =20 if (!fp_access_check(s)) { return; } =20 + switch (size + 4 * is_u) { + case 0: /* AND */ + gvec_op =3D tcg_gen_gvec_and; + goto do_gvec; + case 1: /* BIC */ + gvec_op =3D tcg_gen_gvec_andc; + goto do_gvec; + case 2: /* ORR */ + gvec_op =3D tcg_gen_gvec_or; + goto do_gvec; + case 3: /* ORN */ + gvec_op =3D tcg_gen_gvec_orc; + goto do_gvec; + case 4: /* EOR */ + gvec_op =3D tcg_gen_gvec_xor; + goto do_gvec; + do_gvec: + gvec_op(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s)); + return; + } + + /* Note that we've now eliminated all !is_u. */ + tcg_op1 =3D tcg_temp_new_i64(); tcg_op2 =3D tcg_temp_new_i64(); tcg_res[0] =3D tcg_temp_new_i64(); @@ -9061,47 +9105,27 @@ static void disas_simd_3same_logic(DisasContext *s,= uint32_t insn) read_vec_element(s, tcg_op1, rn, pass, MO_64); read_vec_element(s, tcg_op2, rm, pass, MO_64); =20 - if (!is_u) { - switch (size) { - case 0: /* AND */ - tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 1: /* BIC */ - tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 2: /* ORR */ - tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 3: /* ORN */ - tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - } - } else { - if (size !=3D 0) { - /* B* ops need res loaded to operate on */ - read_vec_element(s, tcg_res[pass], rd, pass, MO_64); - } + /* B* ops need res loaded to operate on */ + read_vec_element(s, tcg_res[pass], rd, pass, MO_64); =20 - switch (size) { - case 0: /* EOR */ - tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2); - break; - case 1: /* BSL bitwise select */ - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2); - tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]); - tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1); - break; - case 2: /* BIT, bitwise insert if true */ - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); - tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2); - tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); - break; - case 3: /* BIF, bitwise insert if false */ - tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); - tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2); - tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); - break; - } + switch (size) { + case 1: /* BSL bitwise select */ + tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2); + tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]); + tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1); + break; + case 2: /* BIT, bitwise insert if true */ + tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); + tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2); + tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); + break; + case 3: /* BIF, bitwise insert if false */ + tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]); + tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2); + tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); + break; + default: + g_assert_not_reached(); } } =20 @@ -9375,6 +9399,7 @@ static void disas_simd_3same_int(DisasContext *s, uin= t32_t insn) int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); int pass; + GVecGenTwoFn *gvec_op; =20 switch (opcode) { case 0x13: /* MUL, PMUL */ @@ -9414,6 +9439,28 @@ static void disas_simd_3same_int(DisasContext *s, ui= nt32_t insn) return; } =20 + switch (opcode) { + case 0x10: /* ADD, SUB */ + { + static GVecGenTwoFn * const fns[4][2] =3D { + { tcg_gen_gvec_add8, tcg_gen_gvec_sub8 }, + { tcg_gen_gvec_add16, tcg_gen_gvec_sub16 }, + { tcg_gen_gvec_add32, tcg_gen_gvec_sub32 }, + { tcg_gen_gvec_add64, tcg_gen_gvec_sub64 }, + }; + gvec_op =3D fns[size][u]; + goto do_gvec; + } + break; + + do_gvec: + gvec_op(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s)); + return; + } + if (size =3D=3D 3) { assert(is_q); for (pass =3D 0; pass < 2; pass++) { @@ -9586,16 +9633,6 @@ static void disas_simd_3same_int(DisasContext *s, ui= nt32_t insn) genfn =3D fns[size][u]; break; } - case 0x10: /* ADD, SUB */ - { - static NeonGenTwoOpFn * const fns[3][2] =3D { - { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 }, - { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 }, - { tcg_gen_add_i32, tcg_gen_sub_i32 }, - }; - genfn =3D fns[size][u]; - break; - } case 0x11: /* CMTST, CMEQ */ { static NeonGenTwoOpFn * const fns[3][2] =3D { --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505233966129266.98037841306007; Tue, 12 Sep 2017 09:32:46 -0700 (PDT) Received: from localhost ([::1]:36915 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro7A-0000B6-O1 for importer@patchew.org; Tue, 12 Sep 2017 12:32:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38111) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro0E-0001pL-44 for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dro0A-00075X-Is for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:34 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:35556) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dro0A-00074W-7q for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:30 -0400 Received: by mail-pf0-x233.google.com with SMTP id q76so5835189pfq.2 for ; Tue, 12 Sep 2017 09:25:30 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net. [97.126.103.167]) by smtp.gmail.com with ESMTPSA id b22sm20382140pfh.175.2017.09.12.09.25.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 09:25:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qZd9rXD4x3sGgQqm73GKr9CNNq9c12Y54lVEupqGsLk=; b=D47IKS5MsEknDhmR6kMr+HsSCihZIf8CdiivHRESwcbXyJWuZyk72knlDE33K6W75T Q6yDIbZcfQuc+5dwwNqp1inAtI2kCCEkgCEq5uJylOnx+KMKeG+LuP9VefKUYGyN/2S5 EiyDDk5IVpHj/3adzxVgzTEM1sElKFPIdA4pI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qZd9rXD4x3sGgQqm73GKr9CNNq9c12Y54lVEupqGsLk=; b=KMpOOMmuS9uwaFNyHw9z2F6FzI/U7LYBnFEG/CvSwChp1r6laOJlc96VD4fK9NlTbK XItqxKud5YeGBop3CB1yMnz671dr1dNvOWgqBsMHL+EXELsU+o1503/aq9ImsQ/pMe9m DXgppB3RMhcBQnlzAUZtb9U3hPIzGNUnaUQERq10l+4go8LP7ZjC+7+eWUQydWlEBI16 qsrT80X9rnUi1wZWJvrqI5igNNEJFxqe1UC4/ZxN7gWTrqBYAr6CfGuccPPnjJRpu1pD DwFMzsXvi1je90+b1MeCgHSMijuU1zC4hhgWeo8pqjpvYw6FIvfkPaUeJkiv8KjC5u1S 1rDA== X-Gm-Message-State: AHPjjUg/pNPNgsV6OawqcTU0hPuzINJ9LCpyDJoCDGlCiqhsv6QdrxDe KisZYvB3REucQ9dKNQOgtA== X-Google-Smtp-Source: AOwi7QC22HxhlvbqDmssv1PH3sv/p78GZH6cRsVG48G3Guj6nVbpHICDlYANsk/gdu+rtyXTz2Dv8g== X-Received: by 10.159.246.2 with SMTP id b2mr1431282pls.85.1505233528585; Tue, 12 Sep 2017 09:25:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Sep 2017 09:25:06 -0700 Message-Id: <20170912162513.21694-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170912162513.21694-1-richard.henderson@linaro.org> References: <20170912162513.21694-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PATCH v2 09/16] tcg/i386: Add vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 46 ++++- tcg/i386/tcg-target.inc.c | 438 +++++++++++++++++++++++++++++++++++++++++-= ---- 2 files changed, 438 insertions(+), 46 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b89dababf4..03f2506223 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -30,11 +30,10 @@ =20 #ifdef __x86_64__ # define TCG_TARGET_REG_BITS 64 -# define TCG_TARGET_NB_REGS 16 #else # define TCG_TARGET_REG_BITS 32 -# define TCG_TARGET_NB_REGS 8 #endif +# define TCG_TARGET_NB_REGS 24 =20 typedef enum { TCG_REG_EAX =3D 0, @@ -56,6 +55,19 @@ typedef enum { TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + + /* SSE registers; 64-bit has access to 8 more, but we won't + need more than a few and using only the first 8 minimizes + the need for a rex prefix on the sse instructions. */ + TCG_REG_XMM0, + TCG_REG_XMM1, + TCG_REG_XMM2, + TCG_REG_XMM3, + TCG_REG_XMM4, + TCG_REG_XMM5, + TCG_REG_XMM6, + TCG_REG_XMM7, + TCG_REG_RAX =3D TCG_REG_EAX, TCG_REG_RCX =3D TCG_REG_ECX, TCG_REG_RDX =3D TCG_REG_EDX, @@ -78,6 +90,17 @@ typedef enum { extern bool have_bmi1; extern bool have_popcnt; =20 +#ifdef __SSE2__ +#define have_sse2 true +#else +extern bool have_sse2; +#endif +#ifdef __AVX2__ +#define have_avx2 true +#else +extern bool have_avx2; +#endif + /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 #define TCG_TARGET_HAS_rot_i32 1 @@ -146,6 +169,25 @@ extern bool have_popcnt; #define TCG_TARGET_HAS_mulsh_i64 0 #endif =20 +#define TCG_TARGET_HAS_v64 have_sse2 +#define TCG_TARGET_HAS_v128 have_sse2 +#define TCG_TARGET_HAS_v256 have_avx2 + +#define TCG_TARGET_HAS_andc_v64 TCG_TARGET_HAS_v64 +#define TCG_TARGET_HAS_orc_v64 0 +#define TCG_TARGET_HAS_not_v64 0 +#define TCG_TARGET_HAS_neg_v64 0 + +#define TCG_TARGET_HAS_andc_v128 TCG_TARGET_HAS_v128 +#define TCG_TARGET_HAS_orc_v128 0 +#define TCG_TARGET_HAS_not_v128 0 +#define TCG_TARGET_HAS_neg_v128 0 + +#define TCG_TARGET_HAS_andc_v256 TCG_TARGET_HAS_v256 +#define TCG_TARGET_HAS_orc_v256 0 +#define TCG_TARGET_HAS_not_v256 0 +#define TCG_TARGET_HAS_neg_v256 0 + #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (((ofs) =3D=3D 0 && (len) =3D=3D 8) || ((ofs) =3D=3D 8 && (len) =3D=3D= 8) || \ ((ofs) =3D=3D 0 && (len) =3D=3D 16)) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 5231056fd3..fbb41c3b7a 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -28,10 +28,11 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { #if TCG_TARGET_REG_BITS =3D=3D 64 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", - "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", #else "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", #endif + "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", + "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", }; #endif =20 @@ -61,6 +62,14 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_EDX, TCG_REG_EAX, #endif + TCG_REG_XMM0, + TCG_REG_XMM1, + TCG_REG_XMM2, + TCG_REG_XMM3, + TCG_REG_XMM4, + TCG_REG_XMM5, + TCG_REG_XMM6, + TCG_REG_XMM7, }; =20 static const int tcg_target_call_iarg_regs[] =3D { @@ -94,7 +103,7 @@ static const int tcg_target_call_oarg_regs[] =3D { #define TCG_CT_CONST_I32 0x400 #define TCG_CT_CONST_WSZ 0x800 =20 -/* Registers used with L constraint, which are the first argument=20 +/* Registers used with L constraint, which are the first argument registers on x86_64, and two random call clobbered registers on i386. */ #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -126,6 +135,16 @@ static bool have_cmov; bool have_bmi1; bool have_popcnt; =20 +#ifndef have_sse2 +bool have_sse2; +#endif +#ifdef have_avx2 +#define have_avx1 have_avx2 +#else +static bool have_avx1; +bool have_avx2; +#endif + #ifdef CONFIG_CPUID_H static bool have_movbe; static bool have_bmi2; @@ -192,6 +211,7 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI); break; case 'q': + /* A register that can be used as a byte operand. */ ct->ct |=3D TCG_CT_REG; if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_regset_set32(ct->u.regs, 0, 0xffff); @@ -200,10 +220,12 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, } break; case 'Q': + /* A register with an addressable second byte (e.g. %ah). */ ct->ct |=3D TCG_CT_REG; tcg_regset_set32(ct->u.regs, 0, 0xf); break; case 'r': + /* A general register. */ ct->ct |=3D TCG_CT_REG; if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_regset_set32(ct->u.regs, 0, 0xffff); @@ -215,6 +237,11 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, /* With TZCNT/LZCNT, we can have operand-size as an input. */ ct->ct |=3D TCG_CT_CONST_WSZ; break; + case 'x': + /* A vector register. */ + ct->ct |=3D TCG_CT_REG; + tcg_regset_set32(ct->u.regs, 0, 0xff0000); + break; =20 /* qemu_ld/st address constraint */ case 'L': @@ -289,8 +316,9 @@ static inline int tcg_target_const_match(tcg_target_lon= g val, TCGType type, # define P_REXB_RM 0 # define P_GS 0 #endif -#define P_SIMDF3 0x10000 /* 0xf3 opcode prefix */ -#define P_SIMDF2 0x20000 /* 0xf2 opcode prefix */ +#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */ +#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */ +#define P_VEXL 0x80000 /* Set VEX.L =3D 1 */ =20 #define OPC_ARITH_EvIz (0x81) #define OPC_ARITH_EvIb (0x83) @@ -322,11 +350,29 @@ static inline int tcg_target_const_match(tcg_target_l= ong val, TCGType type, #define OPC_MOVL_Iv (0xb8) #define OPC_MOVBE_GyMy (0xf0 | P_EXT38) #define OPC_MOVBE_MyGy (0xf1 | P_EXT38) +#define OPC_MOVDQA_GyMy (0x6f | P_EXT | P_DATA16) +#define OPC_MOVDQA_MyGy (0x7f | P_EXT | P_DATA16) +#define OPC_MOVDQU_GyMy (0x6f | P_EXT | P_SIMDF3) +#define OPC_MOVDQU_MyGy (0x7f | P_EXT | P_SIMDF3) +#define OPC_MOVQ_GyMy (0x7e | P_EXT | P_SIMDF3) +#define OPC_MOVQ_MyGy (0xd6 | P_EXT | P_DATA16) #define OPC_MOVSBL (0xbe | P_EXT) #define OPC_MOVSWL (0xbf | P_EXT) #define OPC_MOVSLQ (0x63 | P_REXW) #define OPC_MOVZBL (0xb6 | P_EXT) #define OPC_MOVZWL (0xb7 | P_EXT) +#define OPC_PADDB (0xfc | P_EXT | P_DATA16) +#define OPC_PADDW (0xfd | P_EXT | P_DATA16) +#define OPC_PADDD (0xfe | P_EXT | P_DATA16) +#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16) +#define OPC_PAND (0xdb | P_EXT | P_DATA16) +#define OPC_PANDN (0xdf | P_EXT | P_DATA16) +#define OPC_POR (0xeb | P_EXT | P_DATA16) +#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16) +#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16) +#define OPC_PSUBD (0xfa | P_EXT | P_DATA16) +#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16) +#define OPC_PXOR (0xef | P_EXT | P_DATA16) #define OPC_POP_r32 (0x58) #define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) #define OPC_PUSH_r32 (0x50) @@ -342,6 +388,7 @@ static inline int tcg_target_const_match(tcg_target_lon= g val, TCGType type, #define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2) #define OPC_TESTL (0x85) #define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3) +#define OPC_VZEROUPPER (0x77 | P_EXT) #define OPC_XCHG_ax_r32 (0x90) =20 #define OPC_GRP3_Ev (0xf7) @@ -491,11 +538,20 @@ static void tcg_out_modrm(TCGContext *s, int opc, int= r, int rm) tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } =20 -static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) +static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v, + int rm, int index) { int tmp; =20 - if ((opc & (P_REXW | P_EXT | P_EXT38)) || (rm & 8)) { + /* Use the two byte form if possible, which cannot encode + VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */ + if ((opc & (P_EXT | P_EXT38 | P_REXW)) =3D=3D P_EXT + && ((rm | index) & 8) =3D=3D 0) { + /* Two byte VEX prefix. */ + tcg_out8(s, 0xc5); + + tmp =3D (r & 8 ? 0 : 0x80); /* VEX.R */ + } else { /* Three byte VEX prefix. */ tcg_out8(s, 0xc4); =20 @@ -505,20 +561,17 @@ static void tcg_out_vex_modrm(TCGContext *s, int opc,= int r, int v, int rm) } else if (opc & P_EXT) { tmp =3D 1; } else { - tcg_abort(); + g_assert_not_reached(); } - tmp |=3D 0x40; /* VEX.X */ - tmp |=3D (r & 8 ? 0 : 0x80); /* VEX.R */ - tmp |=3D (rm & 8 ? 0 : 0x20); /* VEX.B */ + tmp |=3D (r & 8 ? 0 : 0x80); /* VEX.R */ + tmp |=3D (index & 8 ? 0 : 0x40); /* VEX.X */ + tmp |=3D (rm & 8 ? 0 : 0x20); /* VEX.B */ tcg_out8(s, tmp); =20 - tmp =3D (opc & P_REXW ? 0x80 : 0); /* VEX.W */ - } else { - /* Two byte VEX prefix. */ - tcg_out8(s, 0xc5); - - tmp =3D (r & 8 ? 0 : 0x80); /* VEX.R */ + tmp =3D (opc & P_REXW ? 0x80 : 0); /* VEX.W */ } + + tmp |=3D (opc & P_VEXL ? 0x04 : 0); /* VEX.L */ /* VEX.pp */ if (opc & P_DATA16) { tmp |=3D 1; /* 0x66 */ @@ -530,6 +583,11 @@ static void tcg_out_vex_modrm(TCGContext *s, int opc, = int r, int v, int rm) tmp |=3D (~v & 15) << 3; /* VEX.vvvv */ tcg_out8(s, tmp); tcg_out8(s, opc); +} + +static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) +{ + tcg_out_vex_opc(s, opc, r, v, rm, 0); tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } =20 @@ -538,8 +596,8 @@ static void tcg_out_vex_modrm(TCGContext *s, int opc, i= nt r, int v, int rm) mode for absolute addresses, ~RM is the size of the immediate operand that will follow the instruction. */ =20 -static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, - int index, int shift, intptr_t offset) +static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index, + int shift, intptr_t offset) { int mod, len; =20 @@ -550,7 +608,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int= opc, int r, int rm, intptr_t pc =3D (intptr_t)s->code_ptr + 5 + ~rm; intptr_t disp =3D offset - pc; if (disp =3D=3D (int32_t)disp) { - tcg_out_opc(s, opc, r, 0, 0); tcg_out8(s, (LOWREGMASK(r) << 3) | 5); tcg_out32(s, disp); return; @@ -560,7 +617,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int= opc, int r, int rm, use of the MODRM+SIB encoding and is therefore larger than rip-relative addressing. */ if (offset =3D=3D (int32_t)offset) { - tcg_out_opc(s, opc, r, 0, 0); tcg_out8(s, (LOWREGMASK(r) << 3) | 4); tcg_out8(s, (4 << 3) | 5); tcg_out32(s, offset); @@ -568,10 +624,9 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, in= t opc, int r, int rm, } =20 /* ??? The memory isn't directly addressable. */ - tcg_abort(); + g_assert_not_reached(); } else { /* Absolute address. */ - tcg_out_opc(s, opc, r, 0, 0); tcg_out8(s, (r << 3) | 5); tcg_out32(s, offset); return; @@ -594,7 +649,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int= opc, int r, int rm, that would be used for %esp is the escape to the two byte form. */ if (index < 0 && LOWREGMASK(rm) !=3D TCG_REG_ESP) { /* Single byte MODRM format. */ - tcg_out_opc(s, opc, r, rm, 0); tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } else { /* Two byte MODRM+SIB format. */ @@ -608,7 +662,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int= opc, int r, int rm, tcg_debug_assert(index !=3D TCG_REG_ESP); } =20 - tcg_out_opc(s, opc, r, rm, index); tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4); tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(r= m)); } @@ -620,6 +673,21 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, in= t opc, int r, int rm, } } =20 +static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, + int index, int shift, intptr_t offset) +{ + tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index); + tcg_out_sib_offset(s, r, rm, index, shift, offset); +} + +static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, in= t v, + int rm, int index, int shift, + intptr_t offset) +{ + tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index); + tcg_out_sib_offset(s, r, rm, index, shift, offset); +} + /* A simplification of the above with no index or shift. */ static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, intptr_t offset) @@ -627,6 +695,31 @@ static inline void tcg_out_modrm_offset(TCGContext *s,= int opc, int r, tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset); } =20 +static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r, + int v, int rm, intptr_t offset) +{ + tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset); +} + +static void tcg_out_maybe_vex_modrm(TCGContext *s, int opc, int r, int rm) +{ + if (have_avx1) { + tcg_out_vex_modrm(s, opc, r, 0, rm); + } else { + tcg_out_modrm(s, opc, r, rm); + } +} + +static void tcg_out_maybe_vex_modrm_offset(TCGContext *s, int opc, int r, + int rm, intptr_t offset) +{ + if (have_avx1) { + tcg_out_vex_modrm_offset(s, opc, r, 0, rm, offset); + } else { + tcg_out_modrm_offset(s, opc, r, rm, offset); + } +} + /* Generate dest op=3D src. Uses the same ARITH_* codes as tgen_arithi. = */ static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src) { @@ -637,12 +730,33 @@ static inline void tgen_arithr(TCGContext *s, int sub= op, int dest, int src) tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src); } =20 -static inline void tcg_out_mov(TCGContext *s, TCGType type, - TCGReg ret, TCGReg arg) +static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { - if (arg !=3D ret) { - int opc =3D OPC_MOVL_GvEv + (type =3D=3D TCG_TYPE_I64 ? P_REXW : 0= ); - tcg_out_modrm(s, opc, ret, arg); + if (arg =3D=3D ret) { + return; + } + switch (type) { + case TCG_TYPE_I32: + tcg_debug_assert(ret < 16 && arg < 16); + tcg_out_modrm(s, OPC_MOVL_GvEv, ret, arg); + break; + case TCG_TYPE_I64: + tcg_debug_assert(ret < 16 && arg < 16); + tcg_out_modrm(s, OPC_MOVL_GvEv | P_REXW, ret, arg); + break; + + case TCG_TYPE_V256: + tcg_debug_assert(ret >=3D 16 && arg >=3D 16); + tcg_out_vex_modrm(s, OPC_MOVDQA_GyMy | P_VEXL, ret, 0, arg); + break; + case TCG_TYPE_V128: + case TCG_TYPE_V64: + tcg_debug_assert(ret >=3D 16 && arg >=3D 16); + tcg_out_maybe_vex_modrm(s, OPC_MOVDQA_GyMy, ret, arg); + break; + + default: + g_assert_not_reached(); } } =20 @@ -651,6 +765,29 @@ static void tcg_out_movi(TCGContext *s, TCGType type, { tcg_target_long diff; =20 + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_I64: + tcg_debug_assert(ret < 16); + break; + + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + tcg_debug_assert(ret >=3D 16); + /* ??? Revisit this as the implementation progresses. */ + tcg_debug_assert(arg =3D=3D 0); + if (have_avx1) { + tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret); + } else { + tcg_out_modrm(s, OPC_PXOR, ret, ret); + } + return; + + default: + g_assert_not_reached(); + } + if (arg =3D=3D 0) { tgen_arithr(s, ARITH_XOR, ret, ret); return; @@ -714,18 +851,64 @@ static inline void tcg_out_pop(TCGContext *s, int reg) tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0); } =20 -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, - TCGReg arg1, intptr_t arg2) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, + TCGReg arg1, intptr_t arg2) { - int opc =3D OPC_MOVL_GvEv + (type =3D=3D TCG_TYPE_I64 ? P_REXW : 0); - tcg_out_modrm_offset(s, opc, ret, arg1, arg2); + switch (type) { + case TCG_TYPE_I64: + tcg_debug_assert(ret < 16); + tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2); + break; + case TCG_TYPE_I32: + tcg_debug_assert(ret < 16); + tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2); + break; + case TCG_TYPE_V64: + tcg_debug_assert(ret >=3D 16); + tcg_out_maybe_vex_modrm_offset(s, OPC_MOVQ_GyMy, ret, arg1, arg2); + break; + case TCG_TYPE_V128: + tcg_debug_assert(ret >=3D 16); + tcg_out_maybe_vex_modrm_offset(s, OPC_MOVDQU_GyMy, ret, arg1, arg2= ); + break; + case TCG_TYPE_V256: + tcg_debug_assert(ret >=3D 16); + tcg_out_vex_modrm_offset(s, OPC_MOVDQU_GyMy | P_VEXL, + ret, 0, arg1, arg2); + break; + default: + g_assert_not_reached(); + } } =20 -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { - int opc =3D OPC_MOVL_EvGv + (type =3D=3D TCG_TYPE_I64 ? P_REXW : 0); - tcg_out_modrm_offset(s, opc, arg, arg1, arg2); + switch (type) { + case TCG_TYPE_I64: + tcg_debug_assert(arg < 16); + tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2); + break; + case TCG_TYPE_I32: + tcg_debug_assert(arg < 16); + tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2); + break; + case TCG_TYPE_V64: + tcg_debug_assert(arg >=3D 16); + tcg_out_maybe_vex_modrm_offset(s, OPC_MOVQ_MyGy, arg, arg1, arg2); + break; + case TCG_TYPE_V128: + tcg_debug_assert(arg >=3D 16); + tcg_out_maybe_vex_modrm_offset(s, OPC_MOVDQU_MyGy, arg, arg1, arg2= ); + break; + case TCG_TYPE_V256: + tcg_debug_assert(arg >=3D 16); + tcg_out_vex_modrm_offset(s, OPC_MOVDQU_MyGy | P_VEXL, + arg, 0, arg1, arg2); + break; + default: + g_assert_not_reached(); + } } =20 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, @@ -737,6 +920,8 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TC= GArg val, return false; } rexw =3D P_REXW; + } else if (type !=3D TCG_TYPE_I32) { + return false; } tcg_out_modrm_offset(s, OPC_MOVL_EvIz | rexw, 0, base, ofs); tcg_out32(s, val); @@ -1871,6 +2056,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, case glue(glue(INDEX_op_, x), _i32) #endif =20 +#define OP_128_256(x) \ + case glue(glue(INDEX_op_, x), _v256): \ + rexw =3D P_VEXL; /* FALLTHRU */ \ + case glue(glue(INDEX_op_, x), _v128) + +#define OP_64_128_256(x) \ + OP_128_256(x): \ + case glue(glue(INDEX_op_, x), _v64) + /* Hoist the loads of the most common arguments. */ a0 =3D args[0]; a1 =3D args[1]; @@ -2266,19 +2460,98 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, } break; =20 + OP_64_128_256(add8): + c =3D OPC_PADDB; + goto gen_simd; + OP_64_128_256(add16): + c =3D OPC_PADDW; + goto gen_simd; + OP_64_128_256(add32): + c =3D OPC_PADDD; + goto gen_simd; + OP_128_256(add64): + c =3D OPC_PADDQ; + goto gen_simd; + OP_64_128_256(sub8): + c =3D OPC_PSUBB; + goto gen_simd; + OP_64_128_256(sub16): + c =3D OPC_PSUBW; + goto gen_simd; + OP_64_128_256(sub32): + c =3D OPC_PSUBD; + goto gen_simd; + OP_128_256(sub64): + c =3D OPC_PSUBQ; + goto gen_simd; + OP_64_128_256(and): + c =3D OPC_PAND; + goto gen_simd; + OP_64_128_256(or): + c =3D OPC_POR; + goto gen_simd; + OP_64_128_256(xor): + c =3D OPC_PXOR; + gen_simd: + if (have_avx1) { + tcg_out_vex_modrm(s, c, a0, a1, a2); + } else { + tcg_out_modrm(s, c, a0, a2); + } + break; + OP_64_128_256(andc): + if (have_avx1) { + tcg_out_vex_modrm(s, OPC_PANDN, a0, a2, a1); + } else { + tcg_out_modrm(s, c, a0, a1); + } + break; + + case INDEX_op_ld_v64: + c =3D TCG_TYPE_V64; + goto gen_simd_ld; + case INDEX_op_ld_v128: + c =3D TCG_TYPE_V128; + goto gen_simd_ld; + case INDEX_op_ld_v256: + c =3D TCG_TYPE_V256; + gen_simd_ld: + tcg_out_ld(s, c, a0, a1, a2); + break; + + case INDEX_op_st_v64: + c =3D TCG_TYPE_V64; + goto gen_simd_st; + case INDEX_op_st_v128: + c =3D TCG_TYPE_V128; + goto gen_simd_st; + case INDEX_op_st_v256: + c =3D TCG_TYPE_V256; + gen_simd_st: + tcg_out_st(s, c, a0, a1, a2); + break; + case INDEX_op_mb: tcg_out_mb(s, a0); break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: + case INDEX_op_mov_v64: + case INDEX_op_mov_v128: + case INDEX_op_mov_v256: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_movi_i64: + case INDEX_op_movi_v64: + case INDEX_op_movi_v128: + case INDEX_op_movi_v256: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: tcg_abort(); } =20 #undef OP_32_64 +#undef OP_128_256 +#undef OP_64_128_256 } =20 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) @@ -2304,6 +2577,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) =3D { .args_ct_str =3D { "r", "r", "L", "L" } }; static const TCGTargetOpDef L_L_L_L =3D { .args_ct_str =3D { "L", "L", "L", "L" } }; + static const TCGTargetOpDef x_0_x =3D { .args_ct_str =3D { "x", "0", "= x" } }; + static const TCGTargetOpDef x_x_0 =3D { .args_ct_str =3D { "x", "x", "= 0" } }; + static const TCGTargetOpDef x_x_x =3D { .args_ct_str =3D { "x", "x", "= x" } }; + static const TCGTargetOpDef x_r =3D { .args_ct_str =3D { "x", "r" } }; =20 switch (op) { case INDEX_op_goto_ptr: @@ -2505,6 +2782,53 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) return &s2; } =20 + case INDEX_op_ld_v64: + case INDEX_op_ld_v128: + case INDEX_op_ld_v256: + case INDEX_op_st_v64: + case INDEX_op_st_v128: + case INDEX_op_st_v256: + return &x_r; + + case INDEX_op_add8_v64: + case INDEX_op_add8_v128: + case INDEX_op_add16_v64: + case INDEX_op_add16_v128: + case INDEX_op_add32_v64: + case INDEX_op_add32_v128: + case INDEX_op_add64_v128: + case INDEX_op_sub8_v64: + case INDEX_op_sub8_v128: + case INDEX_op_sub16_v64: + case INDEX_op_sub16_v128: + case INDEX_op_sub32_v64: + case INDEX_op_sub32_v128: + case INDEX_op_sub64_v128: + case INDEX_op_and_v64: + case INDEX_op_and_v128: + case INDEX_op_or_v64: + case INDEX_op_or_v128: + case INDEX_op_xor_v64: + case INDEX_op_xor_v128: + return have_avx1 ? &x_x_x : &x_0_x; + case INDEX_op_andc_v64: + case INDEX_op_andc_v128: + return have_avx1 ? &x_x_x : &x_x_0; + + case INDEX_op_add8_v256: + case INDEX_op_add16_v256: + case INDEX_op_add32_v256: + case INDEX_op_add64_v256: + case INDEX_op_sub8_v256: + case INDEX_op_sub16_v256: + case INDEX_op_sub32_v256: + case INDEX_op_sub64_v256: + case INDEX_op_and_v256: + case INDEX_op_andc_v256: + case INDEX_op_or_v256: + case INDEX_op_xor_v256: + return &x_x_x; + default: break; } @@ -2589,6 +2913,9 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 tcg_out_addi(s, TCG_REG_CALL_STACK, stack_addend); =20 + if (have_avx2) { + tcg_out_vex_opc(s, OPC_VZEROUPPER, 0, 0, 0, 0); + } for (i =3D ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >=3D 0; i--)= { tcg_out_pop(s, tcg_target_callee_save_regs[i]); } @@ -2610,9 +2937,16 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int c= ount) static void tcg_target_init(TCGContext *s) { #ifdef CONFIG_CPUID_H - unsigned a, b, c, d; + unsigned a, b, c, d, b7 =3D 0; int max =3D __get_cpuid_max(0, 0); =20 + if (max >=3D 7) { + /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ + __cpuid_count(7, 0, a, b7, c, d); + have_bmi1 =3D (b7 & bit_BMI) !=3D 0; + have_bmi2 =3D (b7 & bit_BMI2) !=3D 0; + } + if (max >=3D 1) { __cpuid(1, a, b, c, d); #ifndef have_cmov @@ -2621,17 +2955,26 @@ static void tcg_target_init(TCGContext *s) available, we'll use a small forward branch. */ have_cmov =3D (d & bit_CMOV) !=3D 0; #endif +#ifndef have_sse2 + have_sse2 =3D (d & bit_SSE2) !=3D 0; +#endif /* MOVBE is only available on Intel Atom and Haswell CPUs, so we need to probe for it. */ have_movbe =3D (c & bit_MOVBE) !=3D 0; have_popcnt =3D (c & bit_POPCNT) !=3D 0; - } =20 - if (max >=3D 7) { - /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ - __cpuid_count(7, 0, a, b, c, d); - have_bmi1 =3D (b & bit_BMI) !=3D 0; - have_bmi2 =3D (b & bit_BMI2) !=3D 0; +#ifndef have_avx2 + /* There are a number of things we must check before we can be + sure of not hitting invalid opcode. */ + if (c & bit_OSXSAVE) { + unsigned xcrl, xcrh; + asm ("xgetbv" : "=3Da" (xcrl), "=3Dd" (xcrh) : "c" (0)); + if ((xcrl & 6) =3D=3D 6) { + have_avx1 =3D (c & bit_AVX) !=3D 0; + have_avx2 =3D (b7 & bit_AVX2) !=3D 0; + } + } +#endif } =20 max =3D __get_cpuid_max(0x8000000, 0); @@ -2648,6 +2991,13 @@ static void tcg_target_init(TCGContext *s) } else { tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff); } + if (have_sse2) { + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V64], 0, 0xff0= 000); + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V128], 0, 0xff= 0000); + } + if (have_avx2) { + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V256], 0, 0xff= 0000); + } =20 tcg_regset_clear(tcg_target_call_clobber_regs); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX); --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505234045039225.31508241626852; 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[97.126.103.167]) by smtp.gmail.com with ESMTPSA id b22sm20382140pfh.175.2017.09.12.09.25.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 09:25:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T3cqAUA9w3Delh5SFcIZqMIelJzHo2BSO6oOYIwjG9o=; b=jayI5f04TV+1Cs+pR9L18GeTbRAWCXwM2NAh7JF2ljJFUFGklWdffp148993n89ZZD tVxbgSbNRuLDd9c+82WFIK4eqa1mwqYR2WCanQ16wMcLEm51X+/1G92xtczRrIfpj9/e 9jKlQEFfzSQYXrUme1jXFkxJXc0Xg/Z0RajdY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T3cqAUA9w3Delh5SFcIZqMIelJzHo2BSO6oOYIwjG9o=; b=RBgcad6rRDPoEs7g61ywws7uWo9sZj2efuNTmV2PBx5NTSkOeYCroLVlMTao0B7LcJ 81wl3SmyAK6J3FfU/tdp+HDcMEQGcgyaNChvCesHSbCeCiyEBjTcvykf7/11eon1cudR R8F+hMnoFuqO3wSMQjS59IL5zj180Ac9HxMTY6Rw7/x9QD6NMZX6VAwg1bBOB8hrc54A 4E735lK0Hf/GSPaJ/xza0KBY/r6hp+VCerUa06vmwnNLc2Cor9i2+zIUs7L74UVrYK5E +xB6TXzDtHFy94MPIdbsbEibRlJgjSEpJ6j0IqeBoX2bV8XtDpGAOL7MbCsbEI2k2ev2 BCLw== X-Gm-Message-State: AHPjjUg/RvNxKh6nbbQjgNdt/kXdLd+RKtuaArE2sOdUkNX/8WgJvj0Z AJk17AfXYjCQUG4rDvfiJg== X-Google-Smtp-Source: ADKCNb6h5BOsaNQndR6NWomGKY0QrzkmeCq2WfJRDFVTjcWmOMcvWfh3pk9Fx+LQOzF1WHCLGzl/Ag== X-Received: by 10.98.86.216 with SMTP id h85mr15854684pfj.88.1505233529748; Tue, 12 Sep 2017 09:25:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Sep 2017 09:25:07 -0700 Message-Id: <20170912162513.21694-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170912162513.21694-1-richard.henderson@linaro.org> References: <20170912162513.21694-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22e Subject: [Qemu-devel] [PATCH v2 10/16] tcg/aarch64: Fully convert tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 282 +++++++++++++++++++++++----------------= ---- 1 file changed, 151 insertions(+), 131 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index c2f3812214..1ff32e43f5 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1786,141 +1786,161 @@ static void tcg_out_op(TCGContext *s, TCGOpcode o= pc, #undef REG0 } =20 -static const TCGTargetOpDef aarch64_op_defs[] =3D { - { INDEX_op_exit_tb, { } }, - { INDEX_op_goto_tb, { } }, - { INDEX_op_br, { } }, - { INDEX_op_goto_ptr, { "r" } }, - - { INDEX_op_ld8u_i32, { "r", "r" } }, - { INDEX_op_ld8s_i32, { "r", "r" } }, - { INDEX_op_ld16u_i32, { "r", "r" } }, - { INDEX_op_ld16s_i32, { "r", "r" } }, - { INDEX_op_ld_i32, { "r", "r" } }, - { INDEX_op_ld8u_i64, { "r", "r" } }, - { INDEX_op_ld8s_i64, { "r", "r" } }, - { INDEX_op_ld16u_i64, { "r", "r" } }, - { INDEX_op_ld16s_i64, { "r", "r" } }, - { INDEX_op_ld32u_i64, { "r", "r" } }, - { INDEX_op_ld32s_i64, { "r", "r" } }, - { INDEX_op_ld_i64, { "r", "r" } }, - - { INDEX_op_st8_i32, { "rZ", "r" } }, - { INDEX_op_st16_i32, { "rZ", "r" } }, - { INDEX_op_st_i32, { "rZ", "r" } }, - { INDEX_op_st8_i64, { "rZ", "r" } }, - { INDEX_op_st16_i64, { "rZ", "r" } }, - { INDEX_op_st32_i64, { "rZ", "r" } }, - { INDEX_op_st_i64, { "rZ", "r" } }, - - { INDEX_op_add_i32, { "r", "r", "rA" } }, - { INDEX_op_add_i64, { "r", "r", "rA" } }, - { INDEX_op_sub_i32, { "r", "r", "rA" } }, - { INDEX_op_sub_i64, { "r", "r", "rA" } }, - { INDEX_op_mul_i32, { "r", "r", "r" } }, - { INDEX_op_mul_i64, { "r", "r", "r" } }, - { INDEX_op_div_i32, { "r", "r", "r" } }, - { INDEX_op_div_i64, { "r", "r", "r" } }, - { INDEX_op_divu_i32, { "r", "r", "r" } }, - { INDEX_op_divu_i64, { "r", "r", "r" } }, - { INDEX_op_rem_i32, { "r", "r", "r" } }, - { INDEX_op_rem_i64, { "r", "r", "r" } }, - { INDEX_op_remu_i32, { "r", "r", "r" } }, - { INDEX_op_remu_i64, { "r", "r", "r" } }, - { INDEX_op_and_i32, { "r", "r", "rL" } }, - { INDEX_op_and_i64, { "r", "r", "rL" } }, - { INDEX_op_or_i32, { "r", "r", "rL" } }, - { INDEX_op_or_i64, { "r", "r", "rL" } }, - { INDEX_op_xor_i32, { "r", "r", "rL" } }, - { INDEX_op_xor_i64, { "r", "r", "rL" } }, - { INDEX_op_andc_i32, { "r", "r", "rL" } }, - { INDEX_op_andc_i64, { "r", "r", "rL" } }, - { INDEX_op_orc_i32, { "r", "r", "rL" } }, - { INDEX_op_orc_i64, { "r", "r", "rL" } }, - { INDEX_op_eqv_i32, { "r", "r", "rL" } }, - { INDEX_op_eqv_i64, { "r", "r", "rL" } }, - - { INDEX_op_neg_i32, { "r", "r" } }, - { INDEX_op_neg_i64, { "r", "r" } }, - { INDEX_op_not_i32, { "r", "r" } }, - { INDEX_op_not_i64, { "r", "r" } }, - - { INDEX_op_shl_i32, { "r", "r", "ri" } }, - { INDEX_op_shr_i32, { "r", "r", "ri" } }, - { INDEX_op_sar_i32, { "r", "r", "ri" } }, - { INDEX_op_rotl_i32, { "r", "r", "ri" } }, - { INDEX_op_rotr_i32, { "r", "r", "ri" } }, - { INDEX_op_clz_i32, { "r", "r", "rAL" } }, - { INDEX_op_ctz_i32, { "r", "r", "rAL" } }, - { INDEX_op_shl_i64, { "r", "r", "ri" } }, - { INDEX_op_shr_i64, { "r", "r", "ri" } }, - { INDEX_op_sar_i64, { "r", "r", "ri" } }, - { INDEX_op_rotl_i64, { "r", "r", "ri" } }, - { INDEX_op_rotr_i64, { "r", "r", "ri" } }, - { INDEX_op_clz_i64, { "r", "r", "rAL" } }, - { INDEX_op_ctz_i64, { "r", "r", "rAL" } }, - - { INDEX_op_brcond_i32, { "r", "rA" } }, - { INDEX_op_brcond_i64, { "r", "rA" } }, - { INDEX_op_setcond_i32, { "r", "r", "rA" } }, - { INDEX_op_setcond_i64, { "r", "r", "rA" } }, - { INDEX_op_movcond_i32, { "r", "r", "rA", "rZ", "rZ" } }, - { INDEX_op_movcond_i64, { "r", "r", "rA", "rZ", "rZ" } }, - - { INDEX_op_qemu_ld_i32, { "r", "l" } }, - { INDEX_op_qemu_ld_i64, { "r", "l" } }, - { INDEX_op_qemu_st_i32, { "lZ", "l" } }, - { INDEX_op_qemu_st_i64, { "lZ", "l" } }, - - { INDEX_op_bswap16_i32, { "r", "r" } }, - { INDEX_op_bswap32_i32, { "r", "r" } }, - { INDEX_op_bswap16_i64, { "r", "r" } }, - { INDEX_op_bswap32_i64, { "r", "r" } }, - { INDEX_op_bswap64_i64, { "r", "r" } }, - - { INDEX_op_ext8s_i32, { "r", "r" } }, - { INDEX_op_ext16s_i32, { "r", "r" } }, - { INDEX_op_ext8u_i32, { "r", "r" } }, - { INDEX_op_ext16u_i32, { "r", "r" } }, - - { INDEX_op_ext8s_i64, { "r", "r" } }, - { INDEX_op_ext16s_i64, { "r", "r" } }, - { INDEX_op_ext32s_i64, { "r", "r" } }, - { INDEX_op_ext8u_i64, { "r", "r" } }, - { INDEX_op_ext16u_i64, { "r", "r" } }, - { INDEX_op_ext32u_i64, { "r", "r" } }, - { INDEX_op_ext_i32_i64, { "r", "r" } }, - { INDEX_op_extu_i32_i64, { "r", "r" } }, - - { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, - { INDEX_op_deposit_i64, { "r", "0", "rZ" } }, - { INDEX_op_extract_i32, { "r", "r" } }, - { INDEX_op_extract_i64, { "r", "r" } }, - { INDEX_op_sextract_i32, { "r", "r" } }, - { INDEX_op_sextract_i64, { "r", "r" } }, - - { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rA", "rMZ" } }, - { INDEX_op_add2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } }, - { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rA", "rMZ" } }, - { INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } }, - - { INDEX_op_muluh_i64, { "r", "r", "r" } }, - { INDEX_op_mulsh_i64, { "r", "r", "r" } }, - - { INDEX_op_mb, { } }, - { -1 }, -}; - static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - int i, n =3D ARRAY_SIZE(aarch64_op_defs); + static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; + static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; + static const TCGTargetOpDef r_l =3D { .args_ct_str =3D { "r", "l" } }; + static const TCGTargetOpDef r_rA =3D { .args_ct_str =3D { "r", "rA" } = }; + static const TCGTargetOpDef rZ_r =3D { .args_ct_str =3D { "rZ", "r" } = }; + static const TCGTargetOpDef lZ_l =3D { .args_ct_str =3D { "lZ", "l" } = }; + static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; + static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; + static const TCGTargetOpDef r_r_rA =3D { .args_ct_str =3D { "r", "r", = "rA" } }; + static const TCGTargetOpDef r_r_rL =3D { .args_ct_str =3D { "r", "r", = "rL" } }; + static const TCGTargetOpDef r_r_rAL + =3D { .args_ct_str =3D { "r", "r", "rAL" } }; + static const TCGTargetOpDef dep + =3D { .args_ct_str =3D { "r", "0", "rZ" } }; + static const TCGTargetOpDef movc + =3D { .args_ct_str =3D { "r", "r", "rA", "rZ", "rZ" } }; + static const TCGTargetOpDef add2 + =3D { .args_ct_str =3D { "r", "r", "rZ", "rZ", "rA", "rMZ" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; =20 - for (i =3D 0; i < n; ++i) { - if (aarch64_op_defs[i].op =3D=3D op) { - return &aarch64_op_defs[i]; - } + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_not_i32: + case INDEX_op_not_i64: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext16s_i32: + case INDEX_op_ext8u_i32: + case INDEX_op_ext16u_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext16s_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + case INDEX_op_sextract_i32: + case INDEX_op_sextract_i64: + return &r_r; + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return &rZ_r; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return &r_r_rA; + + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + case INDEX_op_div_i32: + case INDEX_op_div_i64: + case INDEX_op_divu_i32: + case INDEX_op_divu_i64: + case INDEX_op_rem_i32: + case INDEX_op_rem_i64: + case INDEX_op_remu_i32: + case INDEX_op_remu_i64: + case INDEX_op_muluh_i64: + case INDEX_op_mulsh_i64: + return &r_r_r; + + case INDEX_op_and_i32: + case INDEX_op_and_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + return &r_r_rL; + + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_rotl_i32: + case INDEX_op_rotr_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i64: + return &r_r_ri; + + case INDEX_op_clz_i32: + case INDEX_op_ctz_i32: + case INDEX_op_clz_i64: + case INDEX_op_ctz_i64: + return &r_r_rAL; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return &r_rA; + + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: + return &movc; + + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_i64: + return &r_l; + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_i64: + return &lZ_l; + + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + return &dep; + + case INDEX_op_add2_i32: + case INDEX_op_add2_i64: + case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: + return &add2; + + default: + return NULL; } - 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[97.126.103.167]) by smtp.gmail.com with ESMTPSA id b22sm20382140pfh.175.2017.09.12.09.25.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 09:25:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IspWEzo06COifpC5ZCR3/665tlgv1GPpoBBrb2HBEic=; b=F4LoilmH48rhX2n33E7qAxr4CFbzNUltbkuXw6jfjcxe8e1H9ANq7u2aCJcR0vQ7EZ o+4BrzBubNi9WM6Rw3u/tH0eex0GhRSZ4n4qBTDp1Lf/tpimAqopqgCEuA2LlDIWVPF+ QZbjpivYB40mH4RfUSo0JMXC1JFczSQTvMLuU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IspWEzo06COifpC5ZCR3/665tlgv1GPpoBBrb2HBEic=; b=XqYA0bkcP7PNVVHPe8bD10AsrmkbSpkgCXwTgO07G/Gm61p9paQYQi0vlOii7Dqecm qj1AjSe0anIWBi1u3xVCRMIFv1hT+aRuHamh16Tot8Gu7lwpcBhpyEuAm3pLB8/2cQfd k/u6DZAJ5MVIFkQuCKafGeinAGYjS6QKDGjJuLL6KVqBubdOtoX6Wp8QTDD26JzpHQfw 7N3LNC0b7hm8/8reiAEKFpnGufV+5w9TrFWaKWjaGkjylqIiYVkdKYthfMjh4JoQwoRo EzfVStJuLPiD3JWingrMRsSFv/7q3sCt6JALI1o4G2kspoCJXL4dq9qYBpoD3mbw3XUl CDjQ== X-Gm-Message-State: AHPjjUgH3yYI9Me63813B/38ut4bi0DKpLBWvUoiEq747gZgFP4mNK8e qRtfl0wp8E+I5GyIm249aQ== X-Google-Smtp-Source: ADKCNb6p7oBwcH5U5GvHqr6FR5WOOIVIZqxc/7FcJTqUXIDvaq3NinRPO8vOBJ/5je1SNSLkLt5QYg== X-Received: by 10.99.186.91 with SMTP id l27mr15117979pgu.279.1505233530987; Tue, 12 Sep 2017 09:25:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Sep 2017 09:25:08 -0700 Message-Id: <20170912162513.21694-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170912162513.21694-1-richard.henderson@linaro.org> References: <20170912162513.21694-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH v2 11/16] tcg: Remove tcg_regset_clear X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.h | 1 - tcg/aarch64/tcg-target.inc.c | 2 +- tcg/arm/tcg-target.inc.c | 2 +- tcg/i386/tcg-target.inc.c | 4 ++-- tcg/mips/tcg-target.inc.c | 2 +- tcg/ppc/tcg-target.inc.c | 2 +- tcg/s390/tcg-target.inc.c | 8 ++++---- tcg/sparc/tcg-target.inc.c | 2 +- tcg/tcg.c | 5 ++--- tcg/tci/tcg-target.inc.c | 2 +- 10 files changed, 14 insertions(+), 16 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 37ad9fddab..7226727ee4 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -210,7 +210,6 @@ typedef enum TCGOpcode { NB_OPS, } TCGOpcode; =20 -#define tcg_regset_clear(d) (d) =3D 0 #define tcg_regset_set(d, s) (d) =3D (s) #define tcg_regset_set32(d, reg, val32) (d) |=3D (val32) << (reg) #define tcg_regset_set_reg(d, r) (d) |=3D 1L << (r) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 1ff32e43f5..141a86a57d 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1960,7 +1960,7 @@ static void tcg_target_init(TCGContext *s) (1 << TCG_REG_X16) | (1 << TCG_REG_X17) | (1 << TCG_REG_X18) | (1 << TCG_REG_X30)); =20 - tcg_regset_clear(s->reserved_regs); + s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index db46aea38c..f0c176554b 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -2173,7 +2173,7 @@ static void tcg_target_init(TCGContext *s) (1 << TCG_REG_R12) | (1 << TCG_REG_R14)); =20 - tcg_regset_clear(s->reserved_regs); + s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index fbb41c3b7a..e9766f6686 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2999,7 +2999,7 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V256], 0, 0xff= 0000); } =20 - tcg_regset_clear(tcg_target_call_clobber_regs); + tcg_target_call_clobber_regs =3D 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX); @@ -3014,7 +3014,7 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); } =20 - tcg_regset_clear(s->reserved_regs); + s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); } =20 diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 750baadf37..85c1abd14b 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -2629,7 +2629,7 @@ static void tcg_target_init(TCGContext *s) (1 << TCG_REG_T8) | (1 << TCG_REG_T9)); =20 - tcg_regset_clear(s->reserved_regs); + s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only= */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only= */ diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 21d764c102..b1df1e146a 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -2786,7 +2786,7 @@ static void tcg_target_init(TCGContext *s) (1 << TCG_REG_R11) | (1 << TCG_REG_R12)); =20 - tcg_regset_clear(s->reserved_regs); + s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ #if defined(_CALL_SYSV) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index e7ab8e4df3..01baa33673 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -413,12 +413,12 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, break; case 'a': /* force R2 for division */ ct->ct |=3D TCG_CT_REG; - tcg_regset_clear(ct->u.regs); + ct->u.regs =3D 0; tcg_regset_set_reg(ct->u.regs, TCG_REG_R2); break; case 'b': /* force R3 for division */ ct->ct |=3D TCG_CT_REG; - tcg_regset_clear(ct->u.regs); + ct->u.regs =3D 0; tcg_regset_set_reg(ct->u.regs, TCG_REG_R3); break; case 'A': @@ -2522,7 +2522,7 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); =20 - tcg_regset_clear(tcg_target_call_clobber_regs); + tcg_target_call_clobber_regs =3D 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); @@ -2535,7 +2535,7 @@ static void tcg_target_init(TCGContext *s) /* The return register can be considered call-clobbered. */ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); =20 - tcg_regset_clear(s->reserved_regs); + s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* XXX many insns can't be used with R0, so we better avoid it for now= */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index bd7c1461c6..ccd83205d5 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -1771,7 +1771,7 @@ static void tcg_target_init(TCGContext *s) (1 << TCG_REG_O5) | (1 << TCG_REG_O7)); =20 - tcg_regset_clear(s->reserved_regs); + s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_G6); /* reserved for os */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_G7); /* thread pointer */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 240bcaa8d5..f40cce3364 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1590,7 +1590,7 @@ static void process_op_defs(TCGContext *s) /* Incomplete TCGTargetOpDef entry. */ tcg_debug_assert(ct_str !=3D NULL); =20 - tcg_regset_clear(def->args_ct[i].u.regs); + def->args_ct[i].u.regs =3D 0; def->args_ct[i].ct =3D 0; while (*ct_str !=3D '\0') { switch(*ct_str) { @@ -2754,9 +2754,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, tcg_out_mov(s, ts->type, reg, ts->reg); } } else { - TCGRegSet arg_set; + TCGRegSet arg_set =3D 0; =20 - tcg_regset_clear(arg_set); tcg_regset_set_reg(arg_set, reg); temp_load(s, ts, arg_set, allocated_regs); } diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c index 94461b2baf..f9644334cc 100644 --- a/tcg/tci/tcg-target.inc.c +++ b/tcg/tci/tcg-target.inc.c @@ -879,7 +879,7 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set32(tcg_target_call_clobber_regs, 0, BIT(TCG_TARGET_NB_REGS) - 1); =20 - tcg_regset_clear(s->reserved_regs); + s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); =20 /* We use negative offsets from "sp" so that we can distinguish --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505234169158131.23293136991606; Tue, 12 Sep 2017 09:36:09 -0700 (PDT) Received: from localhost ([::1]:36974 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1droAS-0003Tf-AH for importer@patchew.org; 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X-Received-From: 2607:f8b0:400e:c05::22f Subject: [Qemu-devel] [PATCH v2 12/16] tcg: Remove tcg_regset_set X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.h | 1 - tcg/tcg.c | 8 ++++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 7226727ee4..e168bd2c44 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -210,7 +210,6 @@ typedef enum TCGOpcode { NB_OPS, } TCGOpcode; =20 -#define tcg_regset_set(d, s) (d) =3D (s) #define tcg_regset_set32(d, reg, val32) (d) |=3D (val32) << (reg) #define tcg_regset_set_reg(d, r) (d) |=3D 1L << (r) #define tcg_regset_reset_reg(d, r) (d) &=3D ~(1L << (r)) diff --git a/tcg/tcg.c b/tcg/tcg.c index f40cce3364..873915925f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2452,7 +2452,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOpDef *def, TCGTemp *ts, *ots; TCGType otype, itype; =20 - tcg_regset_set(allocated_regs, s->reserved_regs); + allocated_regs =3D s->reserved_regs; ots =3D &s->temps[args[0]]; ts =3D &s->temps[args[1]]; =20 @@ -2540,8 +2540,8 @@ static void tcg_reg_alloc_op(TCGContext *s, args + nb_oargs + nb_iargs,=20 sizeof(TCGArg) * def->nb_cargs); =20 - tcg_regset_set(i_allocated_regs, s->reserved_regs); - tcg_regset_set(o_allocated_regs, s->reserved_regs); + i_allocated_regs =3D s->reserved_regs; + o_allocated_regs =3D s->reserved_regs; =20 /* satisfy input constraints */=20 for(k =3D 0; k < nb_iargs; k++) { @@ -2741,7 +2741,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, } =20 /* assign input registers */ - tcg_regset_set(allocated_regs, s->reserved_regs); + allocated_regs =3D s->reserved_regs; for(i =3D 0; i < nb_regs; i++) { arg =3D args[nb_oargs + i]; if (arg !=3D TCG_CALL_DUMMY_ARG) { --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505233793449816.8213184457832; Tue, 12 Sep 2017 09:29:53 -0700 (PDT) Received: from localhost ([::1]:36899 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro4O-00060r-CA for importer@patchew.org; Tue, 12 Sep 2017 12:29:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38153) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro0F-0001rP-Vx for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dro0F-00079m-1m for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:35 -0400 Received: from mail-pf0-x232.google.com ([2607:f8b0:400e:c00::232]:33036) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dro0E-000799-T2 for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:34 -0400 Received: by mail-pf0-x232.google.com with SMTP id y29so18669343pff.0 for ; Tue, 12 Sep 2017 09:25:34 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::232 Subject: [Qemu-devel] [PATCH v2 13/16] tcg: Remove tcg_regset_{or, and, andnot, not} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.h | 4 ---- tcg/tcg.c | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index e168bd2c44..8b4208ea03 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -214,10 +214,6 @@ typedef enum TCGOpcode { #define tcg_regset_set_reg(d, r) (d) |=3D 1L << (r) #define tcg_regset_reset_reg(d, r) (d) &=3D ~(1L << (r)) #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) -#define tcg_regset_or(d, a, b) (d) =3D (a) | (b) -#define tcg_regset_and(d, a, b) (d) =3D (a) & (b) -#define tcg_regset_andnot(d, a, b) (d) =3D (a) & ~(b) -#define tcg_regset_not(d, a) (d) =3D ~(a) =20 #ifndef TCG_TARGET_INSN_UNIT_SIZE # error "Missing TCG_TARGET_INSN_UNIT_SIZE" diff --git a/tcg/tcg.c b/tcg/tcg.c index 873915925f..a19767b5ef 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2306,7 +2306,7 @@ static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet = desired_regs, TCGReg reg; TCGRegSet reg_ct; =20 - tcg_regset_andnot(reg_ct, desired_regs, allocated_regs); + reg_ct =3D desired_regs & ~allocated_regs; order =3D rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; =20 /* first try free registers */ --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150523431118291.82461716074454; Tue, 12 Sep 2017 09:38:31 -0700 (PDT) Received: from localhost ([::1]:37032 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1droCk-0005jJ-Ad for importer@patchew.org; Tue, 12 Sep 2017 12:38:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38203) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro0J-0001vG-Oi for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dro0G-0007Au-Tf for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:39 -0400 Received: from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:33743) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dro0G-0007AM-KH for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:36 -0400 Received: by mail-pg0-x22c.google.com with SMTP id u18so5584034pgo.0 for ; Tue, 12 Sep 2017 09:25:36 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net. [97.126.103.167]) by smtp.gmail.com with ESMTPSA id b22sm20382140pfh.175.2017.09.12.09.25.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 09:25:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ByrsgJ8FtPrTiASw92OO8jQubvxKAZodnvnQPQHSMTM=; b=ZsFp2TuH9MnQ7kuey8rTzb+jjwia/9hxtUmvkjPD8ZOHJtWxI2QRmUsEk+gl9FyzGZ kYG6VSw9bE3h50l2wcAuqwsRHPLj52OhP/1mdDbrt72CRvhwhB/LeuJHGwqHbIInoX5+ OHPf9LdAH3BI1b0ArdP8xzaYz/sNQGgCEsxQo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ByrsgJ8FtPrTiASw92OO8jQubvxKAZodnvnQPQHSMTM=; b=RO4ly7dJK1DihFWnJi5/AIo5qxOOgrFxytcWTibWdUHihPoTTnbaDsweQHhhlq+Njv 0P6i0A1eot8fjFhcrnQwNt7atYxZm8Rn3N4N6oT1HAMerSfDqtPK2rgNoJNFnd6Pyxd+ IhspPr0bfFkQZb4Vkubmv0DNorHi9GnnoG4qbJ4+HiLCaZ5eVll/rbghnEkr+Gn5Phiq NI2V2g/n3T4DRXT8uDwgHtSn8W1dhmMn2KX3y+fQsF6xsdp/L6OVV3CvXJA0hhthr9v3 bzYBZk/owceDB3bzLMrbdnYsUpdF3eBjIJRyZi4DSjzXvjVoYzARdoH1nWCiH40ayt2t OxGQ== X-Gm-Message-State: AHPjjUg3CTazA/ryAQuvzVCtOLJPjeGvztliCj4l6UmOxmWiWKJL3ycH YXJ8OQzDALV4zkQsJFFmng== X-Google-Smtp-Source: ADKCNb5AmL1RquRpvVOalwUV84liy4isqe4sNh5O7gOIgdMFED9Eg9UZt4ttleFMazcrKJuG77HvQw== X-Received: by 10.98.236.198 with SMTP id e67mr15302570pfm.157.1505233535031; Tue, 12 Sep 2017 09:25:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Sep 2017 09:25:11 -0700 Message-Id: <20170912162513.21694-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170912162513.21694-1-richard.henderson@linaro.org> References: <20170912162513.21694-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PATCH v2 14/16] tcg: Remove tcg_regset_set32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" It's not even clear what the interface REG and VAL32 were supposed to mean. All uses had REG =3D 0 and VAL32 was the bitset assigned to the destination. Signed-off-by: Richard Henderson --- tcg/tcg.h | 1 - tcg/aarch64/tcg-target.inc.c | 33 +++++++++++++++--------------- tcg/arm/tcg-target.inc.c | 23 +++++++++++---------- tcg/i386/tcg-target.inc.c | 34 ++++++++++--------------------- tcg/ppc/tcg-target.inc.c | 37 +++++++++++++++++----------------- tcg/s390/tcg-target.inc.c | 14 ++++++------- tcg/sparc/tcg-target.inc.c | 48 ++++++++++++++++++++++------------------= ---- tcg/tci/tcg-target.inc.c | 11 ++++------ 8 files changed, 94 insertions(+), 107 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 8b4208ea03..d4412102ba 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -210,7 +210,6 @@ typedef enum TCGOpcode { NB_OPS, } TCGOpcode; =20 -#define tcg_regset_set32(d, reg, val32) (d) |=3D (val32) << (reg) #define tcg_regset_set_reg(d, r) (d) |=3D 1L << (r) #define tcg_regset_reset_reg(d, r) (d) &=3D ~(1L << (r)) #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 141a86a57d..150530f30e 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -121,11 +121,11 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, switch (*ct_str++) { case 'r': ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, (1ULL << TCG_TARGET_NB_REGS) - 1); + ct->u.regs =3D 0xffffffffu; break; case 'l': /* qemu_ld / qemu_st address, data_reg */ ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, (1ULL << TCG_TARGET_NB_REGS) - 1); + ct->u.regs =3D 0xffffffffu; #ifdef CONFIG_SOFTMMU /* x0 and x1 will be overwritten when reading the tlb entry, and x2, and x3 for helper args, better to avoid using them. */ @@ -1945,20 +1945,21 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) =20 static void tcg_target_init(TCGContext *s) { - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xfffffff= f); - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xfffffff= f); - - tcg_regset_set32(tcg_target_call_clobber_regs, 0, - (1 << TCG_REG_X0) | (1 << TCG_REG_X1) | - (1 << TCG_REG_X2) | (1 << TCG_REG_X3) | - (1 << TCG_REG_X4) | (1 << TCG_REG_X5) | - (1 << TCG_REG_X6) | (1 << TCG_REG_X7) | - (1 << TCG_REG_X8) | (1 << TCG_REG_X9) | - (1 << TCG_REG_X10) | (1 << TCG_REG_X11) | - (1 << TCG_REG_X12) | (1 << TCG_REG_X13) | - (1 << TCG_REG_X14) | (1 << TCG_REG_X15) | - (1 << TCG_REG_X16) | (1 << TCG_REG_X17) | - (1 << TCG_REG_X18) | (1 << TCG_REG_X30)); + tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffffu; + tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffffu; + + tcg_target_call_clobber_regs =3D 0xfffffffu; + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X19); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X20); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X21); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X22); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X23); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X24); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X25); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X26); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X27); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X28); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X29); =20 s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index f0c176554b..14599a8685 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -264,13 +264,13 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, =20 case 'r': ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); + ct->u.regs =3D 0xffff; break; =20 /* qemu_ld address */ case 'l': ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); + ct->u.regs =3D 0xffff; #ifdef CONFIG_SOFTMMU /* r0-r2,lr will be overwritten when reading the tlb entry, so don't use these. */ @@ -284,7 +284,7 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, /* qemu_st address & data */ case 's': ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); + ct->u.regs =3D 0xffff; /* r0-r2 will be overwritten when reading the tlb entry (softmmu o= nly) and r0-r1 doing the byte swapping, so don't use these. */ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); @@ -2164,14 +2164,15 @@ static void tcg_target_init(TCGContext *s) } } =20 - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); - tcg_regset_set32(tcg_target_call_clobber_regs, 0, - (1 << TCG_REG_R0) | - (1 << TCG_REG_R1) | - (1 << TCG_REG_R2) | - (1 << TCG_REG_R3) | - (1 << TCG_REG_R12) | - (1 << TCG_REG_R14)); + tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffff; + + tcg_target_call_clobber_regs =3D 0; + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); =20 s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index e9766f6686..feb490019b 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -213,25 +213,17 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, case 'q': /* A register that can be used as a byte operand. */ ct->ct |=3D TCG_CT_REG; - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_regset_set32(ct->u.regs, 0, 0xffff); - } else { - tcg_regset_set32(ct->u.regs, 0, 0xf); - } + ct->u.regs =3D TCG_TARGET_REG_BITS =3D=3D 64 ? 0xffff : 0xf; break; case 'Q': /* A register with an addressable second byte (e.g. %ah). */ ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xf); + ct->u.regs =3D 0xf; break; case 'r': /* A general register. */ ct->ct |=3D TCG_CT_REG; - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_regset_set32(ct->u.regs, 0, 0xffff); - } else { - tcg_regset_set32(ct->u.regs, 0, 0xff); - } + ct->u.regs =3D TCG_TARGET_REG_BITS =3D=3D 64 ? 0xffff : 0xff; break; case 'W': /* With TZCNT/LZCNT, we can have operand-size as an input. */ @@ -240,17 +232,13 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, case 'x': /* A vector register. */ ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xff0000); + ct->u.regs =3D 0xff0000; break; =20 /* qemu_ld/st address constraint */ case 'L': ct->ct |=3D TCG_CT_REG; - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_regset_set32(ct->u.regs, 0, 0xffff); - } else { - tcg_regset_set32(ct->u.regs, 0, 0xff); - } + ct->u.regs =3D TCG_TARGET_REG_BITS =3D=3D 64 ? 0xffff : 0xff; tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); break; @@ -2986,17 +2974,17 @@ static void tcg_target_init(TCGContext *s) #endif /* CONFIG_CPUID_H */ =20 if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xfff= f); - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xfff= f); + tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffff; + tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffff; } else { - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff); + tcg_target_available_regs[TCG_TYPE_I32] =3D 0xff; } if (have_sse2) { - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V64], 0, 0xff0= 000); - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V128], 0, 0xff= 0000); + tcg_target_available_regs[TCG_TYPE_V64] =3D 0xff0000; + tcg_target_available_regs[TCG_TYPE_V128] =3D 0xff0000; } if (have_avx2) { - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_V256], 0, 0xff= 0000); + tcg_target_available_regs[TCG_TYPE_V256] =3D 0xff0000; } =20 tcg_target_call_clobber_regs =3D 0; diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index b1df1e146a..4212cba5fd 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -260,11 +260,11 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, break; case 'r': ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffffffff); + ct->u.regs =3D 0xffffffff; break; case 'L': /* qemu_ld constraint */ ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffffffff); + ct->u.regs =3D 0xffffffff; tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); #ifdef CONFIG_SOFTMMU tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); @@ -273,7 +273,7 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, break; case 'S': /* qemu_st constraint */ ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffffffff); + ct->u.regs =3D 0xffffffff; tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); #ifdef CONFIG_SOFTMMU tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); @@ -2770,21 +2770,22 @@ static void tcg_target_init(TCGContext *s) } #endif =20 - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xfffffff= f); - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xfffffff= f); - tcg_regset_set32(tcg_target_call_clobber_regs, 0, - (1 << TCG_REG_R0) | - (1 << TCG_REG_R2) | - (1 << TCG_REG_R3) | - (1 << TCG_REG_R4) | - (1 << TCG_REG_R5) | - (1 << TCG_REG_R6) | - (1 << TCG_REG_R7) | - (1 << TCG_REG_R8) | - (1 << TCG_REG_R9) | - (1 << TCG_REG_R10) | - (1 << TCG_REG_R11) | - (1 << TCG_REG_R12)); + tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; + tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; + + tcg_target_call_clobber_regs =3D 0; + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); =20 s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 01baa33673..38a7cdab75 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -402,14 +402,14 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, switch (*ct_str++) { case 'r': /* all registers */ ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffff); + ct->u.regs =3D 0xffff; break; case 'L': /* qemu_ld/st constraint */ ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffff); - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R2); - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3); - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); + ct->u.regs =3D 0xffff; + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); break; case 'a': /* force R2 for division */ ct->ct |=3D TCG_CT_REG; @@ -2519,8 +2519,8 @@ static void tcg_target_init(TCGContext *s) { query_s390_facilities(); =20 - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); + tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffff; + tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffff; =20 tcg_target_call_clobber_regs =3D 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index ccd83205d5..1da4debbaf 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -343,16 +343,15 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, switch (*ct_str++) { case 'r': ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffffffff); + ct->u.regs =3D 0xffffffff; break; case 'R': ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, ALL_64); + ct->u.regs =3D ALL_64; break; case 'A': /* qemu_ld/st address constraint */ ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, - TARGET_LONG_BITS =3D=3D 64 ? ALL_64 : 0xffffffff); + ct->u.regs =3D TARGET_LONG_BITS =3D=3D 64 ? ALL_64 : 0xffffffff; reserve_helpers: tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); @@ -360,11 +359,11 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, break; case 's': /* qemu_st data 32-bit constraint */ ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 0xffffffff); + ct->u.regs =3D 0xffffffff; goto reserve_helpers; case 'S': /* qemu_st data 64-bit constraint */ ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, ALL_64); + ct->u.regs =3D ALL_64; goto reserve_helpers; case 'I': ct->ct |=3D TCG_CT_CONST_S11; @@ -1752,24 +1751,25 @@ static void tcg_target_init(TCGContext *s) } #endif =20 - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xfffffff= f); - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, ALL_64); - - tcg_regset_set32(tcg_target_call_clobber_regs, 0, - (1 << TCG_REG_G1) | - (1 << TCG_REG_G2) | - (1 << TCG_REG_G3) | - (1 << TCG_REG_G4) | - (1 << TCG_REG_G5) | - (1 << TCG_REG_G6) | - (1 << TCG_REG_G7) | - (1 << TCG_REG_O0) | - (1 << TCG_REG_O1) | - (1 << TCG_REG_O2) | - (1 << TCG_REG_O3) | - (1 << TCG_REG_O4) | - (1 << TCG_REG_O5) | - (1 << TCG_REG_O7)); + tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; + tcg_target_available_regs[TCG_TYPE_I64] =3D ALL_64; + + tcg_target_call_clobber_regs =3D 0; + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_G7); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_O7); =20 s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); /* zero */ diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c index f9644334cc..913c3802a3 100644 --- a/tcg/tci/tcg-target.inc.c +++ b/tcg/tci/tcg-target.inc.c @@ -390,7 +390,7 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, case 'L': /* qemu_ld constraint */ case 'S': /* qemu_st constraint */ ct->ct |=3D TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, BIT(TCG_TARGET_NB_REGS) - 1); + ct->u.regs =3D BIT(TCG_TARGET_NB_REGS) - 1; break; default: return NULL; @@ -870,14 +870,11 @@ static void tcg_target_init(TCGContext *s) tcg_debug_assert(tcg_op_defs_max <=3D UINT8_MAX); =20 /* Registers available for 32 bit operations. */ - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, - BIT(TCG_TARGET_NB_REGS) - 1); + tcg_target_available_regs[TCG_TYPE_I32] =3D BIT(TCG_TARGET_NB_REGS) - = 1; /* Registers available for 64 bit operations. */ - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, - BIT(TCG_TARGET_NB_REGS) - 1); + tcg_target_available_regs[TCG_TYPE_I64] =3D BIT(TCG_TARGET_NB_REGS) - = 1; /* TODO: Which registers should be set here? */ - tcg_regset_set32(tcg_target_call_clobber_regs, 0, - BIT(TCG_TARGET_NB_REGS) - 1); + tcg_target_call_clobber_regs =3D BIT(TCG_TARGET_NB_REGS) - 1; =20 s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505234134928337.3332112316092; Tue, 12 Sep 2017 09:35:34 -0700 (PDT) Received: from localhost ([::1]:36968 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro9u-0002to-3V for importer@patchew.org; Tue, 12 Sep 2017 12:35:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38227) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro0M-0001y5-7t for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dro0I-0007Bl-5E for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:42 -0400 Received: from mail-pf0-x236.google.com ([2607:f8b0:400e:c00::236]:36711) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dro0H-0007Az-Fp for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:37 -0400 Received: by mail-pf0-x236.google.com with SMTP id e199so19406059pfh.3 for ; Tue, 12 Sep 2017 09:25:37 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net. [97.126.103.167]) by smtp.gmail.com with ESMTPSA id b22sm20382140pfh.175.2017.09.12.09.25.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 09:25:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=03UOSpg8PRz0Msrhor56twpaRVfPJZefeQoMqpA2HYA=; b=GvbWZ4GbyXZIoiim2KaUwBPSwM2cV+W8o9s3buZTUIkH/Ff0Jq5n2W7BZAqWFueoAj Q87VTOzCoV3WzTCkcUtH1ZWKeZz2dmE8FcP5+fQ+prDSwbantbJ/cUxs2ZIwpdZfESQm mFfAMZNGInOdC025Selp0QPN9uwdtDSiZopug= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=03UOSpg8PRz0Msrhor56twpaRVfPJZefeQoMqpA2HYA=; b=teyp536j1zuyMEBU7ENys7xDlISBRX9x5353rXUYm46a4ghzjRxMkzBfEQBN6kOY2T mCv8bLtPUYT4f2NLmUgo5URzpXa/uwX62evGy7SWAGT4Jc382bp9Prnh6k7rt2GahSvf qKhi56+Xm5/hueMZ8AQDT1+b8k4JIFul/WL+8E3bZzcLqoZgLtpobYOYHVOE6uIILr8+ 2HE1OfcPkUdyMlU92/M2s9XBMcZOc7ok16aMN4YAyd38RbVwu8juDtAzKpy2YCJePKNX DdQGDCDs0IoFSbWKvc7Lwfea6D0TPDG6vadW3MLute4bZ3fk+IobG8oO1fKAFjjRXyxy q19g== X-Gm-Message-State: AHPjjUio+brQAFvU3JQx3cVTQEtDhK0NSoH5ZY49TqRF2bSN/p4/vAlI MsRwX0PoyVGP3z0Or5QJ0Q== X-Google-Smtp-Source: ADKCNb42vtz3tAw/C6mKTcFnU22PUenbVUhbZvKOVNwA1ctBzx9jrXYZW4oRZ6ltqOOrY1nMSTqn/A== X-Received: by 10.99.120.3 with SMTP id t3mr15235782pgc.388.1505233536341; Tue, 12 Sep 2017 09:25:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Sep 2017 09:25:12 -0700 Message-Id: <20170912162513.21694-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170912162513.21694-1-richard.henderson@linaro.org> References: <20170912162513.21694-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PATCH v2 15/16] tcg: Fix types in tcg_regset_{set, reset}_reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There was a problem here with an ILP32 host with 64 host registers. E.g. aarch64 running in ILP32 mode. Signed-off-by: Richard Henderson --- tcg/tcg.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index d4412102ba..c5ada53358 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -210,9 +210,9 @@ typedef enum TCGOpcode { NB_OPS, } TCGOpcode; =20 -#define tcg_regset_set_reg(d, r) (d) |=3D 1L << (r) -#define tcg_regset_reset_reg(d, r) (d) &=3D ~(1L << (r)) -#define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) +#define tcg_regset_set_reg(d, r) ((d) |=3D (TCGRegSet)1 << (r)) +#define tcg_regset_reset_reg(d, r) ((d) &=3D ~((TCGRegSet)1 << (r))) +#define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) =20 #ifndef TCG_TARGET_INSN_UNIT_SIZE # error "Missing TCG_TARGET_INSN_UNIT_SIZE" --=20 2.13.5 From nobody Tue Nov 4 00:13:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505234340882901.343245549474; Tue, 12 Sep 2017 09:39:00 -0700 (PDT) Received: from localhost ([::1]:37033 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1droDC-0006BN-WA for importer@patchew.org; Tue, 12 Sep 2017 12:38:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38229) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dro0M-0001y7-96 for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dro0J-0007CI-Di for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:42 -0400 Received: from mail-pg0-x22b.google.com ([2607:f8b0:400e:c05::22b]:37517) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dro0J-0007C0-2R for qemu-devel@nongnu.org; Tue, 12 Sep 2017 12:25:39 -0400 Received: by mail-pg0-x22b.google.com with SMTP id d8so22189894pgt.4 for ; Tue, 12 Sep 2017 09:25:38 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net. [97.126.103.167]) by smtp.gmail.com with ESMTPSA id b22sm20382140pfh.175.2017.09.12.09.25.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 09:25:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Revpy4uE5bdOi82L4qVMZbsXEwMBbKX/a7uzM3Um9Ko=; b=dawv6mtr8jwtzJIadXoKrz4iTYpLhpQOzxhdwEbv7F4DgEQ9UsVIrR76mAY1IzzSRK SjrWsLvTRwfmVNfgRX2lxJsMC0QoICg/yY4A34jJoF7h7PWvc/ZdF3bqbksMbyAK71TV kyZQzwLZi0HS8JHSDj/b6g8Y/GN6pmFj3z/Uo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Revpy4uE5bdOi82L4qVMZbsXEwMBbKX/a7uzM3Um9Ko=; b=dhbcorIfpySLB29K1g2zAqPYOTBWHiGLtdNE1ZeP81tBtnQjw0lxH3BN1jB5UD0Faf MsmVs2v/4eoBW8j8e+3Px/FSd/wRyRJ8gP+Ti3wqU6eT/TKKMMZLlf6PE4G+WAPuELCU G5bjqcKcD1VuIKsXolhlAOsyxfw814YJy8iPT61EHMaSJo5Emp6E9el4Kd5MVRLY9C/H HhmaOG3TM9eymuVLdxXqUeZhTPdMQFm/kIETLcqUaMm/U0q7hRtjRha57MoQNcjdU1xT E889/qxksNlu6b4I1vZcJKgP5k7qfG7zonnpoSeSWETCmEheTkz++ltSbVdb1CKVjMTE fLpA== X-Gm-Message-State: AHPjjUgjPQURQLonj9fpoxsozMWcF/NgK1SM1/xIisTp1maDju+fANUj XG5K8LWfc3mjwaRD0kjc1A== X-Google-Smtp-Source: ADKCNb7iIAbmnywK/Xlu4VaQLshbCTPKwcpsE4dmWsOOLNwJ7DKqiI9l3l1KNIj+PDxlvHBz7hZsew== X-Received: by 10.98.60.220 with SMTP id b89mr15201435pfk.82.1505233537541; Tue, 12 Sep 2017 09:25:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 12 Sep 2017 09:25:13 -0700 Message-Id: <20170912162513.21694-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170912162513.21694-1-richard.henderson@linaro.org> References: <20170912162513.21694-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22b Subject: [Qemu-devel] [PATCH v2 16/16] tcg/aarch64: Add vector operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 23 ++- tcg/aarch64/tcg-target.inc.c | 372 ++++++++++++++++++++++++++++++++++++++-= ---- 2 files changed, 350 insertions(+), 45 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index c2525066ab..310efa3c1d 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -31,13 +31,22 @@ typedef enum { TCG_REG_SP =3D 31, TCG_REG_XZR =3D 31, =20 + TCG_REG_V0 =3D 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, + TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, + TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, + TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, + TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, + TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, + TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, + TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, + /* Aliases. */ TCG_REG_FP =3D TCG_REG_X29, TCG_REG_LR =3D TCG_REG_X30, TCG_AREG0 =3D TCG_REG_X19, } TCGReg; =20 -#define TCG_TARGET_NB_REGS 32 +#define TCG_TARGET_NB_REGS 64 =20 /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_SP @@ -113,6 +122,18 @@ typedef enum { #define TCG_TARGET_HAS_mulsh_i64 1 #define TCG_TARGET_HAS_direct_jump 1 =20 +#define TCG_TARGET_HAS_v64 1 +#define TCG_TARGET_HAS_andc_v64 1 +#define TCG_TARGET_HAS_orc_v64 1 +#define TCG_TARGET_HAS_not_v64 1 +#define TCG_TARGET_HAS_neg_v64 1 + +#define TCG_TARGET_HAS_v128 1 +#define TCG_TARGET_HAS_andc_v128 1 +#define TCG_TARGET_HAS_orc_v128 1 +#define TCG_TARGET_HAS_not_v128 1 +#define TCG_TARGET_HAS_neg_v128 1 + #define TCG_TARGET_DEFAULT_MO (0) =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 150530f30e..a2419dcb0c 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -20,10 +20,15 @@ QEMU_BUILD_BUG_ON(TCG_TYPE_I32 !=3D 0 || TCG_TYPE_I64 != =3D 1); =20 #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { - "%x0", "%x1", "%x2", "%x3", "%x4", "%x5", "%x6", "%x7", - "%x8", "%x9", "%x10", "%x11", "%x12", "%x13", "%x14", "%x15", - "%x16", "%x17", "%x18", "%x19", "%x20", "%x21", "%x22", "%x23", - "%x24", "%x25", "%x26", "%x27", "%x28", "%fp", "%x30", "%sp", + "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", + "x24", "x25", "x26", "x27", "x28", "fp", "x30", "sp", + + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "fp", "v30", "v31", }; #endif /* CONFIG_DEBUG_TCG */ =20 @@ -43,6 +48,14 @@ static const int tcg_target_reg_alloc_order[] =3D { /* X19 reserved for AREG0 */ /* X29 reserved as fp */ /* X30 reserved as temporary */ + + TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, + TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, + /* V8 - V15 are call-saved, and skipped. */ + TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, + TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, + TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, + TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, }; =20 static const int tcg_target_call_iarg_regs[8] =3D { @@ -119,10 +132,14 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, const char *ct_str, TCGType typ= e) { switch (*ct_str++) { - case 'r': + case 'r': /* general registers */ ct->ct |=3D TCG_CT_REG; ct->u.regs =3D 0xffffffffu; break; + case 'w': /* advsimd registers */ + ct->ct |=3D TCG_CT_REG; + ct->u.regs =3D 0xffffffff00000000ull; + break; case 'l': /* qemu_ld / qemu_st address, data_reg */ ct->ct |=3D TCG_CT_REG; ct->u.regs =3D 0xffffffffu; @@ -290,6 +307,12 @@ typedef enum { I3312_LDRSHX =3D 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30, I3312_LDRSWX =3D 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30, =20 + I3312_LDRVD =3D 0x3c000000 | LDST_LD << 22 | MO_64 << 30, + I3312_STRVD =3D 0x3c000000 | LDST_ST << 22 | MO_64 << 30, + + I3312_LDRVQ =3D 0x3c000000 | 3 << 22 | 0 << 30, + I3312_STRVQ =3D 0x3c000000 | 2 << 22 | 0 << 30, + I3312_TO_I3310 =3D 0x00200800, I3312_TO_I3313 =3D 0x01000000, =20 @@ -374,8 +397,33 @@ typedef enum { I3510_EON =3D 0x4a200000, I3510_ANDS =3D 0x6a000000, =20 - NOP =3D 0xd503201f, + /* AdvSIMD modified immediate */ + I3606_MOVI =3D 0x0f000400, + + /* AdvSIMD three same. */ + I3616_ADD_B =3D 0x0e208400, + I3616_ADD_H =3D 0x0e608400, + I3616_ADD_S =3D 0x0ea08400, + I3616_ADD_D =3D 0x4ee08400, + I3616_AND =3D 0x0e201c00, + I3616_BIC =3D 0x0e601c00, + I3616_EOR =3D 0x2e201c00, + I3616_ORR =3D 0x0ea01c00, + I3616_ORN =3D 0x0ee01c00, + I3616_SUB_B =3D 0x2e208400, + I3616_SUB_H =3D 0x2e608400, + I3616_SUB_S =3D 0x2ea08400, + I3616_SUB_D =3D 0x6ee08400, + + /* AdvSIMD two-reg misc. */ + I3617_NOT =3D 0x2e205800, + I3617_NEG_B =3D 0x2e20b800, + I3617_NEG_H =3D 0x2e60b800, + I3617_NEG_S =3D 0x2ea0b800, + I3617_NEG_D =3D 0x6ee0b800, + /* System instructions. */ + NOP =3D 0xd503201f, DMB_ISH =3D 0xd50338bf, DMB_LD =3D 0x00000100, DMB_ST =3D 0x00000200, @@ -520,26 +568,47 @@ static void tcg_out_insn_3509(TCGContext *s, AArch64I= nsn insn, TCGType ext, tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd); } =20 +static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q, + TCGReg rd, bool op, int cmode, uint8_t imm8) +{ + tcg_out32(s, insn | q << 30 | op << 29 | cmode << 12 | (rd & 0x1f) + | (imm8 & 0xe0) << 16 | (imm8 & 0x1f) << 5); +} + +static void tcg_out_insn_3616(TCGContext *s, AArch64Insn insn, bool q, + TCGReg rd, TCGReg rn, TCGReg rm) +{ + tcg_out32(s, insn | q << 30 | (rm & 0x1f) << 16 + | (rn & 0x1f) << 5 | (rd & 0x1f)); +} + +static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q, + TCGReg rd, TCGReg rn) +{ + tcg_out32(s, insn | q << 30 | (rn & 0x1f) << 5 | (rd & 0x1f)); +} + static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn, TCGReg rd, TCGReg base, TCGType ext, TCGReg regoff) { /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 | - 0x4000 | ext << 13 | base << 5 | rd); + 0x4000 | ext << 13 | base << 5 | (rd & 0x1f)); } =20 static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn, TCGReg rd, TCGReg rn, intptr_t offset) { - tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | rd); + tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f)); } =20 static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn, TCGReg rd, TCGReg rn, uintptr_t scaled_uimm) { /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ - tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10 | rn << 5 | rd); + tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10 + | rn << 5 | (rd & 0x1f)); } =20 /* Register to register move using ORR (shifted register with no shift). */ @@ -594,6 +663,24 @@ static void tcg_out_movi(TCGContext *s, TCGType type, = TCGReg rd, int s0, s1; AArch64Insn opc; =20 + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_I64: + tcg_debug_assert(rd < 32); + break; + + case TCG_TYPE_V64: + case TCG_TYPE_V128: + tcg_debug_assert(rd >=3D 32); + /* ??? Revisit this as the implementation progresses. */ + tcg_debug_assert(value =3D=3D 0); + tcg_out_insn(s, 3606, MOVI, 0, rd, 0, 0, 0); + return; + + default: + g_assert_not_reached(); + } + /* For 32-bit values, discard potential garbage in value. For 64-bit values within [2**31, 2**32-1], we can create smaller sequences by interpreting this as a negative 32-bit number, while ensuring that @@ -669,15 +756,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type,= TCGReg rd, /* Define something more legible for general use. */ #define tcg_out_ldst_r tcg_out_insn_3310 =20 -static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, - TCGReg rd, TCGReg rn, intptr_t offset) +static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd, + TCGReg rn, intptr_t offset, int lgsize) { - TCGMemOp size =3D (uint32_t)insn >> 30; - /* If the offset is naturally aligned and in range, then we can use the scaled uimm12 encoding */ - if (offset >=3D 0 && !(offset & ((1 << size) - 1))) { - uintptr_t scaled_uimm =3D offset >> size; + if (offset >=3D 0 && !(offset & ((1 << lgsize) - 1))) { + uintptr_t scaled_uimm =3D offset >> lgsize; if (scaled_uimm <=3D 0xfff) { tcg_out_insn_3313(s, insn, rd, rn, scaled_uimm); return; @@ -695,32 +780,94 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn i= nsn, tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP); } =20 -static inline void tcg_out_mov(TCGContext *s, - TCGType type, TCGReg ret, TCGReg arg) +static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) { - if (ret !=3D arg) { + if (ret =3D=3D arg) { + return; + } + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_I64: + tcg_debug_assert(ret < 32 && arg < 32); tcg_out_movr(s, type, ret, arg); + break; + + case TCG_TYPE_V64: + tcg_debug_assert(ret >=3D 32 && arg >=3D 32); + tcg_out_insn(s, 3616, ORR, 0, ret, arg, arg); + break; + case TCG_TYPE_V128: + tcg_debug_assert(ret >=3D 32 && arg >=3D 32); + tcg_out_insn(s, 3616, ORR, 1, ret, arg, arg); + break; + + default: + g_assert_not_reached(); } } =20 -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { - tcg_out_ldst(s, type =3D=3D TCG_TYPE_I32 ? I3312_LDRW : I3312_LDRX, - arg, arg1, arg2); + AArch64Insn insn; + int lgsz; + + switch (type) { + case TCG_TYPE_I32: + insn =3D I3312_LDRW; + lgsz =3D 2; + break; + case TCG_TYPE_I64: + insn =3D I3312_LDRX; + lgsz =3D 3; + break; + case TCG_TYPE_V64: + insn =3D I3312_LDRVD; + lgsz =3D 3; + break; + case TCG_TYPE_V128: + insn =3D I3312_LDRVQ; + lgsz =3D 4; + break; + default: + g_assert_not_reached(); + } + tcg_out_ldst(s, insn, arg, arg1, arg2, lgsz); } =20 -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { - tcg_out_ldst(s, type =3D=3D TCG_TYPE_I32 ? I3312_STRW : I3312_STRX, - arg, arg1, arg2); + AArch64Insn insn; + int lgsz; + + switch (type) { + case TCG_TYPE_I32: + insn =3D I3312_STRW; + lgsz =3D 2; + break; + case TCG_TYPE_I64: + insn =3D I3312_STRX; + lgsz =3D 3; + break; + case TCG_TYPE_V64: + insn =3D I3312_STRVD; + lgsz =3D 3; + break; + case TCG_TYPE_V128: + insn =3D I3312_STRVQ; + lgsz =3D 4; + break; + default: + g_assert_not_reached(); + } + tcg_out_ldst(s, insn, arg, arg1, arg2, lgsz); } =20 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, TCGReg base, intptr_t ofs) { - if (val =3D=3D 0) { + if (type <=3D TCG_TYPE_I64 && val =3D=3D 0) { tcg_out_st(s, type, TCG_REG_XZR, base, ofs); return true; } @@ -1210,14 +1357,15 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg = addr_reg, TCGMemOp opc, /* Merge "low bits" from tlb offset, load the tlb comparator into X0. X0 =3D load [X2 + (tlb_offset & 0x000fff)] */ tcg_out_ldst(s, TARGET_LONG_BITS =3D=3D 32 ? I3312_LDRW : I3312_LDRX, - TCG_REG_X0, TCG_REG_X2, tlb_offset & 0xfff); + TCG_REG_X0, TCG_REG_X2, tlb_offset & 0xfff, + TARGET_LONG_BITS =3D=3D 32 ? 2 : 3); =20 /* Load the tlb addend. Do that early to avoid stalling. X1 =3D load [X2 + (tlb_offset & 0xfff) + offsetof(addend)] */ tcg_out_ldst(s, I3312_LDRX, TCG_REG_X1, TCG_REG_X2, (tlb_offset & 0xfff) + (offsetof(CPUTLBEntry, addend)) - (is_read ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write))); + : offsetof(CPUTLBEntry, addr_write)), 3); =20 /* Perform the address comparison. */ tcg_out_cmp(s, (TARGET_LONG_BITS =3D=3D 64), TCG_REG_X0, TCG_REG_X3, 0= ); @@ -1435,49 +1583,49 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 case INDEX_op_ld8u_i32: case INDEX_op_ld8u_i64: - tcg_out_ldst(s, I3312_LDRB, a0, a1, a2); + tcg_out_ldst(s, I3312_LDRB, a0, a1, a2, 0); break; case INDEX_op_ld8s_i32: - tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2); + tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2, 0); break; case INDEX_op_ld8s_i64: - tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2); + tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2, 0); break; case INDEX_op_ld16u_i32: case INDEX_op_ld16u_i64: - tcg_out_ldst(s, I3312_LDRH, a0, a1, a2); + tcg_out_ldst(s, I3312_LDRH, a0, a1, a2, 1); break; case INDEX_op_ld16s_i32: - tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2); + tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2, 1); break; case INDEX_op_ld16s_i64: - tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2); + tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2, 1); break; case INDEX_op_ld_i32: case INDEX_op_ld32u_i64: - tcg_out_ldst(s, I3312_LDRW, a0, a1, a2); + tcg_out_ldst(s, I3312_LDRW, a0, a1, a2, 2); break; case INDEX_op_ld32s_i64: - tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2); + tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2, 2); break; case INDEX_op_ld_i64: - tcg_out_ldst(s, I3312_LDRX, a0, a1, a2); + tcg_out_ldst(s, I3312_LDRX, a0, a1, a2, 3); break; =20 case INDEX_op_st8_i32: case INDEX_op_st8_i64: - tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2); + tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2, 0); break; case INDEX_op_st16_i32: case INDEX_op_st16_i64: - tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2); + tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2, 1); break; case INDEX_op_st_i32: case INDEX_op_st32_i64: - tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2); + tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2, 2); break; case INDEX_op_st_i64: - tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2); + tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2, 3); break; =20 case INDEX_op_add_i32: @@ -1774,13 +1922,93 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_mb(s, a0); break; =20 + case INDEX_op_ld_v64: + tcg_out_ldst(s, I3312_LDRVD, a0, a1, a2, 3); + break; + case INDEX_op_ld_v128: + tcg_out_ldst(s, I3312_LDRVQ, a0, a1, a2, 4); + break; + case INDEX_op_st_v64: + tcg_out_ldst(s, I3312_STRVD, a0, a1, a2, 3); + break; + case INDEX_op_st_v128: + tcg_out_ldst(s, I3312_STRVQ, a0, a1, a2, 4); + break; + +#define VOP(NAME) case INDEX_op_##NAME##_v128: ext =3D 1; /* fallthru */ \ + case INDEX_op_##NAME##_v64 + + VOP(add8): + tcg_out_insn(s, 3616, ADD_B, ext, a0, a1, a2); + break; + VOP(add16): + tcg_out_insn(s, 3616, ADD_H, ext, a0, a1, a2); + break; + VOP(add32): + tcg_out_insn(s, 3616, ADD_S, ext, a0, a1, a2); + break; + case INDEX_op_add64_v128: + tcg_out_insn(s, 3616, ADD_D, 1, a0, a1, a2); + break; + + VOP(sub8): + tcg_out_insn(s, 3616, SUB_B, ext, a0, a1, a2); + break; + VOP(sub16): + tcg_out_insn(s, 3616, SUB_H, ext, a0, a1, a2); + break; + VOP(sub32): + tcg_out_insn(s, 3616, SUB_S, ext, a0, a1, a2); + break; + case INDEX_op_sub64_v128: + tcg_out_insn(s, 3616, SUB_D, 1, a0, a1, a2); + break; + + VOP(neg8): + tcg_out_insn(s, 3617, NEG_B, ext, a0, a1); + break; + VOP(neg16): + tcg_out_insn(s, 3617, NEG_H, ext, a0, a1); + break; + VOP(neg32): + tcg_out_insn(s, 3617, NEG_S, ext, a0, a1); + break; + case INDEX_op_neg64_v128: + tcg_out_insn(s, 3617, NEG_D, 1, a0, a1); + break; + + VOP(and): + tcg_out_insn(s, 3616, AND, ext, a0, a1, a2); + break; + VOP(or): + tcg_out_insn(s, 3616, ORR, ext, a0, a1, a2); + break; + VOP(xor): + tcg_out_insn(s, 3616, EOR, ext, a0, a1, a2); + break; + VOP(andc): + tcg_out_insn(s, 3616, BIC, ext, a0, a1, a2); + break; + VOP(orc): + tcg_out_insn(s, 3616, ORN, ext, a0, a1, a2); + break; + VOP(not): + tcg_out_insn(s, 3617, NOT, ext, a0, a1); + break; + +#undef VOP + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: + case INDEX_op_mov_v64: + case INDEX_op_mov_v128: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_movi_i64: + case INDEX_op_movi_v64: + case INDEX_op_movi_v128: case INDEX_op_call: /* Always emitted via tcg_out_call. */ default: - tcg_abort(); + g_assert_not_reached(); } =20 #undef REG0 @@ -1790,11 +2018,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) { static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; + static const TCGTargetOpDef w_w =3D { .args_ct_str =3D { "w", "w" } }; + static const TCGTargetOpDef w_r =3D { .args_ct_str =3D { "w", "r" } }; static const TCGTargetOpDef r_l =3D { .args_ct_str =3D { "r", "l" } }; static const TCGTargetOpDef r_rA =3D { .args_ct_str =3D { "r", "rA" } = }; static const TCGTargetOpDef rZ_r =3D { .args_ct_str =3D { "rZ", "r" } = }; static const TCGTargetOpDef lZ_l =3D { .args_ct_str =3D { "lZ", "l" } = }; static const TCGTargetOpDef r_r_r =3D { .args_ct_str =3D { "r", "r", "= r" } }; + static const TCGTargetOpDef w_w_w =3D { .args_ct_str =3D { "w", "w", "= w" } }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; static const TCGTargetOpDef r_r_rA =3D { .args_ct_str =3D { "r", "r", = "rA" } }; static const TCGTargetOpDef r_r_rL =3D { .args_ct_str =3D { "r", "r", = "rL" } }; @@ -1938,6 +2169,49 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_sub2_i64: return &add2; =20 + case INDEX_op_add8_v64: + case INDEX_op_add16_v64: + case INDEX_op_add32_v64: + case INDEX_op_add8_v128: + case INDEX_op_add16_v128: + case INDEX_op_add32_v128: + case INDEX_op_add64_v128: + case INDEX_op_sub8_v64: + case INDEX_op_sub16_v64: + case INDEX_op_sub32_v64: + case INDEX_op_sub8_v128: + case INDEX_op_sub16_v128: + case INDEX_op_sub32_v128: + case INDEX_op_sub64_v128: + case INDEX_op_and_v64: + case INDEX_op_and_v128: + case INDEX_op_or_v64: + case INDEX_op_or_v128: + case INDEX_op_xor_v64: + case INDEX_op_xor_v128: + case INDEX_op_andc_v64: + case INDEX_op_andc_v128: + case INDEX_op_orc_v64: + case INDEX_op_orc_v128: + return &w_w_w; + + case INDEX_op_not_v64: + case INDEX_op_not_v128: + case INDEX_op_neg8_v64: + case INDEX_op_neg16_v64: + case INDEX_op_neg32_v64: + case INDEX_op_neg8_v128: + case INDEX_op_neg16_v128: + case INDEX_op_neg32_v128: + case INDEX_op_neg64_v128: + return &w_w; + + case INDEX_op_ld_v64: + case INDEX_op_ld_v128: + case INDEX_op_st_v64: + case INDEX_op_st_v128: + return &w_r; + default: return NULL; } @@ -1947,8 +2221,10 @@ static void tcg_target_init(TCGContext *s) { tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffffu; tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffffu; + tcg_target_available_regs[TCG_TYPE_V64] =3D 0xffffffff00000000ull; + tcg_target_available_regs[TCG_TYPE_V128] =3D 0xffffffff00000000ull; =20 - tcg_target_call_clobber_regs =3D 0xfffffffu; + tcg_target_call_clobber_regs =3D -1ull; tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X19); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X20); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X21); @@ -1960,6 +2236,14 @@ static void tcg_target_init(TCGContext *s) tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X27); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X28); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X29); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V8); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V9); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V10); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V11); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V12); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V13); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V14); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V15); =20 s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); --=20 2.13.5