From nobody Tue Nov 4 07:18:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505150631311333.7472480749499; Mon, 11 Sep 2017 10:23:51 -0700 (PDT) Received: from localhost ([::1]:59322 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drSR4-000106-BZ for importer@patchew.org; Mon, 11 Sep 2017 13:23:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35382) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drSHs-0001QQ-Uc for qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:14:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1drSHo-0004U8-Dx for qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:14:20 -0400 Received: from 3.mo2.mail-out.ovh.net ([46.105.58.226]:59734) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1drSHo-0004Ti-88 for qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:14:16 -0400 Received: from player770.ha.ovh.net (b6.ovh.net [213.186.33.56]) by mo2.mail-out.ovh.net (Postfix) with ESMTP id 507E3AB262 for ; Mon, 11 Sep 2017 19:14:15 +0200 (CEST) Received: from zorba.kaod.org.com (LFbn-1-2231-173.w90-76.abo.wanadoo.fr [90.76.52.173]) (Authenticated sender: clg@kaod.org) by player770.ha.ovh.net (Postfix) with ESMTPSA id 1C2663C0072; Mon, 11 Sep 2017 19:14:08 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson , Benjamin Herrenschmidt , Alexey Kardashevskiy , Alexander Graf Date: Mon, 11 Sep 2017 19:12:26 +0200 Message-Id: <20170911171235.29331-13-clg@kaod.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170911171235.29331-1-clg@kaod.org> References: <20170911171235.29331-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 14152280358323194707 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelledrgedtgdduudehucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 46.105.58.226 Subject: [Qemu-devel] [RFC PATCH v2 12/21] ppc/xive: notify the CPU when interrupt priority is more privileged X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The Pending Interrupt Priority Register (PIPR) contains the priority of the most favored pending notification. It is calculated from the Interrupt Pending Buffer (IPB) which indicates a pending interrupt at the priority corresponding to the bit number. If the PIPR is more favored (1) than the Current Processor Priority Register (CPPR), the CPU interrupt line can be raised and the EO bit of the Notification Source Register is updated to notify the presence of an exception for the O/S. The check needs to be done whenever the PIPR or the CPPR is changed. (1) numerically less than Signed-off-by: C=C3=A9dric Le Goater --- hw/intc/spapr_xive.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++= ++ 1 file changed, 50 insertions(+) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 4bc61cfda67a..e5d4b723b7e0 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -28,11 +28,39 @@ #include "xive-internal.h" =20 =20 +/* Convert a priority number to an Interrupt Pending Buffer (IPB) + * register, which indicates a pending interrupt at the priority + * corresponding to the bit number + */ +static uint8_t priority_to_ipb(uint8_t priority) +{ + return priority > XIVE_PRIORITY_MAX ? 0 : 1 << (7 - priority); +} + +/* Convert an Interrupt Pending Buffer (IPB) register to a Pending + * Interrupt Priority Register (PIPR), which contains the priority of + * the most favored pending notification. + * + * TODO: PIPR can never be OxFF. Needs a fix. + */ +static uint8_t ipb_to_pipr(uint8_t ibp) +{ + return ibp ? clz32((uint32_t)ibp << 24) : 0xff; +} + static uint64_t spapr_xive_icp_accept(ICPState *icp) { return 0; } =20 +static void spapr_xive_icp_notify(ICPState *icp) +{ + if (icp->tima_os[TM_PIPR] < icp->tima_os[TM_CPPR]) { + icp->tima_os[TM_NSR] |=3D TM_QW1_NSR_EO; + qemu_irq_raise(ICP(icp)->output); + } +} + static void spapr_xive_icp_set_cppr(ICPState *icp, uint8_t cppr) { if (cppr > XIVE_PRIORITY_MAX) { @@ -40,6 +68,10 @@ static void spapr_xive_icp_set_cppr(ICPState *icp, uint8= _t cppr) } =20 icp->tima_os[TM_CPPR] =3D cppr; + + /* CPPR has changed, inform the ICP which might raise an + * exception */ + spapr_xive_icp_notify(icp); } =20 /* @@ -206,6 +238,8 @@ static void spapr_xive_irq(sPAPRXive *xive, int srcno) XiveEQ *eq; uint32_t eq_idx; uint32_t priority; + uint32_t target; + ICPState *icp; =20 ive =3D spapr_xive_get_ive(xive, srcno); if (!ive || !(ive->w & IVE_VALID)) { @@ -235,6 +269,13 @@ static void spapr_xive_irq(sPAPRXive *xive, int srcno) qemu_log_mask(LOG_UNIMP, "XIVE: !UCOND_NOTIFY not implemented\n"); } =20 + target =3D GETFIELD(EQ_W6_NVT_INDEX, eq->w6); + icp =3D xics_icp_get(xive->ics->xics, target); + if (!icp) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No ICP for target %d\n", tar= get); + return; + } + if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) =3D=3D 0) { priority =3D GETFIELD(EQ_W7_F0_PRIORITY, eq->w7); =20 @@ -242,9 +283,18 @@ static void spapr_xive_irq(sPAPRXive *xive, int srcno) if (priority =3D=3D 0xff) { return; } + + /* Update the IPB (Interrupt Pending Buffer) with the priority + * of the new notification and inform the ICP, which will + * decide to raise the exception, or not, depending the CPPR. + */ + icp->tima_os[TM_IPB] |=3D priority_to_ipb(priority); + icp->tima_os[TM_PIPR] =3D ipb_to_pipr(icp->tima_os[TM_IPB]); } else { qemu_log_mask(LOG_UNIMP, "XIVE: w7 format1 not implemented\n"); } + + spapr_xive_icp_notify(icp); } =20 /* --=20 2.13.5