From nobody Tue Feb 10 03:38:44 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504867649497315.1451737932937; Fri, 8 Sep 2017 03:47:29 -0700 (PDT) Received: from localhost ([::1]:44501 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dqGoq-0003rm-7C for importer@patchew.org; Fri, 08 Sep 2017 06:47:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58708) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dqGe6-00029v-Ra for qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dqGe0-0003FA-T8 for qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:22 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:59749) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dqGdz-0003BI-FA; Fri, 08 Sep 2017 06:36:16 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 3xpYdK2J0Pz9t3w; Fri, 8 Sep 2017 20:36:04 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1504866965; bh=CU1BlHzc/lBE980DbHuRTfVd8Q1T+KcQEnInH5aGPZ0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=isMhIqb1ArKeFluYPbLsTI9R6VIlHdIsI/8OqQ8QIQ2vHzjsN/x4CwZCGnVJKo+ax qTGkOpV/NHSSt+v63v4ZfAGpytE3MA+tu8W52F4EZEjvkU7FgU+kx4kXgDzWjkZgrU B14fA7TJ3FJ/yDKsOr7/iPBzEVJzsQvrX87YN4wc= From: David Gibson To: peter.maydell@linaro.org Date: Fri, 8 Sep 2017 20:35:38 +1000 Message-Id: <20170908103558.31632-21-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908103558.31632-1-david@gibson.dropbear.id.au> References: <20170908103558.31632-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 20/40] ppc64: introduce e6500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, aik@ozlabs.ru, agraf@suse.de, mdroth@linux.vnet.ibm.com, KONRAD Frederic , qemu-ppc@nongnu.org, imammedo@redhat.com, sam.bobroff@au1.ibm.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic This introduces e6500 core. Signed-off-by: KONRAD Frederic Signed-off-by: David Gibson --- target/ppc/cpu-models.c | 2 + target/ppc/cpu-models.h | 1 + target/ppc/translate_init.c | 91 +++++++++++++++++++++++++++++++++++++++++= +++- 3 files changed, 93 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index 4d3e6354cf..e0d9faf848 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -693,6 +693,8 @@ #ifdef TARGET_PPC64 POWERPC_DEF_SVR("e5500", "e5500", CPU_POWERPC_e5500, POWERPC_SVR_E500, e5500) + POWERPC_DEF_SVR("e6500", "e6500", + CPU_POWERPC_e6500, POWERPC_SVR_E500, e6500) #endif /* PowerPC e500 microcontrollers = */ POWERPC_DEF_SVR("MPC8533_v10", "MPC8533 v1.0", diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index b563c45b68..eaa6849a42 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -346,6 +346,7 @@ enum { CPU_POWERPC_e500v2_v30 =3D 0x80210030, CPU_POWERPC_e500mc =3D 0x80230020, CPU_POWERPC_e5500 =3D 0x80240020, + CPU_POWERPC_e6500 =3D 0x80400020, /* MPC85xx microcontrollers */ #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22 diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 4104629df7..08ef74f064 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -4888,6 +4888,7 @@ enum fsl_e500_version { fsl_e500v2, fsl_e500mc, fsl_e5500, + fsl_e6500, }; =20 static void init_proc_e500(CPUPPCState *env, int version) @@ -4922,6 +4923,9 @@ static void init_proc_e500(CPUPPCState *env, int vers= ion) case fsl_e5500: ivor_mask =3D 0x000003FE0000FFFFULL; break; + case fsl_e6500: + ivor_mask =3D 0x000003FF0000FFFFULL; + break; } gen_spr_BookE(env, ivor_mask); gen_spr_usprg3(env); @@ -4954,6 +4958,12 @@ static void init_proc_e500(CPUPPCState *env, int ver= sion) tlbncfg[0] =3D gen_tlbncfg(4, 1, 1, 0, 512); tlbncfg[1] =3D gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPRO= T, 64); break; + case fsl_e6500: + mmucfg =3D 0x6510B45; + env->nb_pids =3D 1; + tlbncfg[0] =3D 0x08052400; + tlbncfg[1] =3D 0x40028040; + break; default: cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[S= PR_PVR]); } @@ -4972,6 +4982,12 @@ static void init_proc_e500(CPUPPCState *env, int ver= sion) l1cfg0 |=3D 0x1000000; /* 64 byte cache block size */ l1cfg1 |=3D 0x1000000; /* 64 byte cache block size */ break; + case fsl_e6500: + env->dcache_line_size =3D 32; + env->icache_line_size =3D 32; + l1cfg0 |=3D 0x0F83820; + l1cfg1 |=3D 0x0B83820; + break; default: cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[S= PR_PVR]); } @@ -5050,7 +5066,7 @@ static void init_proc_e500(CPUPPCState *env, int vers= ion) &spr_read_generic, SPR_NOACCESS, 0x00000000); /* XXX better abstract into Emb.xxx features */ - if (version =3D=3D fsl_e5500) { + if ((version =3D=3D fsl_e5500) || (version =3D=3D fsl_e6500)) { spr_register(env, SPR_BOOKE_EPCR, "EPCR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -5062,6 +5078,30 @@ static void init_proc_e500(CPUPPCState *env, int ver= sion) ivpr_mask =3D (target_ulong)~0xFFFFULL; } =20 + if (version =3D=3D fsl_e6500) { + spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + /* Thread identification */ + spr_register(env, SPR_TIR, "TIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000004); + spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x7FFFFFFC); + } + #if !defined(CONFIG_USER_ONLY) env->nb_tlb =3D 0; env->tlb_type =3D TLB_MAS; @@ -5254,6 +5294,55 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) pcc->flags =3D POWERPC_FLAG_CE | POWERPC_FLAG_DE | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; } + +static void init_proc_e6500(CPUPPCState *env) +{ + init_proc_e500(env, fsl_e6500); +} + +POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + PowerPCCPUClass *pcc =3D POWERPC_CPU_CLASS(oc); + + dc->desc =3D "e6500 core"; + pcc->init_proc =3D init_proc_e6500; + pcc->check_pow =3D check_pow_none; + pcc->insns_flags =3D PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | + PPC_WRTEE | PPC_RFDI | PPC_RFMCI | + PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_FLOAT | PPC_FLOAT_FRES | + PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | + PPC_FLOAT_STFIWX | PPC_WAIT | + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | + PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; + pcc->insns_flags2 =3D PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |= \ + PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; + pcc->msr_mask =3D (1ull << MSR_CM) | + (1ull << MSR_GS) | + (1ull << MSR_UCLE) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IS) | + (1ull << MSR_DS) | + (1ull << MSR_PX) | + (1ull << MSR_RI) | + (1ull << MSR_VR); + pcc->mmu_model =3D POWERPC_MMU_BOOKE206; + pcc->excp_model =3D POWERPC_EXCP_BOOKE; + pcc->bus_model =3D PPC_FLAGS_INPUT_BookE; + pcc->bfd_mach =3D bfd_mach_ppc_e500; + pcc->flags =3D POWERPC_FLAG_CE | POWERPC_FLAG_DE | + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VR= E; +} + #endif =20 /* Non-embedded PowerPC = */ --=20 2.13.5