From nobody Tue Feb 10 01:35:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504868515709371.34967722641636; Fri, 8 Sep 2017 04:01:55 -0700 (PDT) Received: from localhost ([::1]:44576 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dqH2o-0007yP-Ca for importer@patchew.org; Fri, 08 Sep 2017 07:01:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58668) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dqGe5-00028i-AG for qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dqGe0-0003EJ-F5 for qemu-devel@nongnu.org; Fri, 08 Sep 2017 06:36:21 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:54369) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dqGe0-0003Bn-02; Fri, 08 Sep 2017 06:36:16 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 3xpYdL5f8wz9t4c; Fri, 8 Sep 2017 20:36:04 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1504866966; bh=08F7meoLgnirL0dn0DGt7ZuONGT7wTakwVjKuIjq5Wg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FaBqhYcAh0tyJz2J8lT/Al3TXMtlN0ikeCVvvs8LhrIeY9UcdlsemuU+DYD/dGGFv OjCLIjYXdpwdcKD5WWGITX8nU9F5d7wKzkKJ6ggRbyIXKRjjSRENjtRbtgBKGKINAF 6VvaZBAwkvoLM9lkPzxb0I1cQfPISOKJmxD4aQWY= From: David Gibson To: peter.maydell@linaro.org Date: Fri, 8 Sep 2017 20:35:36 +1000 Message-Id: <20170908103558.31632-19-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170908103558.31632-1-david@gibson.dropbear.id.au> References: <20170908103558.31632-1-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 Subject: [Qemu-devel] [PULL 18/40] booke206: fix tlbnps for fixed size TLB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, aik@ozlabs.ru, agraf@suse.de, mdroth@linux.vnet.ibm.com, KONRAD Frederic , qemu-ppc@nongnu.org, imammedo@redhat.com, sam.bobroff@au1.ibm.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: KONRAD Frederic Some OS don't populate the TSIZE field when using a fixed size TLB which re= sult in a 1KB TLB. When the TLB is a fixed size TLB the TSIZE field should be ignored. Fix this wrong behavior with MAV 2.0. Signed-off-by: KONRAD Frederic Signed-off-by: David Gibson --- target/ppc/cpu.h | 22 ++++++++++++++++++++++ target/ppc/mmu_helper.c | 16 ++++++++++------ 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 21f0ddd056..042372c5ad 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2491,6 +2491,28 @@ static inline uint32_t booke206_tlbnps(CPUPPCState *= env, const int tlbn) return ret; } =20 +static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tl= bn, + ppcmas_tlb_t *tlb) +{ + uint8_t i; + int32_t tsize =3D -1; + + for (i =3D 0; i < 32; i++) { + if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) { + if (tsize =3D=3D -1) { + tsize =3D i; + } else { + return; + } + } + } + + /* TLBnPS unimplemented? Odd.. */ + assert(tsize !=3D -1); + tlb->mas1 &=3D ~MAS1_TSIZE_MASK; + tlb->mas1 |=3D ((uint32_t)tsize) << MAS1_TSIZE_SHIFT; +} + #endif =20 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr) diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index f06b9382b4..2a1f9902c9 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -2632,12 +2632,16 @@ void helper_booke206_tlbwe(CPUPPCState *env) env->spr[SPR_BOOKE_MAS3]; tlb->mas1 =3D env->spr[SPR_BOOKE_MAS1]; =20 - /* MAV 1.0 only */ - if (!(tlbncfg & TLBnCFG_AVAIL)) { - /* force !AVAIL TLB entries to correct page size */ - tlb->mas1 &=3D ~MAS1_TSIZE_MASK; - /* XXX can be configured in MMUCSR0 */ - tlb->mas1 |=3D (tlbncfg & TLBnCFG_MINSIZE) >> 12; + if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) =3D=3D MMUCFG_MAVN_V2) { + /* For TLB which has a fixed size TSIZE is ignored with MAV2 */ + booke206_fixed_size_tlbn(env, tlbn, tlb); + } else { + if (!(tlbncfg & TLBnCFG_AVAIL)) { + /* force !AVAIL TLB entries to correct page size */ + tlb->mas1 &=3D ~MAS1_TSIZE_MASK; + /* XXX can be configured in MMUCSR0 */ + tlb->mas1 |=3D (tlbncfg & TLBnCFG_MINSIZE) >> 12; + } } =20 /* Make a mask from TLB size to discard invalid bits in EPN field */ --=20 2.13.5