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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id h19sm770678pfh.142.2017.09.07.15.41.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 15:41:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5QX8KOLakpmoalYp7gpxxqobtH+OmlG68TqfOqz5jpo=; b=avymF+iOfoV8ayOmc8Mnwihij2BQDSjIC91GwHzdyHC85dBGmOAKFQVUNUKL6SoqHR HfsCyZPnb5oWDhqxFe5uMxIAm36ZL0815l1YPzK18v761+2voPbgt1wBv39eNtrBpyku LtzGCRbLx46rV185K81dEjxWwxjp6yl7diF9A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5QX8KOLakpmoalYp7gpxxqobtH+OmlG68TqfOqz5jpo=; b=JgkVAgAiKIDm6H/0nC15PrjYpkT2gRyy13enAxkF/ukQlJzgAKoPZb1gQxEEf6IYlW rDGHxkh/B/9PzEKR1N0j8jWrKWWpb9MfAQbYIWuxF6vildGztQzyn9LtQuVw91nvbIH2 VkibDzOllyA4q3Hn4si16uBmfXAcWrvEdZ07znvt5T3IOKH34k1YlrycImMKF0YzuFRQ 1QUut3EXaAt2y0pIyHIFpnh8XQsRDpRI0xr9z8BTNhZaNwu8a+QgivZVpo8wegrShEI2 f0DUrmJxjrdDf5hG5ELwyhIU903sGHa4ux3uz6MyVmnK1IEKNzp7JaUhiEZwPWDcNtLj SXog== X-Gm-Message-State: AHPjjUh8PLoIduf1YyN8KbTp5450uIRQSpVEhlNxRPafejJrWut1cOzy ErfA4PpVI40KWcW709Wvzg== X-Google-Smtp-Source: ADKCNb63ADnTh4NOSJD7r9onJtaYBix66AUmwIAEck69NSjD9CCs//JMcSPn5sgDBOYDsft4+/w9pw== X-Received: by 10.84.132.1 with SMTP id 1mr1003215ple.253.1504824076120; Thu, 07 Sep 2017 15:41:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 15:40:43 -0700 Message-Id: <20170907224051.21518-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907224051.21518-1-richard.henderson@linaro.org> References: <20170907224051.21518-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PULL 15/23] tcg/arm: Improve tlb load for armv7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use UBFX to avoid limitation on CPU_TLB_BITS. Since we're dropping the initial shift, we need to replace the page masking. We can use MOVW+BIC to do this without shifting. The result is the same size as the armv6 path with one less conditional instruction. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 72 ++++++++++++++++++++++++++++++++++----------= ---- 1 file changed, 52 insertions(+), 20 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 81ea900852..66c369c239 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1173,18 +1173,33 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 - /* Should generate something like the following: - * shr tmp, addrlo, #TARGET_PAGE_BITS (1) + /* V7 generates the following: + * ubfx r0, addrlo, #TARGET_PAGE_BITS, #CPU_TLB_BITS * add r2, env, #high - * and r0, tmp, #(CPU_TLB_SIZE - 1) (2) - * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS (3) - * ldr r0, [r2, #cmp] (4) + * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS + * ldr r0, [r2, #cmp] + * ldr r2, [r2, #add] + * movw tmp, #page_align_mask + * bic tmp, addrlo, tmp + * cmp r0, tmp + * + * Otherwise we generate: + * shr tmp, addrlo, #TARGET_PAGE_BITS + * add r2, env, #high + * and r0, tmp, #(CPU_TLB_SIZE - 1) + * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS + * ldr r0, [r2, #cmp] + * ldr r2, [r2, #add] * tst addrlo, #s_mask - * ldr r2, [r2, #add] (5) * cmpeq r0, tmp, lsl #TARGET_PAGE_BITS */ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, - 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + if (use_armv7_instructions) { + tcg_out_extract(s, COND_AL, TCG_REG_R0, addrlo, + TARGET_PAGE_BITS, CPU_TLB_BITS); + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, + 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + } =20 /* We checked that the offset is contained within 16 bits above. */ if (add_off > 0xfff || (use_armv6_instructions && cmp_off > 0xff)) { @@ -1194,9 +1209,10 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg= addrlo, TCGReg addrhi, add_off -=3D cmp_off & 0xff00; cmp_off &=3D 0xff; } - - tcg_out_dat_imm(s, COND_AL, ARITH_AND, - TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1); + if (!use_armv7_instructions) { + tcg_out_dat_imm(s, COND_AL, ARITH_AND, + TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1); + } tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); =20 @@ -1212,24 +1228,40 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, } } =20 + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, add_off); + /* Check alignment. We don't support inline unaligned acceses, but we can easily support overalignment checks. */ if (a_bits < s_bits) { a_bits =3D s_bits; } - if (a_bits) { - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, (1 << a_bits) - = 1); - } =20 - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, add_off); + if (use_armv7_instructions) { + tcg_target_ulong mask =3D ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1)= ); + int rot =3D encode_imm(mask); =20 - tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, 0, - TCG_REG_R0, TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BIT= S)); + if (rot >=3D 0) {=20 + tcg_out_dat_imm(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo, + rotl(mask, rot) | (rot << 7)); + } else { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, + addrlo, TCG_REG_TMP, 0); + } + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP,= 0); + } else { + if (a_bits) { + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, + (1 << a_bits) - 1); + } + tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, + 0, TCG_REG_R0, TCG_REG_TMP, + SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + } =20 if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, - TCG_REG_R1, addrhi, SHIFT_IMM_LSL(0)); + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addrhi, 0); } =20 return TCG_REG_R2; --=20 2.13.5