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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id h19sm770678pfh.142.2017.09.07.15.41.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 15:41:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UqbemKBcSAFRk6ka+QSoQnu16oHX7Q4v8g2SbdNvrNg=; b=XV66D4qTRKuoPoR3cygKOGztQhn4oTbTVRzufrL6MKhdzOftNQznijsU9sfoQLqX3y X3BFlJbssgee/3i2flY8mlgTj2FZq037uyCblmh3iQEkXRigKbjb247QUNQoNtaoSe+U Q3Fn0E2P6Ir32r+yCulyCLd1BSD4edjhn4TM0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UqbemKBcSAFRk6ka+QSoQnu16oHX7Q4v8g2SbdNvrNg=; b=DVs7GjtYDhGtrUP35qnRH94w0rKTjLvrZJsF/7zsro1hjNkjTfiktKoVOpHdBm9ugb tNN7/0ZsBxie28lkejZo8Co5Gk6aqQ8+zVmTQFJKwj/+xmJnuqnLYd+JHSy3g44baF/i br9xOi/HUhU7WzJjMfudcNYtyL2SeH0xv2HeN+8XjCq3iZfFWAZ30LH+YohI6DqPh12W h1fcExcoahJp3iGus2+2eRBwT9GEsneH9EM6OPtwkV1WzI/B/meZO3tXgEVgzQQO4cyz 4NtpXpAKzO603rPbg2fp2RZJRDIvPLlasWec8cbNjk2hN4pqTwB17ssJer4uqKEQ5btM 9f3A== X-Gm-Message-State: AHPjjUj0R0Q87ZBKmoL/qHpsDr0hJwNU1OtCCxgI6dCczBDVGRNRfAHl dsvSEjKibn4L+xcKRwKUEQ== X-Google-Smtp-Source: ADKCNb5+ckXCrF6q6YJFifvsgY+QZqxirFKKvIQepWd4NC/tI2knqNyVlnDGx7t+VUXo5hZUcCqETw== X-Received: by 10.99.116.21 with SMTP id p21mr944350pgc.93.1504824070414; Thu, 07 Sep 2017 15:41:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 15:40:39 -0700 Message-Id: <20170907224051.21518-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907224051.21518-1-richard.henderson@linaro.org> References: <20170907224051.21518-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22e Subject: [Qemu-devel] [PULL 11/23] tcg/s390: Use constant pool for cmpi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Also use CHI/CGHI for 16-bit signed constants. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 136 +++++++++++++++++++++++-------------------= ---- 1 file changed, 67 insertions(+), 69 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index b0b34fa5ab..e7ab8e4df3 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -39,9 +39,8 @@ =20 #define TCG_CT_CONST_S16 0x100 #define TCG_CT_CONST_S32 0x200 -#define TCG_CT_CONST_U31 0x400 -#define TCG_CT_CONST_S33 0x800 -#define TCG_CT_CONST_ZERO 0x1000 +#define TCG_CT_CONST_S33 0x400 +#define TCG_CT_CONST_ZERO 0x800 =20 /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ @@ -75,6 +74,10 @@ typedef enum S390Opcode { RIL_CGFI =3D 0xc20c, RIL_CLFI =3D 0xc20f, RIL_CLGFI =3D 0xc20e, + RIL_CLRL =3D 0xc60f, + RIL_CLGRL =3D 0xc60a, + RIL_CRL =3D 0xc60d, + RIL_CGRL =3D 0xc608, RIL_IIHF =3D 0xc008, RIL_IILF =3D 0xc009, RIL_LARL =3D 0xc000, @@ -97,6 +100,8 @@ typedef enum S390Opcode { RI_AGHI =3D 0xa70b, RI_AHI =3D 0xa70a, RI_BRC =3D 0xa704, + RI_CHI =3D 0xa70e, + RI_CGHI =3D 0xa70f, RI_IIHH =3D 0xa500, RI_IIHL =3D 0xa501, RI_IILH =3D 0xa502, @@ -206,6 +211,8 @@ typedef enum S390Opcode { RXY_AG =3D 0xe308, RXY_AY =3D 0xe35a, RXY_CG =3D 0xe320, + RXY_CLG =3D 0xe321, + RXY_CLY =3D 0xe355, RXY_CY =3D 0xe359, RXY_LAY =3D 0xe371, RXY_LB =3D 0xe376, @@ -423,20 +430,6 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, case 'J': ct->ct |=3D TCG_CT_CONST_S32; break; - case 'C': - /* ??? We have no insight here into whether the comparison is - signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit - signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses - a 32-bit unsigned immediate. If we were to use the (semi) - obvious "val =3D=3D (int32_t)val" we would be enabling unsigned - comparisons vs very large numbers. The only solution is to - take the intersection of the ranges. */ - /* ??? Another possible solution is to simply lie and allow all - constants here and force the out-of-range values into a temp - register in tgen_cmp when we have knowledge of the actual - comparison code in use. */ - ct->ct |=3D TCG_CT_CONST_U31; - break; case 'Z': ct->ct |=3D TCG_CT_CONST_ZERO; break; @@ -467,8 +460,6 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, return val =3D=3D (int32_t)val; } else if (ct & TCG_CT_CONST_S33) { return val >=3D -0xffffffffll && val <=3D 0xffffffffll; - } else if (ct & TCG_CT_CONST_U31) { - return val >=3D 0 && val <=3D 0x7fffffff; } else if (ct & TCG_CT_CONST_ZERO) { return val =3D=3D 0; } @@ -1092,6 +1083,8 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGC= ond c, TCGReg r1, TCGArg c2, bool c2const, bool need_carry) { bool is_unsigned =3D is_unsigned_cond(c); + S390Opcode op; + if (c2const) { if (c2 =3D=3D 0) { if (!(is_unsigned && need_carry)) { @@ -1102,44 +1095,67 @@ static int tgen_cmp(TCGContext *s, TCGType type, TC= GCond c, TCGReg r1, } return tcg_cond_to_ltr_cond[c]; } - /* If we only got here because of load-and-test, - and we couldn't use that, then we need to load - the constant into a register. */ - if (!(s390_facilities & FACILITY_EXT_IMM)) { - c2 =3D TCG_TMP0; - tcg_out_movi(s, type, c2, 0); - goto do_reg; - } } - if (is_unsigned) { - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RIL, CLFI, r1, c2); - } else { - tcg_out_insn(s, RIL, CLGFI, r1, c2); - } - } else { + + if (!is_unsigned && c2 =3D=3D (int16_t)c2) { + op =3D (type =3D=3D TCG_TYPE_I32 ? RI_CHI : RI_CGHI); + tcg_out_insn_RI(s, op, r1, c2); + goto exit; + } + + if (s390_facilities & FACILITY_EXT_IMM) { if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RIL, CFI, r1, c2); - } else { - tcg_out_insn(s, RIL, CGFI, r1, c2); + op =3D (is_unsigned ? RIL_CLFI : RIL_CFI); + tcg_out_insn_RIL(s, op, r1, c2); + goto exit; + } else if (c2 =3D=3D (is_unsigned ? (uint32_t)c2 : (int32_t)c2= )) { + op =3D (is_unsigned ? RIL_CLGFI : RIL_CGFI); + tcg_out_insn_RIL(s, op, r1, c2); + goto exit; } } - } else { - do_reg: - if (is_unsigned) { + + /* Use the constant pool, but not for small constants. */ + if (maybe_out_small_movi(s, type, TCG_TMP0, c2)) { + c2 =3D TCG_TMP0; + /* fall through to reg-reg */ + } else if (USE_REG_TB) { if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RR, CLR, r1, c2); + op =3D (is_unsigned ? RXY_CLY : RXY_CY); + tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, (uint32_t)c2, R_390_20, s->code_ptr - 2, + 4 - (intptr_t)s->code_gen_ptr); } else { - tcg_out_insn(s, RRE, CLGR, r1, c2); + op =3D (is_unsigned ? RXY_CLG : RXY_CG); + tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, c2, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); } + goto exit; } else { if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RR, CR, r1, c2); + op =3D (is_unsigned ? RIL_CLRL : RIL_CRL); + tcg_out_insn_RIL(s, op, r1, 0); + new_pool_label(s, (uint32_t)c2, R_390_PC32DBL, + s->code_ptr - 2, 2 + 4); } else { - tcg_out_insn(s, RRE, CGR, r1, c2); + op =3D (is_unsigned ? RIL_CLGRL : RIL_CGRL); + tcg_out_insn_RIL(s, op, r1, 0); + new_pool_label(s, c2, R_390_PC32DBL, s->code_ptr - 2, 2); } + goto exit; } } + + if (type =3D=3D TCG_TYPE_I32) { + op =3D (is_unsigned ? RR_CLR : RR_CR); + tcg_out_insn_RR(s, op, r1, c2); + } else { + op =3D (is_unsigned ? RRE_CLGR : RRE_CGR); + tcg_out_insn_RRE(s, op, r1, c2); + } + + exit: return tcg_cond_to_s390_cond[c]; } =20 @@ -2325,8 +2341,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; static const TCGTargetOpDef L_L =3D { .args_ct_str =3D { "L", "L" } }; static const TCGTargetOpDef r_ri =3D { .args_ct_str =3D { "r", "ri" } = }; - static const TCGTargetOpDef r_rC =3D { .args_ct_str =3D { "r", "rC" } = }; - static const TCGTargetOpDef r_rZ =3D { .args_ct_str =3D { "r", "rZ" } = }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; @@ -2401,10 +2415,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) return &r_r_ri; =20 case INDEX_op_brcond_i32: - /* Without EXT_IMM, only the LOAD AND TEST insn is available. */ - return (s390_facilities & FACILITY_EXT_IMM ? &r_ri : &r_rZ); case INDEX_op_brcond_i64: - return (s390_facilities & FACILITY_EXT_IMM ? &r_rC : &r_rZ); + return &r_ri; =20 case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -2430,6 +2442,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &r_r; =20 case INDEX_op_clz_i64: + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: return &r_r_ri; =20 case INDEX_op_qemu_ld_i32: @@ -2446,30 +2460,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) =3D { .args_ct_str =3D { "r", "rZ", "r" } }; return &dep; } - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - { - /* Without EXT_IMM, only the LOAD AND TEST insn is available. = */ - static const TCGTargetOpDef setc_z - =3D { .args_ct_str =3D { "r", "r", "rZ" } }; - static const TCGTargetOpDef setc_c - =3D { .args_ct_str =3D { "r", "r", "rC" } }; - return (s390_facilities & FACILITY_EXT_IMM ? &setc_c : &setc_z= ); - } case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: { - /* Without EXT_IMM, only the LOAD AND TEST insn is available. = */ - static const TCGTargetOpDef movc_z - =3D { .args_ct_str =3D { "r", "r", "rZ", "r", "0" } }; - static const TCGTargetOpDef movc_c - =3D { .args_ct_str =3D { "r", "r", "rC", "r", "0" } }; + static const TCGTargetOpDef movc + =3D { .args_ct_str =3D { "r", "r", "ri", "r", "0" } }; static const TCGTargetOpDef movc_l - =3D { .args_ct_str =3D { "r", "r", "rC", "rI", "0" } }; - return (s390_facilities & FACILITY_EXT_IMM - ? (s390_facilities & FACILITY_LOAD_ON_COND2 - ? &movc_l : &movc_c) - : &movc_z); + =3D { .args_ct_str =3D { "r", "r", "ri", "rI", "0" } }; + return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &= movc); } case INDEX_op_div2_i32: case INDEX_op_div2_i64: --=20 2.13.5