From nobody Tue May 7 18:43:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504810411601648.7911659562433; Thu, 7 Sep 2017 11:53:31 -0700 (PDT) Received: from localhost ([::1]:41773 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1ve-0001yN-81 for importer@patchew.org; Thu, 07 Sep 2017 14:53:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54124) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1tK-00008v-Pw for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dq1tF-0000TY-LZ for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:06 -0400 Received: from mail-pg0-x230.google.com ([2607:f8b0:400e:c05::230]:33554) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dq1tF-0000T1-D7 for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:01 -0400 Received: by mail-pg0-x230.google.com with SMTP id t3so1010855pgt.0 for ; Thu, 07 Sep 2017 11:51:01 -0700 (PDT) Received: from pike.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id l74sm481401pfi.9.2017.09.07.11.50.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 11:50:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=upScR165ou3rsrjnioluJcuDJXLGqYreYtv7+HgSjuE=; b=c5c+HUTN0SGIquPr/Xsv8fSAKe8BrmV2CkebcLzjT4CoTG5y1910SJE7kc7fMdhRdS MkMcv00VFZS/zWLFq2Rv3vbPvRVZsAJT1MQSy/9HWzemUsDJEBpVDp/GI6ORA0GBRdMH wPfTXSqMB63wJbQsKC3D5IKgiuI10fK6cQMT4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=upScR165ou3rsrjnioluJcuDJXLGqYreYtv7+HgSjuE=; b=PCe4xqtER1FRA1nil37QosZwwJZUna9Pqpa/yZJqvvP6SiBDkscLK+3M05ibi3PRnL EAiVisa4ZJzzDhBGT8Wx++/A+eT1V71VhlOVbAtq6ACNxbBLxOIF2R4HNDAywJKl1Kgz ZyxDlKLO1iuRo4b8SgRTY522gBCJQk8pRP7Xqxlsy5SdbI0pJ6yIHJgWEhFQWR25iyiN AuG8buoeNoyScpXPvRAl6M+sDfKXfS3MiJ0K4vPUSMJKaLxCAcocziK9jrOdrMJO3SoF F6lggjoM2Uth1NjEnv0X6WePy5HSWPVaYwlH7I4nH/M19u/ystsiqStoG5aCC4nVer9O qIMQ== X-Gm-Message-State: AHPjjUgb//E2ku0IFvOoUlZSRxh7Lz5/e+Cq28ANNvaq5h49rRlnvxyq UBCcAtwDmbVURlUpE1ny7A== X-Google-Smtp-Source: ADKCNb70S1DvMlJJwALbSuWuQyJ774ZMM0QKwQXZjQi6I0FC+zxG/T764yKy0zEUdFptYBpEp9/0fA== X-Received: by 10.99.42.11 with SMTP id q11mr312130pgq.7.1504810260017; Thu, 07 Sep 2017 11:51:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 11:50:53 -0700 Message-Id: <20170907185057.23421-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907185057.23421-1-richard.henderson@linaro.org> References: <20170907185057.23421-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::230 Subject: [Qemu-devel] [PATCH v2 1/5] target/sh4: Use cmpxchg for movco when parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson As for other targets, cmpxchg isn't quite right for ll/sc, suffering from an ABA race, but is sufficient to implement portable atomic operations. Signed-off-by: Richard Henderson --- linux-user/main.c | 19 +++++++++--- target/sh4/cpu.h | 4 ++- target/sh4/helper.c | 1 + target/sh4/translate.c | 81 ++++++++++++++++++++++++++++++++++++----------= ---- 4 files changed, 78 insertions(+), 27 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 03666ef657..22b3bdafc5 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2665,6 +2665,8 @@ void cpu_loop(CPUSH4State *env) target_siginfo_t info; =20 while (1) { + bool arch_interrupt =3D true; + cpu_exec_start(cs); trapnr =3D cpu_exec(cs); cpu_exec_end(cs); @@ -2696,13 +2698,14 @@ void cpu_loop(CPUSH4State *env) int sig; =20 sig =3D gdb_handlesig(cs, TARGET_SIGTRAP); - if (sig) - { + if (sig) { info.si_signo =3D sig; info.si_errno =3D 0; info.si_code =3D TARGET_TRAP_BRKPT; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); - } + } else { + arch_interrupt =3D false; + } } break; case 0xa0: @@ -2713,9 +2716,9 @@ void cpu_loop(CPUSH4State *env) info._sifields._sigfault._addr =3D env->tea; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; - case EXCP_ATOMIC: cpu_exec_step_atomic(cs); + arch_interrupt =3D false; break; default: printf ("Unhandled trap: 0x%x\n", trapnr); @@ -2723,6 +2726,14 @@ void cpu_loop(CPUSH4State *env) exit(EXIT_FAILURE); } process_pending_signals (env); + + /* Most of the traps imply an exception or interrupt, which + implies an REI instruction has been executed. Which means + that LDST (aka LOK_ADDR) should be cleared. But there are + a few exceptions for traps internal to QEMU. */ + if (arch_interrupt) { + env->lock_addr =3D -1; + } } } #endif diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 79f85d3365..603614a2d8 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -184,7 +184,9 @@ typedef struct CPUSH4State { tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ tlb_t utlb[UTLB_SIZE]; /* unified translation table */ =20 - uint32_t ldst; + /* LDST =3D LOCK_ADDR !=3D -1. */ + uint32_t lock_addr; + uint32_t lock_value; =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 28d93c2543..680b583e53 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -171,6 +171,7 @@ void superh_cpu_do_interrupt(CPUState *cs) env->spc =3D env->pc; env->sgr =3D env->gregs[15]; env->sr |=3D (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB); + env->lock_addr =3D -1; =20 if (env->flags & DELAY_SLOT_MASK) { /* Branch instruction should be executed again before delay slot. = */ diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 10191073b2..4365b21624 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -70,7 +70,8 @@ static TCGv cpu_gregs[32]; static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t; static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr; static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl; -static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst; +static TCGv cpu_pr, cpu_fpscr, cpu_fpul; +static TCGv cpu_lock_addr, cpu_lock_value; static TCGv cpu_fregs[32]; =20 /* internal register indexes */ @@ -156,8 +157,12 @@ void sh4_translate_init(void) offsetof(CPUSH4State, delayed_cond), "_delayed_cond_"); - cpu_ldst =3D tcg_global_mem_new_i32(cpu_env, - offsetof(CPUSH4State, ldst), "_ldst_"); + cpu_lock_addr =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, lock_addr), + "_lock_addr_"); + cpu_lock_value =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPUSH4State, lock_value), + "_lock_value_"); =20 for (i =3D 0; i < 32; i++) cpu_fregs[i] =3D tcg_global_mem_new_i32(cpu_env, @@ -1558,31 +1563,63 @@ static void _decode_opc(DisasContext * ctx) return; case 0x0073: /* MOVCO.L - LDST -> T - If (T =3D=3D 1) R0 -> (Rn) - 0 -> LDST - */ + * LDST -> T + * If (T =3D=3D 1) R0 -> (Rn) + * 0 -> LDST + * + * The above description doesn't work in a parallel context. + * Since we currently support no smp boards, this implies user-mod= e. + * But we can still support the official mechanism while user-mode + * is single-threaded. */ CHECK_SH4A { - TCGLabel *label =3D gen_new_label(); - tcg_gen_mov_i32(cpu_sr_t, cpu_ldst); - tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label); - tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL); - gen_set_label(label); - tcg_gen_movi_i32(cpu_ldst, 0); - return; + TCGLabel *fail =3D gen_new_label(); + TCGLabel *done =3D gen_new_label(); + + if (parallel_cpus) { + TCGv tmp; + + tcg_gen_brcond_i32(TCG_COND_NE, REG(B11_8), cpu_lock_addr,= fail); + tmp =3D tcg_temp_new(); + tcg_gen_atomic_cmpxchg_i32(tmp, REG(B11_8), cpu_lock_value, + REG(0), ctx->memidx, MO_TEUL); + tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, tmp, cpu_lock_v= alue); + tcg_temp_free(tmp); + } else { + tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_lock_addr, -1, fail); + tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TE= UL); + tcg_gen_movi_i32(cpu_sr_t, 1); + } + tcg_gen_br(done); + + gen_set_label(fail); + tcg_gen_movi_i32(cpu_sr_t, 0); + + gen_set_label(done); + tcg_gen_movi_i32(cpu_lock_addr, -1); } + return; case 0x0063: /* MOVLI.L @Rm,R0 - 1 -> LDST - (Rm) -> R0 - When interrupt/exception - occurred 0 -> LDST - */ + * 1 -> LDST + * (Rm) -> R0 + * When interrupt/exception + * occurred 0 -> LDST + * + * In a parallel context, we must also save the loaded value + * for use with the cmpxchg that we'll use with movco.l. */ CHECK_SH4A - tcg_gen_movi_i32(cpu_ldst, 0); - tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); - tcg_gen_movi_i32(cpu_ldst, 1); + if (parallel_cpus) { + TCGv tmp =3D tcg_temp_new(); + tcg_gen_mov_i32(tmp, REG(B11_8)); + tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); + tcg_gen_mov_i32(cpu_lock_value, REG(0)); + tcg_gen_mov_i32(cpu_lock_addr, tmp); + tcg_temp_free(tmp); + } else { + tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); + tcg_gen_movi_i32(cpu_lock_addr, 0); + } return; case 0x0093: /* ocbi @Rn */ { --=20 2.13.5 From nobody Tue May 7 18:43:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504810364301587.9960880273586; Thu, 7 Sep 2017 11:52:44 -0700 (PDT) Received: from localhost ([::1]:41772 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1us-0001A4-Vj for importer@patchew.org; Thu, 07 Sep 2017 14:52:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54134) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1tL-00009b-WA for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dq1tG-0000UY-Sv for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:08 -0400 Received: from mail-pg0-x22d.google.com ([2607:f8b0:400e:c05::22d]:34895) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dq1tG-0000Tw-KU for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:02 -0400 Received: by mail-pg0-x22d.google.com with SMTP id 188so996415pgb.2 for ; Thu, 07 Sep 2017 11:51:02 -0700 (PDT) Received: from pike.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id l74sm481401pfi.9.2017.09.07.11.51.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 11:51:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=c51vYkb1GwmgGJFPbsnYbSf4DXjQs1LHm4YBN3duoa4=; b=V3j5YqkQ/q+CaZ1f2IFdzD2popOiJHoIfFJ5FxzkD36HIUiPjCZsxXRCrmq4Z27EuT jQvXX1CiVqvQlXawAv398OsF5HWHk6FuhARpG/iI6OaVaQy96yQEt80RHcBzmE+bICKn lNle/AXYh90HkiupDJ9Yrh/sxX6/G2Xj56s7I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c51vYkb1GwmgGJFPbsnYbSf4DXjQs1LHm4YBN3duoa4=; b=hh/J6nMIuukSPcrmIbbAtXNOfwj88XdXIv5nPOpVAiIIpITmYP513bqyp7jAO6eaPj T3ppp09e+NcHjyFxf02gOmgAisp2jxHCiMD6hOzl1Quw7bhEZZuvUzzA35+U3vOKjrFy CK7QvUk6ltliPTfBGMz2y9cbihNZ+5OW4nMETx4GwBHB0f8RIAGCKnPCFCRwsctydehh 5UFC0+DQe7q1Wfm/tX6ML2zrGcC3/6rEHCz+EnthxCIPUrefNHygMvSAzMSBNeuWqIYn DCZH4VPgflUOdhRw4LbXS/n6TKfDurSiEtvRCkJrI2/EpmIfM1PF/s65enXpigNjD9aB HZFw== X-Gm-Message-State: AHPjjUgIOacHZe7SjsHwYA7VNGNLB38HB1GFKef00PmGC0ZuBTUXYaD2 rjj/GYR9DDmMnGtURNIb6A== X-Google-Smtp-Source: ADKCNb77UgRJZhNSa7CptIdGYkSuMb9fNDflJ6+N5mtnm8ONVwq4CxLk603ba3BYzt6f5kS7GexxcA== X-Received: by 10.99.99.197 with SMTP id x188mr321514pgb.298.1504810261234; Thu, 07 Sep 2017 11:51:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 11:50:54 -0700 Message-Id: <20170907185057.23421-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907185057.23421-1-richard.henderson@linaro.org> References: <20170907185057.23421-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: [Qemu-devel] [PATCH v2 2/5] target/sh4: Convert to DisasJumpType X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson --- target/sh4/translate.c | 65 +++++++++++++++++++++++-----------------------= ---- 1 file changed, 30 insertions(+), 35 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 4365b21624..6e03370871 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -25,10 +25,9 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" - +#include "exec/translator.h" #include "trace-tcg.h" #include "exec/log.h" =20 @@ -39,7 +38,7 @@ typedef struct DisasContext { uint16_t opcode; uint32_t tbflags; /* should stay unmodified during the TB translati= on */ uint32_t envflags; /* should stay in sync with env->flags using TCG = ops */ - int bstate; + DisasJumpType bstate; int memidx; int gbank; int fbank; @@ -55,14 +54,10 @@ typedef struct DisasContext { #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD))) #endif =20 -enum { - BS_NONE =3D 0, /* We go out of the TB without reaching a branch or= an - * exception condition - */ - BS_STOP =3D 1, /* We want to stop translation for any reason */ - BS_BRANCH =3D 2, /* We reached a branch condition */ - BS_EXCP =3D 3, /* We reached an exception condition */ -}; +/* Target-specific values for ctx->bstate. */ +/* We want to exit back to the cpu loop for some reason. + Usually this is to recognize interrupts immediately. */ +#define DISAS_STOP DISAS_TARGET_0 =20 /* global register indexes */ static TCGv_env cpu_env; @@ -269,6 +264,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, targe= t_ulong dest) tcg_gen_lookup_and_goto_ptr(cpu_pc); } } + ctx->bstate =3D DISAS_NORETURN; } =20 static void gen_jump(DisasContext * ctx) @@ -315,7 +311,7 @@ static void gen_conditional_jump(DisasContext *ctx, tar= get_ulong dest, gen_goto_tb(ctx, 0, dest); gen_set_label(l1); gen_goto_tb(ctx, 1, ctx->pc + 2); - ctx->bstate =3D BS_BRANCH; + ctx->bstate =3D DISAS_NORETURN; } =20 /* Delayed conditional jump (bt or bf) */ @@ -338,6 +334,7 @@ static void gen_delayed_conditional_jump(DisasContext *= ctx) gen_jump(ctx); =20 gen_set_label(l1); + ctx->bstate =3D DISAS_NEXT; return; } =20 @@ -479,7 +476,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); ctx->envflags |=3D DELAY_SLOT_RTE; ctx->delayed_pc =3D (uint32_t) - 1; - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; return; case 0x0058: /* sets */ tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S)); @@ -490,17 +487,17 @@ static void _decode_opc(DisasContext * ctx) case 0xfbfd: /* frchg */ CHECK_FPSCR_PR_0 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; return; case 0xf3fd: /* fschg */ CHECK_FPSCR_PR_0 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; return; case 0xf7fd: /* fpchg */ CHECK_SH4A tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_PR); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; return; case 0x0009: /* nop */ return; @@ -535,7 +532,7 @@ static void _decode_opc(DisasContext * ctx) region (stored in R0) in the next TB. */ if (B11_8 =3D=3D 15 && B7_0s < 0 && parallel_cpus) { ctx->envflags =3D deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0= s); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; } #endif tcg_gen_movi_i32(REG(B11_8), B7_0s); @@ -1320,7 +1317,7 @@ static void _decode_opc(DisasContext * ctx) imm =3D tcg_const_i32(B7_0); gen_helper_trapa(cpu_env, imm); tcg_temp_free(imm); - ctx->bstate =3D BS_EXCP; + ctx->bstate =3D DISAS_NORETURN; } return; case 0xc800: /* tst #imm,R0 */ @@ -1429,7 +1426,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3); gen_write_sr(val); tcg_temp_free(val); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; } return; case 0x4007: /* ldc.l @Rm+,SR */ @@ -1441,7 +1438,7 @@ static void _decode_opc(DisasContext * ctx) gen_write_sr(val); tcg_temp_free(val); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; } return; case 0x0002: /* stc SR,Rn */ @@ -1503,7 +1500,7 @@ static void _decode_opc(DisasContext * ctx) case 0x406a: /* lds Rm,FPSCR */ CHECK_FPU_ENABLED gen_helper_ld_fpscr(cpu_env, REG(B11_8)); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; return; case 0x4066: /* lds.l @Rm+,FPSCR */ CHECK_FPU_ENABLED @@ -1513,7 +1510,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); gen_helper_ld_fpscr(cpu_env, addr); tcg_temp_free(addr); - ctx->bstate =3D BS_STOP; + ctx->bstate =3D DISAS_STOP; } return; case 0x006a: /* sts FPSCR,Rn */ @@ -1849,7 +1846,7 @@ static void _decode_opc(DisasContext * ctx) gen_save_cpu_state(ctx, true); gen_helper_raise_illegal_instruction(cpu_env); } - ctx->bstate =3D BS_EXCP; + ctx->bstate =3D DISAS_NORETURN; return; =20 do_fpu_disabled: @@ -1859,7 +1856,7 @@ static void _decode_opc(DisasContext * ctx) } else { gen_helper_raise_fpu_disable(cpu_env); } - ctx->bstate =3D BS_EXCP; + ctx->bstate =3D DISAS_NORETURN; return; } =20 @@ -1885,7 +1882,6 @@ static void decode_opc(DisasContext * ctx) ctx->envflags &=3D ~GUSA_MASK; =20 tcg_gen_movi_i32(cpu_flags, ctx->envflags); - ctx->bstate =3D BS_BRANCH; if (old_flags & DELAY_SLOT_CONDITIONAL) { gen_delayed_conditional_jump(ctx); } else { @@ -2256,7 +2252,7 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) ctx->envflags |=3D GUSA_EXCLUSIVE; gen_save_cpu_state(ctx, false); gen_helper_exclusive(cpu_env); - ctx->bstate =3D BS_EXCP; + ctx->bstate =3D DISAS_NORETURN; =20 /* We're not executing an instruction, but we must report one for the purposes of accounting within the TB. We might as well report the @@ -2279,7 +2275,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) ctx.pc =3D pc_start; ctx.tbflags =3D (uint32_t)tb->flags; ctx.envflags =3D tb->flags & TB_FLAG_ENVFLAGS_MASK; - ctx.bstate =3D BS_NONE; + ctx.bstate =3D DISAS_NEXT; ctx.memidx =3D (ctx.tbflags & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; /* We don't know if the delayed pc came from a dynamic or static branc= h, so assume it is a dynamic branch. */ @@ -2317,7 +2313,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) } #endif =20 - while (ctx.bstate =3D=3D BS_NONE + while (ctx.bstate =3D=3D DISAS_NEXT && num_insns < max_insns && !tcg_op_buf_full()) { tcg_gen_insn_start(ctx.pc, ctx.envflags); @@ -2327,7 +2323,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) /* We have hit a breakpoint - make sure PC is up-to-date */ gen_save_cpu_state(&ctx, true); gen_helper_debug(cpu_env); - ctx.bstate =3D BS_EXCP; + ctx.bstate =3D DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that @@ -2358,19 +2354,18 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) gen_helper_debug(cpu_env); } else { switch (ctx.bstate) { - case BS_STOP: + case DISAS_STOP: gen_save_cpu_state(&ctx, true); tcg_gen_exit_tb(0); break; - case BS_NONE: + case DISAS_NEXT: gen_save_cpu_state(&ctx, false); gen_goto_tb(&ctx, 0, ctx.pc); break; - case BS_EXCP: - /* fall through */ - case BS_BRANCH: - default: + case DISAS_NORETURN: break; + default: + g_assert_not_reached(); } } =20 --=20 2.13.5 From nobody Tue May 7 18:43:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504810487636273.7411657178113; Thu, 7 Sep 2017 11:54:47 -0700 (PDT) Received: from localhost ([::1]:41779 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1ws-00032i-Md for importer@patchew.org; Thu, 07 Sep 2017 14:54:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54143) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1tM-0000A4-PZ for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dq1tI-0000VH-7l for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:08 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:35759) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dq1tI-0000Ur-1b for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:04 -0400 Received: by mail-pf0-x233.google.com with SMTP id g13so834775pfm.2 for ; Thu, 07 Sep 2017 11:51:03 -0700 (PDT) Received: from pike.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id l74sm481401pfi.9.2017.09.07.11.51.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 11:51:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+obuuT3KDqk3lML+4zyj2n1JXa6qR78HKFY2pMtYFmA=; b=JnwOSDVH65IdZBt4GomioBwawVzPBNGhhQmwF+vK/2rG8mb1dPW+0r5sjhaa8la1yB eW50md0xERs5pLkDps2lvfdyuhLvuuRu38xI7o1LJwIDgSJDyUiiQx5vW9qGrahXjsTn gnn3BHKaLGUc5WJQVdFwN1ty66mD3JZ9bawrY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+obuuT3KDqk3lML+4zyj2n1JXa6qR78HKFY2pMtYFmA=; b=KJcoPz6MdPjWJyp9pZAYL77DI4q0E98RtIRJPAWmrpn95z0Y/nbsKm//YFLCZ9mYb8 jYEbRv6gkcSawubzmNGTPLmug1OtP+JQwV6dKehL99eSF7CuXh1TQBnQMfNhtgXM3qFN /ZheoG5eudxMjQV9UKh3FX2umSD4l0Tf2xlN8SBIXsdcoDfXfGmLOq1VpqqFSM0SHLE8 ijMsvkl00UxQ7ZwF3JXNQAnm3EJJGblbu5x+2ltNOGrRu1Z7q83/t+ZlzvaGsHS1RFNq bLfPV7kqeN/62iP0e8uwjvcmxXLgVHCJYWvp07JVVVzZ2YLXaGbg5UBvvskLSRD4VQGI 2+Hw== X-Gm-Message-State: AHPjjUg+W91CLsei8STNdDbdxxAVN0s+xra2duN8Igs7sRTJrDRFW6Vb YHzsfVpbgiRWjdvBFTOzfQ== X-Google-Smtp-Source: ADKCNb5Pq79h9mMTbhRSZKBQQqool5j18X6wC25rhbhLh6sM3GsB/EHoOtieaQym5SIkl9jr/MQn1A== X-Received: by 10.99.44.86 with SMTP id s83mr299904pgs.341.1504810262625; Thu, 07 Sep 2017 11:51:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 11:50:55 -0700 Message-Id: <20170907185057.23421-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907185057.23421-1-richard.henderson@linaro.org> References: <20170907185057.23421-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PATCH v2 3/5] target/sh4: Do not singlestep after exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson If we've already raised an exception (and set NORETURN), do not emit unreachable code to raise a debug exception. Note that gen_goto_tb takes single-stepping into account. Signed-off-by: Richard Henderson --- target/sh4/translate.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 6e03370871..5cda27cc0a 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -281,6 +281,7 @@ static void gen_jump(DisasContext * ctx) } else { tcg_gen_lookup_and_goto_ptr(cpu_pc); } + ctx->bstate =3D DISAS_NORETURN; } else { gen_goto_tb(ctx, 0, ctx->delayed_pc); } @@ -2349,24 +2350,23 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) ctx.envflags &=3D ~GUSA_MASK; } =20 - if (cs->singlestep_enabled) { + switch (ctx.bstate) { + case DISAS_STOP: gen_save_cpu_state(&ctx, true); - gen_helper_debug(cpu_env); - } else { - switch (ctx.bstate) { - case DISAS_STOP: - gen_save_cpu_state(&ctx, true); + if (cs->singlestep_enabled) { + gen_helper_debug(cpu_env); + } else { tcg_gen_exit_tb(0); - break; - case DISAS_NEXT: - gen_save_cpu_state(&ctx, false); - gen_goto_tb(&ctx, 0, ctx.pc); - break; - case DISAS_NORETURN: - break; - default: - g_assert_not_reached(); - } + } + break; + case DISAS_NEXT: + gen_save_cpu_state(&ctx, false); + gen_goto_tb(&ctx, 0, ctx.pc); + break; + case DISAS_NORETURN: + break; + default: + g_assert_not_reached(); } =20 gen_tb_end(tb, num_insns); --=20 2.13.5 From nobody Tue May 7 18:43:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150481053589558.1701920935584; Thu, 7 Sep 2017 11:55:35 -0700 (PDT) Received: from localhost ([::1]:41786 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1xe-0003qR-U8 for importer@patchew.org; Thu, 07 Sep 2017 14:55:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54189) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1tQ-0000Dx-B1 for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dq1tK-0000Wa-7N for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:12 -0400 Received: from mail-pg0-x22e.google.com ([2607:f8b0:400e:c05::22e]:33555) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dq1tJ-0000W0-VB for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:06 -0400 Received: by mail-pg0-x22e.google.com with SMTP id t3so1011170pgt.0 for ; Thu, 07 Sep 2017 11:51:05 -0700 (PDT) Received: from pike.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id l74sm481401pfi.9.2017.09.07.11.51.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 11:51:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4i80/mNJBgdsRZ6rI0oMRFx3xHTE62r5Hp+trlIew1s=; b=U4JrNREynaBrJh9am2WUR74AJwRgjiPSL5k00YBPqoxbdQLa3S62Ika7zu++3JsdAc /WPA0Ozz6JSw8jJ18zuBzda1jYiZjElZXaS8K2Pudw5bj1AbsBvEYKE9X/qW1gBFJAk8 xmNt7DUno4H+gzt9fIEEBN6tZcyVp4/8yMmqo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4i80/mNJBgdsRZ6rI0oMRFx3xHTE62r5Hp+trlIew1s=; b=rRs15+8e3DUepEm3OfbHa1LdqEZqWWXzz+zfhFG3Nbna8Vd3WpLX7Tb/+8cGJFvxv9 ZXq70CAkOkwNF/wVp6jnqd7Ry+aD2JPlawoM0w9wQjTbGVaEgG6+RsZasGGsr6Jfdqlg I2yrvu7ObGqgMT2g922cHhcVWJWamvnpwVqSX7+UqQCbvPM/G73g0g2hpyWI/0DjWiud r+s4QF7ubEU3MINbV9VDLy+g7lQGHORZ6rvtPYZEGx4lyKLHjiaLXmCVJqU9vttnsBSm 0YWcmpVBHl3ctU+v/irnxDYFfbf4YXhAVZySkRVxY6EcStjazHn7W3wIZtTHHXcbOXMr XXJg== X-Gm-Message-State: AHPjjUjBNxRLh9ZlA4ENRlB/+3Koq4jSPkfwl0U9JN7OHeX4bs5eiUjB Sf4j1xyJXB+EyApyAbloSg== X-Google-Smtp-Source: ADKCNb57dtXnGFCor03Cox8ncJNeJgxgl0aX8WZKcibrtsPz0r308SP28Y3FjSx4VgZHV++Uq6MN3A== X-Received: by 10.98.245.207 with SMTP id b76mr307435pfm.223.1504810264426; Thu, 07 Sep 2017 11:51:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 11:50:56 -0700 Message-Id: <20170907185057.23421-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907185057.23421-1-richard.henderson@linaro.org> References: <20170907185057.23421-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22e Subject: [Qemu-devel] [PATCH v2 4/5] target/sh4: Convert to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson --- target/sh4/translate.c | 146 ++++++++++++++++++++++++---------------------= ---- 1 file changed, 73 insertions(+), 73 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 5cda27cc0a..ed462bab12 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -33,19 +33,19 @@ =20 =20 typedef struct DisasContext { - struct TranslationBlock *tb; - target_ulong pc; - uint16_t opcode; - uint32_t tbflags; /* should stay unmodified during the TB translati= on */ - uint32_t envflags; /* should stay in sync with env->flags using TCG = ops */ - DisasJumpType bstate; + DisasContextBase base; + + uint32_t tbflags; /* should stay unmodified during the TB translation= */ + uint32_t envflags; /* should stay in sync with env->flags using TCG op= s */ int memidx; int gbank; int fbank; uint32_t delayed_pc; - int singlestep_enabled; uint32_t features; - int has_movcal; + + uint16_t opcode; + + bool has_movcal; } DisasContext; =20 #if defined(CONFIG_USER_ONLY) @@ -54,7 +54,7 @@ typedef struct DisasContext { #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD))) #endif =20 -/* Target-specific values for ctx->bstate. */ +/* Target-specific values for ctx->base.is_jmp. */ /* We want to exit back to the cpu loop for some reason. Usually this is to recognize interrupts immediately. */ #define DISAS_STOP DISAS_TARGET_0 @@ -220,7 +220,7 @@ static void gen_write_sr(TCGv src) static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc) { if (save_pc) { - tcg_gen_movi_i32(cpu_pc, ctx->pc); + tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); } if (ctx->delayed_pc !=3D (uint32_t) -1) { tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); @@ -238,11 +238,11 @@ static inline bool use_exit_tb(DisasContext *ctx) static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { /* Use a direct jump if in same page and singlestep not enabled */ - if (unlikely(ctx->singlestep_enabled || use_exit_tb(ctx))) { + if (unlikely(ctx->base.singlestep_enabled || use_exit_tb(ctx))) { return false; } #ifndef CONFIG_USER_ONLY - return (ctx->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MAS= K); + return (ctx->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAG= E_MASK); #else return true; #endif @@ -253,10 +253,10 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar= get_ulong dest) if (use_goto_tb(ctx, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(cpu_pc, dest); - tcg_gen_exit_tb((uintptr_t)ctx->tb + n); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb + n); } else { tcg_gen_movi_i32(cpu_pc, dest); - if (ctx->singlestep_enabled) { + if (ctx->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else if (use_exit_tb(ctx)) { tcg_gen_exit_tb(0); @@ -264,7 +264,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, targe= t_ulong dest) tcg_gen_lookup_and_goto_ptr(cpu_pc); } } - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_jump(DisasContext * ctx) @@ -274,14 +274,14 @@ static void gen_jump(DisasContext * ctx) delayed jump as immediate jump are conditinal jumps */ tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); tcg_gen_discard_i32(cpu_delayed_pc); - if (ctx->singlestep_enabled) { + if (ctx->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else if (use_exit_tb(ctx)) { tcg_gen_exit_tb(0); } else { tcg_gen_lookup_and_goto_ptr(cpu_pc); } - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; } else { gen_goto_tb(ctx, 0, ctx->delayed_pc); } @@ -311,8 +311,8 @@ static void gen_conditional_jump(DisasContext *ctx, tar= get_ulong dest, tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1); gen_goto_tb(ctx, 0, dest); gen_set_label(l1); - gen_goto_tb(ctx, 1, ctx->pc + 2); - ctx->bstate =3D DISAS_NORETURN; + gen_goto_tb(ctx, 1, ctx->base.pc_next + 2); + ctx->base.is_jmp =3D DISAS_NORETURN; } =20 /* Delayed conditional jump (bt or bf) */ @@ -335,12 +335,12 @@ static void gen_delayed_conditional_jump(DisasContext= * ctx) gen_jump(ctx); =20 gen_set_label(l1); - ctx->bstate =3D DISAS_NEXT; + ctx->base.is_jmp =3D DISAS_NEXT; return; } =20 tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1); - gen_goto_tb(ctx, 1, ctx->pc + 2); + gen_goto_tb(ctx, 1, ctx->base.pc_next + 2); gen_set_label(l1); gen_jump(ctx); } @@ -477,7 +477,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); ctx->envflags |=3D DELAY_SLOT_RTE; ctx->delayed_pc =3D (uint32_t) - 1; - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; return; case 0x0058: /* sets */ tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S)); @@ -488,23 +488,23 @@ static void _decode_opc(DisasContext * ctx) case 0xfbfd: /* frchg */ CHECK_FPSCR_PR_0 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; return; case 0xf3fd: /* fschg */ CHECK_FPSCR_PR_0 tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; return; case 0xf7fd: /* fpchg */ CHECK_SH4A tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_PR); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; return; case 0x0009: /* nop */ return; case 0x001b: /* sleep */ CHECK_PRIVILEGED - tcg_gen_movi_i32(cpu_pc, ctx->pc + 2); + tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next + 2); gen_helper_sleep(cpu_env); return; } @@ -533,21 +533,21 @@ static void _decode_opc(DisasContext * ctx) region (stored in R0) in the next TB. */ if (B11_8 =3D=3D 15 && B7_0s < 0 && parallel_cpus) { ctx->envflags =3D deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0= s); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; } #endif tcg_gen_movi_i32(REG(B11_8), B7_0s); return; case 0x9000: /* mov.w @(disp,PC),Rn */ { - TCGv addr =3D tcg_const_i32(ctx->pc + 4 + B7_0 * 2); + TCGv addr =3D tcg_const_i32(ctx->base.pc_next + 4 + B7_0 * 2); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); tcg_temp_free(addr); } return; case 0xd000: /* mov.l @(disp,PC),Rn */ { - TCGv addr =3D tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3); + TCGv addr =3D tcg_const_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); tcg_temp_free(addr); } @@ -557,13 +557,13 @@ static void _decode_opc(DisasContext * ctx) return; case 0xa000: /* bra disp */ CHECK_NOT_DELAY_SLOT - ctx->delayed_pc =3D ctx->pc + 4 + B11_0s * 2; + ctx->delayed_pc =3D ctx->base.pc_next + 4 + B11_0s * 2; ctx->envflags |=3D DELAY_SLOT; return; case 0xb000: /* bsr disp */ CHECK_NOT_DELAY_SLOT - tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); - ctx->delayed_pc =3D ctx->pc + 4 + B11_0s * 2; + tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); + ctx->delayed_pc =3D ctx->base.pc_next + 4 + B11_0s * 2; ctx->envflags |=3D DELAY_SLOT; return; } @@ -1190,22 +1190,22 @@ static void _decode_opc(DisasContext * ctx) return; case 0x8b00: /* bf label */ CHECK_NOT_DELAY_SLOT - gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, false); + gen_conditional_jump(ctx, ctx->base.pc_next + 4 + B7_0s * 2, false= ); return; case 0x8f00: /* bf/s label */ CHECK_NOT_DELAY_SLOT tcg_gen_xori_i32(cpu_delayed_cond, cpu_sr_t, 1); - ctx->delayed_pc =3D ctx->pc + 4 + B7_0s * 2; + ctx->delayed_pc =3D ctx->base.pc_next + 4 + B7_0s * 2; ctx->envflags |=3D DELAY_SLOT_CONDITIONAL; return; case 0x8900: /* bt label */ CHECK_NOT_DELAY_SLOT - gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, true); + gen_conditional_jump(ctx, ctx->base.pc_next + 4 + B7_0s * 2, true); return; case 0x8d00: /* bt/s label */ CHECK_NOT_DELAY_SLOT tcg_gen_mov_i32(cpu_delayed_cond, cpu_sr_t); - ctx->delayed_pc =3D ctx->pc + 4 + B7_0s * 2; + ctx->delayed_pc =3D ctx->base.pc_next + 4 + B7_0s * 2; ctx->envflags |=3D DELAY_SLOT_CONDITIONAL; return; case 0x8800: /* cmp/eq #imm,R0 */ @@ -1292,7 +1292,7 @@ static void _decode_opc(DisasContext * ctx) } return; case 0xc700: /* mova @(disp,PC),R0 */ - tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3); + tcg_gen_movi_i32(REG(0), ((ctx->base.pc_next & 0xfffffffc) + 4 + B7_0 * 4= ) & ~3); return; case 0xcb00: /* or #imm,R0 */ tcg_gen_ori_i32(REG(0), REG(0), B7_0); @@ -1318,7 +1318,7 @@ static void _decode_opc(DisasContext * ctx) imm =3D tcg_const_i32(B7_0); gen_helper_trapa(cpu_env, imm); tcg_temp_free(imm); - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; } return; case 0xc800: /* tst #imm,R0 */ @@ -1386,13 +1386,13 @@ static void _decode_opc(DisasContext * ctx) switch (ctx->opcode & 0xf0ff) { case 0x0023: /* braf Rn */ CHECK_NOT_DELAY_SLOT - tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4); + tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->base.pc_next + 4); ctx->envflags |=3D DELAY_SLOT; ctx->delayed_pc =3D (uint32_t) - 1; return; case 0x0003: /* bsrf Rn */ CHECK_NOT_DELAY_SLOT - tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); + tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr); ctx->envflags |=3D DELAY_SLOT; ctx->delayed_pc =3D (uint32_t) - 1; @@ -1415,7 +1415,7 @@ static void _decode_opc(DisasContext * ctx) return; case 0x400b: /* jsr @Rn */ CHECK_NOT_DELAY_SLOT - tcg_gen_movi_i32(cpu_pr, ctx->pc + 4); + tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4); tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); ctx->envflags |=3D DELAY_SLOT; ctx->delayed_pc =3D (uint32_t) - 1; @@ -1427,7 +1427,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3); gen_write_sr(val); tcg_temp_free(val); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; } return; case 0x4007: /* ldc.l @Rm+,SR */ @@ -1439,7 +1439,7 @@ static void _decode_opc(DisasContext * ctx) gen_write_sr(val); tcg_temp_free(val); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; } return; case 0x0002: /* stc SR,Rn */ @@ -1501,7 +1501,7 @@ static void _decode_opc(DisasContext * ctx) case 0x406a: /* lds Rm,FPSCR */ CHECK_FPU_ENABLED gen_helper_ld_fpscr(cpu_env, REG(B11_8)); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; return; case 0x4066: /* lds.l @Rm+,FPSCR */ CHECK_FPU_ENABLED @@ -1511,7 +1511,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); gen_helper_ld_fpscr(cpu_env, addr); tcg_temp_free(addr); - ctx->bstate =3D DISAS_STOP; + ctx->base.is_jmp =3D DISAS_STOP; } return; case 0x006a: /* sts FPSCR,Rn */ @@ -1835,7 +1835,7 @@ static void _decode_opc(DisasContext * ctx) } #if 0 fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", - ctx->opcode, ctx->pc); + ctx->opcode, ctx->base.pc_next); fflush(stderr); #endif do_illegal: @@ -1847,7 +1847,7 @@ static void _decode_opc(DisasContext * ctx) gen_save_cpu_state(ctx, true); gen_helper_raise_illegal_instruction(cpu_env); } - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; return; =20 do_fpu_disabled: @@ -1857,7 +1857,7 @@ static void _decode_opc(DisasContext * ctx) } else { gen_helper_raise_fpu_disable(cpu_env); } - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; return; } =20 @@ -1909,8 +1909,8 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) int mv_src, mt_dst, st_src, st_mop; TCGv op_arg; =20 - uint32_t pc =3D ctx->pc; - uint32_t pc_end =3D ctx->tb->cs_base; + uint32_t pc =3D ctx->base.pc_next; + uint32_t pc_end =3D ctx->base.tb->cs_base; int backup =3D sextract32(ctx->tbflags, GUSA_SHIFT, 8); int max_insns =3D (pc_end - pc) / 2; int i; @@ -2240,7 +2240,7 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) =20 /* The entire region has been translated. */ ctx->envflags &=3D ~GUSA_MASK; - ctx->pc =3D pc_end; + ctx->base.pc_next =3D pc_end; return max_insns; =20 fail: @@ -2253,13 +2253,13 @@ static int decode_gusa(DisasContext *ctx, CPUSH4Sta= te *env, int *pmax_insns) ctx->envflags |=3D GUSA_EXCLUSIVE; gen_save_cpu_state(ctx, false); gen_helper_exclusive(cpu_env); - ctx->bstate =3D DISAS_NORETURN; + ctx->base.is_jmp =3D DISAS_NORETURN; =20 /* We're not executing an instruction, but we must report one for the purposes of accounting within the TB. We might as well report the - entire region consumed via ctx->pc so that it's immediately availab= le - in the disassembly dump. */ - ctx->pc =3D pc_end; + entire region consumed via ctx->base.pc_next so that it's immediate= ly + available in the disassembly dump. */ + ctx->base.pc_next =3D pc_end; return 1; } #endif @@ -2273,16 +2273,16 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) int max_insns; =20 pc_start =3D tb->pc; - ctx.pc =3D pc_start; + ctx.base.pc_next =3D pc_start; ctx.tbflags =3D (uint32_t)tb->flags; ctx.envflags =3D tb->flags & TB_FLAG_ENVFLAGS_MASK; - ctx.bstate =3D DISAS_NEXT; + ctx.base.is_jmp =3D DISAS_NEXT; ctx.memidx =3D (ctx.tbflags & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; /* We don't know if the delayed pc came from a dynamic or static branc= h, so assume it is a dynamic branch. */ ctx.delayed_pc =3D -1; /* use delayed pc from env pointer */ - ctx.tb =3D tb; - ctx.singlestep_enabled =3D cs->singlestep_enabled; + ctx.base.tb =3D tb; + ctx.base.singlestep_enabled =3D cs->singlestep_enabled; ctx.features =3D env->features; ctx.has_movcal =3D (ctx.tbflags & TB_FLAG_PENDING_MOVCA); ctx.gbank =3D ((ctx.tbflags & (1 << SR_MD)) && @@ -2297,11 +2297,11 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) =20 /* Since the ISA is fixed-width, we can bound by the number of instructions remaining on the page. */ - num_insns =3D -(ctx.pc | TARGET_PAGE_MASK) / 2; + num_insns =3D -(ctx.base.pc_next | TARGET_PAGE_MASK) / 2; max_insns =3D MIN(max_insns, num_insns); =20 /* Single stepping means just that. */ - if (ctx.singlestep_enabled || singlestep) { + if (ctx.base.singlestep_enabled || singlestep) { max_insns =3D 1; } =20 @@ -2314,22 +2314,22 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) } #endif =20 - while (ctx.bstate =3D=3D DISAS_NEXT + while (ctx.base.is_jmp =3D=3D DISAS_NEXT && num_insns < max_insns && !tcg_op_buf_full()) { - tcg_gen_insn_start(ctx.pc, ctx.envflags); + tcg_gen_insn_start(ctx.base.pc_next, ctx.envflags); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { /* We have hit a breakpoint - make sure PC is up-to-date */ gen_save_cpu_state(&ctx, true); gen_helper_debug(cpu_env); - ctx.bstate =3D DISAS_NORETURN; + ctx.base.is_jmp =3D DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - ctx.pc +=3D 2; + ctx.base.pc_next +=3D 2; break; } =20 @@ -2337,9 +2337,9 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) gen_io_start(); } =20 - ctx.opcode =3D cpu_lduw_code(env, ctx.pc); + ctx.opcode =3D cpu_lduw_code(env, ctx.base.pc_next); decode_opc(&ctx); - ctx.pc +=3D 2; + ctx.base.pc_next +=3D 2; } if (tb->cflags & CF_LAST_IO) { gen_io_end(); @@ -2350,10 +2350,10 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) ctx.envflags &=3D ~GUSA_MASK; } =20 - switch (ctx.bstate) { + switch (ctx.base.is_jmp) { case DISAS_STOP: gen_save_cpu_state(&ctx, true); - if (cs->singlestep_enabled) { + if (ctx.base.singlestep_enabled) { gen_helper_debug(cpu_env); } else { tcg_gen_exit_tb(0); @@ -2361,7 +2361,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) break; case DISAS_NEXT: gen_save_cpu_state(&ctx, false); - gen_goto_tb(&ctx, 0, ctx.pc); + gen_goto_tb(&ctx, 0, ctx.base.pc_next); break; case DISAS_NORETURN: break; @@ -2371,7 +2371,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) =20 gen_tb_end(tb, num_insns); =20 - tb->size =3D ctx.pc - pc_start; + tb->size =3D ctx.base.pc_next - pc_start; tb->icount =3D num_insns; =20 #ifdef DEBUG_DISAS @@ -2379,7 +2379,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) && qemu_log_in_addr_range(pc_start)) { qemu_log_lock(); qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */ - log_target_disas(cs, pc_start, ctx.pc - pc_start, 0); + log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start, 0); qemu_log("\n"); qemu_log_unlock(); } --=20 2.13.5 From nobody Tue May 7 18:43:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504810494701241.9606886122608; Thu, 7 Sep 2017 11:54:54 -0700 (PDT) Received: from localhost ([::1]:41780 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1wz-00037w-CK for importer@patchew.org; Thu, 07 Sep 2017 14:54:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54202) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1tR-0000F0-K2 for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dq1tL-0000XV-Qi for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:13 -0400 Received: from mail-pg0-x232.google.com ([2607:f8b0:400e:c05::232]:33555) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dq1tL-0000X8-Ie for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:51:07 -0400 Received: by mail-pg0-x232.google.com with SMTP id t3so1011282pgt.0 for ; Thu, 07 Sep 2017 11:51:07 -0700 (PDT) Received: from pike.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id l74sm481401pfi.9.2017.09.07.11.51.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 11:51:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jYYKiAzIoFqTuiYuHu7WB/C983bpNQLGILsQ08P+xLU=; b=L9oXoSq2DECuoNTmPYiJrBxhVEXZjIc9k9ATFvMVK/lkF0V+6K6/GVrG8OMAxRsnu+ nG8maRpFw9w/DYrKpxBV4+zyFbOOK6TOvADFF8bN3uLapy/jpiZZPqZr3oxgSFpJ79YY RHvypP+VSJ0Uq8XqTl/wP7MvraAz8o5Zg6pOA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jYYKiAzIoFqTuiYuHu7WB/C983bpNQLGILsQ08P+xLU=; b=J5zHP3Uuay3ZCBa55xUFEEaqmcg1UZqWchxhxmu+GB9jc80/CNQx6PJVeb2vQ+9Eut QetY0iA3B9pY4rQxnf8Vw7KoZnEAd2jK835x2XLt+FjbjAQ9+QPgeBS7kYXuhtpQ3ep2 rVkFAYIVpDVA1Z2kcnQY7fyjgRPJTb/lt8JlQgRKnQmngNFLViKT7DgbfC5YRQOwNdCl RCWfkmetgJNa/Ul8qdHNu76TG60uW+2nyaKW5YZ5l4K38G5kEI2tqjh5oS/Zixqi3zXQ WbpKOGsz2iTEVHweQ7dw+Sy8KwKdJ0qy2GzVtBP2l9xtkCeKhBpPd1Aq625CIvPzkoK5 GlQA== X-Gm-Message-State: AHPjjUgLxRM7RQmMXQGtDWg+17m4jlynx8Gq9+1hvs/dZvjlWHOQA1Ro gT26VUMdYIdAkUrFA/birg== X-Google-Smtp-Source: ADKCNb4UTrOyIFVlHybwFTK+9HCXZVjleW8bbYPFbYbCgAcV7X4N0XMGttkp/qcHxC1uTU/dnLEh9w== X-Received: by 10.98.224.92 with SMTP id f89mr363499pfh.138.1504810266049; Thu, 07 Sep 2017 11:51:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 11:50:57 -0700 Message-Id: <20170907185057.23421-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907185057.23421-1-richard.henderson@linaro.org> References: <20170907185057.23421-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::232 Subject: [Qemu-devel] [PATCH v2 5/5] target/sh4: Convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson --- target/sh4/translate.c | 272 ++++++++++++++++++++++++++-------------------= ---- 1 file changed, 147 insertions(+), 125 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index ed462bab12..ca6589047b 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -34,6 +34,9 @@ =20 typedef struct DisasContext { DisasContextBase base; +#ifdef CONFIG_USER_ONLY + TranslatorOps ops; +#endif =20 uint32_t tbflags; /* should stay unmodified during the TB translation= */ uint32_t envflags; /* should stay in sync with env->flags using TCG op= s */ @@ -1892,6 +1895,100 @@ static void decode_opc(DisasContext * ctx) } =20 #ifdef CONFIG_USER_ONLY +static void sh4_tr_translate_gusa(DisasContextBase *dcbase, CPUState *cpu); +#endif + +static int sh4_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu, int max_insns) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPUSH4State *env =3D cpu->env_ptr; + uint32_t pc =3D ctx->base.pc_next; + uint32_t tbflags =3D ctx->base.tb->flags; + int bound; + + ctx->tbflags =3D tbflags; + ctx->envflags =3D tbflags & TB_FLAG_ENVFLAGS_MASK; + ctx->memidx =3D (tbflags & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; + /* We don't know if the delayed pc came from a dynamic or static branc= h, + so assume it is a dynamic branch. */ + ctx->delayed_pc =3D -1; /* use delayed pc from env pointer */ + ctx->features =3D env->features; + ctx->has_movcal =3D (tbflags & TB_FLAG_PENDING_MOVCA) !=3D 0; + ctx->gbank =3D ((tbflags & (1 << SR_MD)) && + (tbflags & (1 << SR_RB))) * 0x10; + ctx->fbank =3D tbflags & FPSCR_FR ? 0x10 : 0; + + /* Since the ISA is fixed-width, we can bound by the number + of instructions remaining on the page. */ + bound =3D -(pc | TARGET_PAGE_MASK) / 2; + max_insns =3D MIN(max_insns, bound); + +#ifdef CONFIG_USER_ONLY + if (tbflags & GUSA_MASK) { + uint32_t pc_end =3D ctx->base.tb->cs_base; + int backup =3D sextract32(ctx->tbflags, GUSA_SHIFT, 8); + int gusa_insns =3D -backup / 2; + + if (pc !=3D pc_end + backup || gusa_insns < 2) { + /* This is a malformed gUSA region. Don't do anything special, + since the interpreter is likely to get confused. */ + ctx->envflags &=3D ~GUSA_MASK; + } else if (tbflags & GUSA_EXCLUSIVE) { + /* Regardless of single-stepping or the end of the page, + we must complete execution of the gUSA region while + holding the exclusive lock. */ + max_insns =3D gusa_insns; + } else { + /* Attempt to translate to an atomic insn. */ + ctx->ops.translate_insn =3D sh4_tr_translate_gusa; + } + } +#endif + + return max_insns; +} + +static void sh4_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) +{ +} + +static void sh4_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags); +} + +static bool sh4_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cp= u, + const CPUBreakpoint *bp) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + /* We have hit a breakpoint - make sure PC is up-to-date */ + gen_save_cpu_state(ctx, true); + gen_helper_debug(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + ctx->base.pc_next +=3D 2; + return true; +} + +static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPUSH4State *env =3D cpu->env_ptr; + + ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); + decode_opc(ctx); + ctx->base.pc_next +=3D 2; +} + +#ifdef CONFIG_USER_ONLY /* For uniprocessors, SH4 uses optimistic restartable atomic sequences. Upon an interrupt, a real kernel would simply notice magic values in the registers and reset the PC to the start of the sequence. @@ -1901,35 +1998,23 @@ static void decode_opc(DisasContext * ctx) any sequence via cpu_exec_step_atomic, we can recognize the "normal" sequences and transform them into atomic operations as seen by the host. */ -static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insn= s) +static void sh4_tr_translate_gusa(DisasContextBase *dcbase, CPUState *cpu) { + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPUSH4State *env =3D cpu->env_ptr; + + int backup =3D sextract32(ctx->tbflags, GUSA_SHIFT, 8); + int max_insns =3D -backup / 2; + uint32_t pc =3D ctx->base.pc_next; + uint32_t pc_end =3D ctx->base.tb->cs_base; + uint16_t insns[5]; int ld_adr, ld_dst, ld_mop; int op_dst, op_src, op_opc; int mv_src, mt_dst, st_src, st_mop; TCGv op_arg; - - uint32_t pc =3D ctx->base.pc_next; - uint32_t pc_end =3D ctx->base.tb->cs_base; - int backup =3D sextract32(ctx->tbflags, GUSA_SHIFT, 8); - int max_insns =3D (pc_end - pc) / 2; int i; =20 - if (pc !=3D pc_end + backup || max_insns < 2) { - /* This is a malformed gUSA region. Don't do anything special, - since the interpreter is likely to get confused. */ - ctx->envflags &=3D ~GUSA_MASK; - return 0; - } - - if (ctx->tbflags & GUSA_EXCLUSIVE) { - /* Regardless of single-stepping or the end of the page, - we must complete execution of the gUSA region while - holding the exclusive lock. */ - *pmax_insns =3D max_insns; - return 0; - } - /* The state machine below will consume only a few insns. If there are more than that in a region, fail now. */ if (max_insns > ARRAY_SIZE(insns)) { @@ -2146,7 +2231,6 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) /* * Emit the operation. */ - tcg_gen_insn_start(pc, ctx->envflags); switch (op_opc) { case -1: /* No operation found. Look for exchange pattern. */ @@ -2239,9 +2323,13 @@ static int decode_gusa(DisasContext *ctx, CPUSH4Stat= e *env, int *pmax_insns) } =20 /* The entire region has been translated. */ - ctx->envflags &=3D ~GUSA_MASK; ctx->base.pc_next =3D pc_end; - return max_insns; + ctx->base.num_insns =3D max_insns; + + /* Revert to normal parsing for the rest of the TB. */ + ctx->envflags &=3D ~GUSA_MASK; + ctx->ops.translate_insn =3D sh4_tr_translate_insn; + return; =20 fail: qemu_log_mask(LOG_UNIMP, "Unrecognized gUSA sequence %08x-%08x\n", @@ -2249,7 +2337,6 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) =20 /* Restart with the EXCLUSIVE bit set, within a TB run via cpu_exec_step_atomic holding the exclusive lock. */ - tcg_gen_insn_start(pc, ctx->envflags); ctx->envflags |=3D GUSA_EXCLUSIVE; gen_save_cpu_state(ctx, false); gen_helper_exclusive(cpu_env); @@ -2260,129 +2347,64 @@ static int decode_gusa(DisasContext *ctx, CPUSH4St= ate *env, int *pmax_insns) entire region consumed via ctx->base.pc_next so that it's immediate= ly available in the disassembly dump. */ ctx->base.pc_next =3D pc_end; - return 1; } #endif =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { - CPUSH4State *env =3D cs->env_ptr; - DisasContext ctx; - target_ulong pc_start; - int num_insns; - int max_insns; - - pc_start =3D tb->pc; - ctx.base.pc_next =3D pc_start; - ctx.tbflags =3D (uint32_t)tb->flags; - ctx.envflags =3D tb->flags & TB_FLAG_ENVFLAGS_MASK; - ctx.base.is_jmp =3D DISAS_NEXT; - ctx.memidx =3D (ctx.tbflags & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; - /* We don't know if the delayed pc came from a dynamic or static branc= h, - so assume it is a dynamic branch. */ - ctx.delayed_pc =3D -1; /* use delayed pc from env pointer */ - ctx.base.tb =3D tb; - ctx.base.singlestep_enabled =3D cs->singlestep_enabled; - ctx.features =3D env->features; - ctx.has_movcal =3D (ctx.tbflags & TB_FLAG_PENDING_MOVCA); - ctx.gbank =3D ((ctx.tbflags & (1 << SR_MD)) && - (ctx.tbflags & (1 << SR_RB))) * 0x10; - ctx.fbank =3D ctx.tbflags & FPSCR_FR ? 0x10 : 0; - - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - max_insns =3D MIN(max_insns, TCG_MAX_INSNS); - - /* Since the ISA is fixed-width, we can bound by the number - of instructions remaining on the page. */ - num_insns =3D -(ctx.base.pc_next | TARGET_PAGE_MASK) / 2; - max_insns =3D MIN(max_insns, num_insns); + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - /* Single stepping means just that. */ - if (ctx.base.singlestep_enabled || singlestep) { - max_insns =3D 1; - } - - gen_tb_start(tb); - num_insns =3D 0; - -#ifdef CONFIG_USER_ONLY - if (ctx.tbflags & GUSA_MASK) { - num_insns =3D decode_gusa(&ctx, env, &max_insns); - } -#endif - - while (ctx.base.is_jmp =3D=3D DISAS_NEXT - && num_insns < max_insns - && !tcg_op_buf_full()) { - tcg_gen_insn_start(ctx.base.pc_next, ctx.envflags); - num_insns++; - - if (unlikely(cpu_breakpoint_test(cs, ctx.base.pc_next, BP_ANY))) { - /* We have hit a breakpoint - make sure PC is up-to-date */ - gen_save_cpu_state(&ctx, true); - gen_helper_debug(cpu_env); - ctx.base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx.base.pc_next +=3D 2; - break; - } - - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - ctx.opcode =3D cpu_lduw_code(env, ctx.base.pc_next); - decode_opc(&ctx); - ctx.base.pc_next +=3D 2; - } - if (tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - - if (ctx.tbflags & GUSA_EXCLUSIVE) { + if (ctx->tbflags & GUSA_EXCLUSIVE) { /* Ending the region of exclusivity. Clear the bits. */ - ctx.envflags &=3D ~GUSA_MASK; + ctx->envflags &=3D ~GUSA_MASK; } =20 - switch (ctx.base.is_jmp) { + switch (ctx->base.is_jmp) { case DISAS_STOP: - gen_save_cpu_state(&ctx, true); - if (ctx.base.singlestep_enabled) { + gen_save_cpu_state(ctx, true); + if (ctx->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else { tcg_gen_exit_tb(0); } break; - case DISAS_NEXT: - gen_save_cpu_state(&ctx, false); - gen_goto_tb(&ctx, 0, ctx.base.pc_next); + case DISAS_TOO_MANY: + gen_save_cpu_state(ctx, false); + gen_goto_tb(ctx, 0, ctx->base.pc_next); break; case DISAS_NORETURN: break; default: g_assert_not_reached(); } +} =20 - gen_tb_end(tb, num_insns); +static void sh4_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size, 0); +} =20 - tb->size =3D ctx.base.pc_next - pc_start; - tb->icount =3D num_insns; +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) +{ + static const TranslatorOps ops =3D { + .init_disas_context =3D sh4_tr_init_disas_context, + .tb_start =3D sh4_tr_tb_start, + .insn_start =3D sh4_tr_insn_start, + .breakpoint_check =3D sh4_tr_breakpoint_check, + .translate_insn =3D sh4_tr_translate_insn, + .tb_stop =3D sh4_tr_tb_stop, + .disas_log =3D sh4_tr_disas_log, + }; + DisasContext ctx; =20 -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */ - log_target_disas(cs, pc_start, ctx.base.pc_next - pc_start, 0); - qemu_log("\n"); - qemu_log_unlock(); - } +#ifdef CONFIG_USER_ONLY + /* We may switch the translate_insn hook in init_disas_context + and within translate_insn itself. */ + ctx.ops =3D ops; + translator_loop(&ctx.ops, &ctx.base, cpu, tb); +#else + translator_loop(&ops, &ctx.base, cpu, tb); #endif } =20 --=20 2.13.5