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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id r68sm464247pfi.7.2017.09.07.11.44.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 11:44:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5G4v/C4pi3nwuV9WyDzArU/Ya6lj2d15KaFSQ+W+JSA=; b=LoKbJhpm2Z+O3eHU/9LQVvKKt2S6Uq+P6ypTLYNbF03kkA+3ix/rJ64MRGPihSlNdD EN5726CO8AjTbahlXToeQbhbP0xWytK69ew+0gly+F4QxBXcSfl57ZaftnVFgD8XFTMP s/tnrgWaOrNnkjyY2llOt0VvDy/9o9b8Hx6Ck= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5G4v/C4pi3nwuV9WyDzArU/Ya6lj2d15KaFSQ+W+JSA=; b=KO7x3ii9n0mhrXb+Z9woz+eawDAp9H8zg0Ua/w3/G6Xux5V+mMwwynY+M8hEUV7rwq xRIchiocD6H4YadmkqnQUSDupjl/hvzbEVYT6XO8K4bsrGw9rtd4mi9ufLPARiGO6LIt D1FlWHOs9FTmtg3ybcxy4kZFrO/NkJyWz6tm7iln547F7rqunn8MSfCSXoqLqjZ6eWRD 7eRurRZzvATST5CtuaBHeKIy3Q/71dCa+TPVrGT2APnskl8qxQTIa5pYGsbTTAMHxGNN 2elaXD+CjwxeN6838iyTVxCZ5uADNK0wR8ofPLNHTU29RtqfkrxLzhfOiYJGegMg7IL/ mk6A== X-Gm-Message-State: AHPjjUh0OHnbMabmZJVp2QlEHHNDpq6iSFDCLuaXUNy+1L0Ok+7EFt8x L+4D1pCNqfWIHjg2+zv2/g== X-Google-Smtp-Source: ADKCNb63adOamm3Gi9qEFwaXj1E4x2s5OlplAKQVcqaVxZEtUiErb7OPpfzYHKtWw0TxQuVffnlO0g== X-Received: by 10.98.208.69 with SMTP id p66mr351299pfg.6.1504809890429; Thu, 07 Sep 2017 11:44:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 11:44:45 -0700 Message-Id: <20170907184447.22752-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907184447.22752-1-richard.henderson@linaro.org> References: <20170907184447.22752-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PULL 1/3] target/hppa: Convert to DisasJumpType X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson --- target/hppa/translate.c | 601 +++++++++++++++++++++++---------------------= ---- 1 file changed, 294 insertions(+), 307 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 900870cd5a..cb4a3e6cb4 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -24,10 +24,9 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" - +#include "exec/translator.h" #include "trace-tcg.h" #include "exec/log.h" =20 @@ -57,32 +56,22 @@ typedef struct DisasContext { bool psw_n_nonzero; } DisasContext; =20 -/* Return values from translate_one, indicating the state of the TB. - Note that zero indicates that we are not exiting the TB. */ - -typedef enum { - NO_EXIT, +/* Target-specific return values from translate_one, indicating the + state of the TB. Note that DISAS_NEXT indicates that we are not + exiting the TB. */ =20 - /* We have emitted one or more goto_tb. No fixup required. */ - EXIT_GOTO_TB, +/* We are not using a goto_tb (for whatever reason), but have updated + the iaq (for whatever reason), so don't do it again on exit. */ +#define DISAS_IAQ_N_UPDATED DISAS_TARGET_0 =20 - /* We are not using a goto_tb (for whatever reason), but have updated - the iaq (for whatever reason), so don't do it again on exit. */ - EXIT_IAQ_N_UPDATED, - - /* We are exiting the TB, but have neither emitted a goto_tb, nor - updated the iaq for the next instruction to be executed. */ - EXIT_IAQ_N_STALE, - - /* We are ending the TB with a noreturn function call, e.g. longjmp. - No following code will be executed. */ - EXIT_NORETURN, -} ExitStatus; +/* We are exiting the TB, but have neither emitted a goto_tb, nor + updated the iaq for the next instruction to be executed. */ +#define DISAS_IAQ_N_STALE DISAS_TARGET_1 =20 typedef struct DisasInsn { uint32_t insn, mask; - ExitStatus (*trans)(DisasContext *ctx, uint32_t insn, - const struct DisasInsn *f); + DisasJumpType (*trans)(DisasContext *ctx, uint32_t insn, + const struct DisasInsn *f); union { void (*ttt)(TCGv, TCGv, TCGv); void (*weww)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32); @@ -415,7 +404,7 @@ static void nullify_set(DisasContext *ctx, bool x) =20 /* Mark the end of an instruction that may have been nullified. This is the pair to nullify_over. */ -static ExitStatus nullify_end(DisasContext *ctx, ExitStatus status) +static DisasJumpType nullify_end(DisasContext *ctx, DisasJumpType status) { TCGLabel *null_lab =3D ctx->null_lab; =20 @@ -441,9 +430,9 @@ static ExitStatus nullify_end(DisasContext *ctx, ExitSt= atus status) ctx->null_cond =3D cond_make_n(); } =20 - assert(status !=3D EXIT_GOTO_TB && status !=3D EXIT_IAQ_N_UPDATED); - if (status =3D=3D EXIT_NORETURN) { - status =3D NO_EXIT; + assert(status !=3D DISAS_NORETURN && status !=3D DISAS_IAQ_N_UPDATED); + if (status =3D=3D DISAS_NORETURN) { + status =3D DISAS_NEXT; } return status; } @@ -469,16 +458,16 @@ static void gen_excp_1(int exception) tcg_temp_free_i32(t); } =20 -static ExitStatus gen_excp(DisasContext *ctx, int exception) +static DisasJumpType gen_excp(DisasContext *ctx, int exception) { copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); gen_excp_1(exception); - return EXIT_NORETURN; + return DISAS_NORETURN; } =20 -static ExitStatus gen_illegal(DisasContext *ctx) +static DisasJumpType gen_illegal(DisasContext *ctx) { nullify_over(ctx); return nullify_end(ctx, gen_excp(ctx, EXCP_SIGILL)); @@ -839,9 +828,9 @@ static TCGv do_sub_sv(DisasContext *ctx, TCGv res, TCGv= in1, TCGv in2) return sv; } =20 -static ExitStatus do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in= 2, - unsigned shift, bool is_l, bool is_tsv, bool is_t= c, - bool is_c, unsigned cf) +static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv= in2, + unsigned shift, bool is_l, bool is_tsv, bool i= s_tc, + bool is_c, unsigned cf) { TCGv dest, cb, cb_msb, sv, tmp; unsigned c =3D cf >> 1; @@ -908,11 +897,11 @@ static ExitStatus do_add(DisasContext *ctx, unsigned = rt, TCGv in1, TCGv in2, /* Install the new nullification. */ cond_free(&ctx->null_cond); ctx->null_cond =3D cond; - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in= 2, - bool is_tsv, bool is_b, bool is_tc, unsigned cf) +static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv= in2, + bool is_tsv, bool is_b, bool is_tc, unsigned c= f) { TCGv dest, sv, cb, cb_msb, zero, tmp; unsigned c =3D cf >> 1; @@ -974,11 +963,11 @@ static ExitStatus do_sub(DisasContext *ctx, unsigned = rt, TCGv in1, TCGv in2, /* Install the new nullification. */ cond_free(&ctx->null_cond); ctx->null_cond =3D cond; - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1, - TCGv in2, unsigned cf) +static DisasJumpType do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1, + TCGv in2, unsigned cf) { TCGv dest, sv; DisasCond cond; @@ -1003,11 +992,11 @@ static ExitStatus do_cmpclr(DisasContext *ctx, unsig= ned rt, TCGv in1, /* Install the new nullification. */ cond_free(&ctx->null_cond); ctx->null_cond =3D cond; - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus do_log(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in= 2, - unsigned cf, void (*fn)(TCGv, TCGv, TCGv)) +static DisasJumpType do_log(DisasContext *ctx, unsigned rt, TCGv in1, TCGv= in2, + unsigned cf, void (*fn)(TCGv, TCGv, TCGv)) { TCGv dest =3D dest_gpr(ctx, rt); =20 @@ -1020,12 +1009,12 @@ static ExitStatus do_log(DisasContext *ctx, unsigne= d rt, TCGv in1, TCGv in2, if (cf) { ctx->null_cond =3D do_log_cond(cf, dest); } - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus do_unit(DisasContext *ctx, unsigned rt, TCGv in1, - TCGv in2, unsigned cf, bool is_tc, - void (*fn)(TCGv, TCGv, TCGv)) +static DisasJumpType do_unit(DisasContext *ctx, unsigned rt, TCGv in1, + TCGv in2, unsigned cf, bool is_tc, + void (*fn)(TCGv, TCGv, TCGv)) { TCGv dest; DisasCond cond; @@ -1053,7 +1042,7 @@ static ExitStatus do_unit(DisasContext *ctx, unsigned= rt, TCGv in1, cond_free(&ctx->null_cond); ctx->null_cond =3D cond; } - return NO_EXIT; + return DISAS_NEXT; } =20 /* Emit a memory load. The modify parameter should be @@ -1185,9 +1174,9 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 s= rc, unsigned rb, #define do_store_tl do_store_32 #endif =20 -static ExitStatus do_load(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, - int modify, TCGMemOp mop) +static DisasJumpType do_load(DisasContext *ctx, unsigned rt, unsigned rb, + unsigned rx, int scale, target_long disp, + int modify, TCGMemOp mop) { TCGv dest; =20 @@ -1203,12 +1192,12 @@ static ExitStatus do_load(DisasContext *ctx, unsign= ed rt, unsigned rb, do_load_tl(ctx, dest, rb, rx, scale, disp, modify, mop); save_gpr(ctx, rt, dest); =20 - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, - int modify) +static DisasJumpType do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, + unsigned rx, int scale, target_long disp, + int modify) { TCGv_i32 tmp; =20 @@ -1223,12 +1212,12 @@ static ExitStatus do_floadw(DisasContext *ctx, unsi= gned rt, unsigned rb, gen_helper_loaded_fr0(cpu_env); } =20 - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, - int modify) +static DisasJumpType do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, + unsigned rx, int scale, target_long disp, + int modify) { TCGv_i64 tmp; =20 @@ -1243,20 +1232,20 @@ static ExitStatus do_floadd(DisasContext *ctx, unsi= gned rt, unsigned rb, gen_helper_loaded_fr0(cpu_env); } =20 - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus do_store(DisasContext *ctx, unsigned rt, unsigned rb, - target_long disp, int modify, TCGMemOp mop) +static DisasJumpType do_store(DisasContext *ctx, unsigned rt, unsigned rb, + target_long disp, int modify, TCGMemOp mop) { nullify_over(ctx); do_store_tl(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, modify, mop); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, - int modify) +static DisasJumpType do_fstorew(DisasContext *ctx, unsigned rt, unsigned r= b, + unsigned rx, int scale, target_long disp, + int modify) { TCGv_i32 tmp; =20 @@ -1266,12 +1255,12 @@ static ExitStatus do_fstorew(DisasContext *ctx, uns= igned rt, unsigned rb, do_store_32(ctx, tmp, rb, rx, scale, disp, modify, MO_TEUL); tcg_temp_free_i32(tmp); =20 - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_long disp, - int modify) +static DisasJumpType do_fstored(DisasContext *ctx, unsigned rt, unsigned r= b, + unsigned rx, int scale, target_long disp, + int modify) { TCGv_i64 tmp; =20 @@ -1281,11 +1270,11 @@ static ExitStatus do_fstored(DisasContext *ctx, uns= igned rt, unsigned rb, do_store_64(ctx, tmp, rb, rx, scale, disp, modify, MO_TEQ); tcg_temp_free_i64(tmp); =20 - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus do_fop_wew(DisasContext *ctx, unsigned rt, unsigned ra, - void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) +static DisasJumpType do_fop_wew(DisasContext *ctx, unsigned rt, unsigned r= a, + void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) { TCGv_i32 tmp; =20 @@ -1296,11 +1285,11 @@ static ExitStatus do_fop_wew(DisasContext *ctx, uns= igned rt, unsigned ra, =20 save_frw_i32(rt, tmp); tcg_temp_free_i32(tmp); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus do_fop_wed(DisasContext *ctx, unsigned rt, unsigned ra, - void (*func)(TCGv_i32, TCGv_env, TCGv_i64)) +static DisasJumpType do_fop_wed(DisasContext *ctx, unsigned rt, unsigned r= a, + void (*func)(TCGv_i32, TCGv_env, TCGv_i64)) { TCGv_i32 dst; TCGv_i64 src; @@ -1314,11 +1303,11 @@ static ExitStatus do_fop_wed(DisasContext *ctx, uns= igned rt, unsigned ra, tcg_temp_free_i64(src); save_frw_i32(rt, dst); tcg_temp_free_i32(dst); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus do_fop_ded(DisasContext *ctx, unsigned rt, unsigned ra, - void (*func)(TCGv_i64, TCGv_env, TCGv_i64)) +static DisasJumpType do_fop_ded(DisasContext *ctx, unsigned rt, unsigned r= a, + void (*func)(TCGv_i64, TCGv_env, TCGv_i64)) { TCGv_i64 tmp; =20 @@ -1329,11 +1318,11 @@ static ExitStatus do_fop_ded(DisasContext *ctx, uns= igned rt, unsigned ra, =20 save_frd(rt, tmp); tcg_temp_free_i64(tmp); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus do_fop_dew(DisasContext *ctx, unsigned rt, unsigned ra, - void (*func)(TCGv_i64, TCGv_env, TCGv_i32)) +static DisasJumpType do_fop_dew(DisasContext *ctx, unsigned rt, unsigned r= a, + void (*func)(TCGv_i64, TCGv_env, TCGv_i32)) { TCGv_i32 src; TCGv_i64 dst; @@ -1347,13 +1336,13 @@ static ExitStatus do_fop_dew(DisasContext *ctx, uns= igned rt, unsigned ra, tcg_temp_free_i32(src); save_frd(rt, dst); tcg_temp_free_i64(dst); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus do_fop_weww(DisasContext *ctx, unsigned rt, - unsigned ra, unsigned rb, - void (*func)(TCGv_i32, TCGv_env, - TCGv_i32, TCGv_i32)) +static DisasJumpType do_fop_weww(DisasContext *ctx, unsigned rt, + unsigned ra, unsigned rb, + void (*func)(TCGv_i32, TCGv_env, + TCGv_i32, TCGv_i32)) { TCGv_i32 a, b; =20 @@ -1366,13 +1355,13 @@ static ExitStatus do_fop_weww(DisasContext *ctx, un= signed rt, tcg_temp_free_i32(b); save_frw_i32(rt, a); tcg_temp_free_i32(a); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus do_fop_dedd(DisasContext *ctx, unsigned rt, - unsigned ra, unsigned rb, - void (*func)(TCGv_i64, TCGv_env, - TCGv_i64, TCGv_i64)) +static DisasJumpType do_fop_dedd(DisasContext *ctx, unsigned rt, + unsigned ra, unsigned rb, + void (*func)(TCGv_i64, TCGv_env, + TCGv_i64, TCGv_i64)) { TCGv_i64 a, b; =20 @@ -1385,13 +1374,13 @@ static ExitStatus do_fop_dedd(DisasContext *ctx, un= signed rt, tcg_temp_free_i64(b); save_frd(rt, a); tcg_temp_free_i64(a); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 /* Emit an unconditional branch to a direct target, which may or may not have already had nullification handled. */ -static ExitStatus do_dbranch(DisasContext *ctx, target_ulong dest, - unsigned link, bool is_n) +static DisasJumpType do_dbranch(DisasContext *ctx, target_ulong dest, + unsigned link, bool is_n) { if (ctx->null_cond.c =3D=3D TCG_COND_NEVER && ctx->null_lab =3D=3D NUL= L) { if (link !=3D 0) { @@ -1401,7 +1390,7 @@ static ExitStatus do_dbranch(DisasContext *ctx, targe= t_ulong dest, if (is_n) { ctx->null_cond.c =3D TCG_COND_ALWAYS; } - return NO_EXIT; + return DISAS_NEXT; } else { nullify_over(ctx); =20 @@ -1417,18 +1406,18 @@ static ExitStatus do_dbranch(DisasContext *ctx, tar= get_ulong dest, gen_goto_tb(ctx, 0, ctx->iaoq_b, dest); } =20 - nullify_end(ctx, NO_EXIT); + nullify_end(ctx, DISAS_NEXT); =20 nullify_set(ctx, 0); gen_goto_tb(ctx, 1, ctx->iaoq_b, ctx->iaoq_n); - return EXIT_GOTO_TB; + return DISAS_NORETURN; } } =20 /* Emit a conditional branch to a direct target. If the branch itself is nullified, we should have already used nullify_over. */ -static ExitStatus do_cbranch(DisasContext *ctx, target_long disp, bool is_= n, - DisasCond *cond) +static DisasJumpType do_cbranch(DisasContext *ctx, target_long disp, bool = is_n, + DisasCond *cond) { target_ulong dest =3D iaoq_dest(ctx, disp); TCGLabel *taken =3D NULL; @@ -1480,16 +1469,16 @@ static ExitStatus do_cbranch(DisasContext *ctx, tar= get_long disp, bool is_n, if (ctx->null_lab) { gen_set_label(ctx->null_lab); ctx->null_lab =3D NULL; - return EXIT_IAQ_N_STALE; + return DISAS_IAQ_N_STALE; } else { - return EXIT_GOTO_TB; + return DISAS_NORETURN; } } =20 /* Emit an unconditional branch to an indirect target. This handles nullification of the branch itself. */ -static ExitStatus do_ibranch(DisasContext *ctx, TCGv dest, - unsigned link, bool is_n) +static DisasJumpType do_ibranch(DisasContext *ctx, TCGv dest, + unsigned link, bool is_n) { TCGv a0, a1, next, tmp; TCGCond c; @@ -1528,7 +1517,7 @@ static ExitStatus do_ibranch(DisasContext *ctx, TCGv = dest, tcg_gen_movi_tl(cpu_gr[link], ctx->iaoq_n); } tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } else { cond_prep(&ctx->null_cond); c =3D ctx->null_cond.c; @@ -1560,7 +1549,7 @@ static ExitStatus do_ibranch(DisasContext *ctx, TCGv = dest, } } =20 - return NO_EXIT; + return DISAS_NEXT; } =20 /* On Linux, page zero is normally marked execute only + gateway. @@ -1570,7 +1559,7 @@ static ExitStatus do_ibranch(DisasContext *ctx, TCGv = dest, in than the "be disp(sr2,r0)" instruction that probably sent us here, is the easiest way to handle the branch delay slot on the aforementioned BE. */ -static ExitStatus do_page_zero(DisasContext *ctx) +static DisasJumpType do_page_zero(DisasContext *ctx) { /* If by some means we get here with PSW[N]=3D1, that implies that the B,GATE instruction would be skipped, and we'd fault on the @@ -1598,55 +1587,55 @@ static ExitStatus do_page_zero(DisasContext *ctx) switch (ctx->iaoq_f) { case 0x00: /* Null pointer call */ gen_excp_1(EXCP_SIGSEGV); - return EXIT_NORETURN; + return DISAS_NORETURN; =20 case 0xb0: /* LWS */ gen_excp_1(EXCP_SYSCALL_LWS); - return EXIT_NORETURN; + return DISAS_NORETURN; =20 case 0xe0: /* SET_THREAD_POINTER */ tcg_gen_mov_tl(cpu_cr27, cpu_gr[26]); tcg_gen_mov_tl(cpu_iaoq_f, cpu_gr[31]); tcg_gen_addi_tl(cpu_iaoq_b, cpu_iaoq_f, 4); - return EXIT_IAQ_N_UPDATED; + return DISAS_IAQ_N_UPDATED; =20 case 0x100: /* SYSCALL */ gen_excp_1(EXCP_SYSCALL); - return EXIT_NORETURN; + return DISAS_NORETURN; =20 default: do_sigill: gen_excp_1(EXCP_SIGILL); - return EXIT_NORETURN; + return DISAS_NORETURN; } } =20 -static ExitStatus trans_nop(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_nop(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus trans_break(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_break(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { nullify_over(ctx); return nullify_end(ctx, gen_excp(ctx, EXCP_DEBUG)); } =20 -static ExitStatus trans_sync(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_sync(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { /* No point in nullifying the memory barrier. */ tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); =20 cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus trans_mfia(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_mfia(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); TCGv tmp =3D dest_gpr(ctx, rt); @@ -1654,11 +1643,11 @@ static ExitStatus trans_mfia(DisasContext *ctx, uin= t32_t insn, save_gpr(ctx, rt, tmp); =20 cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus trans_mfsp(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_mfsp(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); TCGv tmp =3D dest_gpr(ctx, rt); @@ -1668,11 +1657,11 @@ static ExitStatus trans_mfsp(DisasContext *ctx, uin= t32_t insn, save_gpr(ctx, rt, tmp); =20 cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus trans_mfctl(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_mfctl(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned ctl =3D extract32(insn, 21, 5); @@ -1708,11 +1697,11 @@ static ExitStatus trans_mfctl(DisasContext *ctx, ui= nt32_t insn, } =20 cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus trans_mtctl(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_mtctl(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rin =3D extract32(insn, 16, 5); unsigned ctl =3D extract32(insn, 21, 5); @@ -1729,11 +1718,11 @@ static ExitStatus trans_mtctl(DisasContext *ctx, ui= nt32_t insn, } =20 cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus trans_mtsarcm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_mtsarcm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rin =3D extract32(insn, 16, 5); TCGv tmp =3D tcg_temp_new(); @@ -1744,11 +1733,11 @@ static ExitStatus trans_mtsarcm(DisasContext *ctx, = uint32_t insn, tcg_temp_free(tmp); =20 cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus trans_ldsid(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ldsid(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); TCGv dest =3D dest_gpr(ctx, rt); @@ -1758,7 +1747,7 @@ static ExitStatus trans_ldsid(DisasContext *ctx, uint= 32_t insn, save_gpr(ctx, rt, dest); =20 cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } =20 static const DisasInsn table_system[] =3D { @@ -1774,8 +1763,8 @@ static const DisasInsn table_system[] =3D { { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, }; =20 -static ExitStatus trans_base_idx_mod(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_base_idx_mod(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rb =3D extract32(insn, 21, 5); unsigned rx =3D extract32(insn, 16, 5); @@ -1788,11 +1777,11 @@ static ExitStatus trans_base_idx_mod(DisasContext *= ctx, uint32_t insn, save_gpr(ctx, rb, dest); =20 cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus trans_probe(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_probe(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned rb =3D extract32(insn, 21, 5); @@ -1809,7 +1798,7 @@ static ExitStatus trans_probe(DisasContext *ctx, uint= 32_t insn, gen_helper_probe_r(dest, load_gpr(ctx, rb)); } save_gpr(ctx, rt, dest); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 static const DisasInsn table_mem_mgmt[] =3D { @@ -1830,8 +1819,8 @@ static const DisasInsn table_mem_mgmt[] =3D { { 0x04003180u, 0xfc003fa0u, trans_probe }, /* probei */ }; =20 -static ExitStatus trans_add(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_add(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 =3D extract32(insn, 21, 5); unsigned r1 =3D extract32(insn, 16, 5); @@ -1844,7 +1833,7 @@ static ExitStatus trans_add(DisasContext *ctx, uint32= _t insn, bool is_l =3D false; bool is_tc =3D false; bool is_tsv =3D false; - ExitStatus ret; + DisasJumpType ret; =20 switch (ext) { case 0x6: /* ADD, SHLADD */ @@ -1874,8 +1863,8 @@ static ExitStatus trans_add(DisasContext *ctx, uint32= _t insn, return nullify_end(ctx, ret); } =20 -static ExitStatus trans_sub(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_sub(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 =3D extract32(insn, 21, 5); unsigned r1 =3D extract32(insn, 16, 5); @@ -1886,7 +1875,7 @@ static ExitStatus trans_sub(DisasContext *ctx, uint32= _t insn, bool is_b =3D false; bool is_tc =3D false; bool is_tsv =3D false; - ExitStatus ret; + DisasJumpType ret; =20 switch (ext) { case 0x10: /* SUB */ @@ -1919,15 +1908,15 @@ static ExitStatus trans_sub(DisasContext *ctx, uint= 32_t insn, return nullify_end(ctx, ret); } =20 -static ExitStatus trans_log(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_log(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 =3D extract32(insn, 21, 5); unsigned r1 =3D extract32(insn, 16, 5); unsigned cf =3D extract32(insn, 12, 4); unsigned rt =3D extract32(insn, 0, 5); TCGv tcg_r1, tcg_r2; - ExitStatus ret; + DisasJumpType ret; =20 if (cf) { nullify_over(ctx); @@ -1939,8 +1928,8 @@ static ExitStatus trans_log(DisasContext *ctx, uint32= _t insn, } =20 /* OR r,0,t -> COPY (according to gas) */ -static ExitStatus trans_copy(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_copy(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r1 =3D extract32(insn, 16, 5); unsigned rt =3D extract32(insn, 0, 5); @@ -1953,18 +1942,18 @@ static ExitStatus trans_copy(DisasContext *ctx, uin= t32_t insn, save_gpr(ctx, rt, cpu_gr[r1]); } cond_free(&ctx->null_cond); - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus trans_cmpclr(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_cmpclr(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 =3D extract32(insn, 21, 5); unsigned r1 =3D extract32(insn, 16, 5); unsigned cf =3D extract32(insn, 12, 4); unsigned rt =3D extract32(insn, 0, 5); TCGv tcg_r1, tcg_r2; - ExitStatus ret; + DisasJumpType ret; =20 if (cf) { nullify_over(ctx); @@ -1975,15 +1964,15 @@ static ExitStatus trans_cmpclr(DisasContext *ctx, u= int32_t insn, return nullify_end(ctx, ret); } =20 -static ExitStatus trans_uxor(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_uxor(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 =3D extract32(insn, 21, 5); unsigned r1 =3D extract32(insn, 16, 5); unsigned cf =3D extract32(insn, 12, 4); unsigned rt =3D extract32(insn, 0, 5); TCGv tcg_r1, tcg_r2; - ExitStatus ret; + DisasJumpType ret; =20 if (cf) { nullify_over(ctx); @@ -1994,8 +1983,8 @@ static ExitStatus trans_uxor(DisasContext *ctx, uint3= 2_t insn, return nullify_end(ctx, ret); } =20 -static ExitStatus trans_uaddcm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_uaddcm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 =3D extract32(insn, 21, 5); unsigned r1 =3D extract32(insn, 16, 5); @@ -2003,7 +1992,7 @@ static ExitStatus trans_uaddcm(DisasContext *ctx, uin= t32_t insn, unsigned is_tc =3D extract32(insn, 6, 1); unsigned rt =3D extract32(insn, 0, 5); TCGv tcg_r1, tcg_r2, tmp; - ExitStatus ret; + DisasJumpType ret; =20 if (cf) { nullify_over(ctx); @@ -2016,15 +2005,15 @@ static ExitStatus trans_uaddcm(DisasContext *ctx, u= int32_t insn, return nullify_end(ctx, ret); } =20 -static ExitStatus trans_dcor(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_dcor(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 =3D extract32(insn, 21, 5); unsigned cf =3D extract32(insn, 12, 4); unsigned is_i =3D extract32(insn, 6, 1); unsigned rt =3D extract32(insn, 0, 5); TCGv tmp; - ExitStatus ret; + DisasJumpType ret; =20 nullify_over(ctx); =20 @@ -2041,8 +2030,8 @@ static ExitStatus trans_dcor(DisasContext *ctx, uint3= 2_t insn, return nullify_end(ctx, ret); } =20 -static ExitStatus trans_ds(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned r2 =3D extract32(insn, 21, 5); unsigned r1 =3D extract32(insn, 16, 5); @@ -2105,7 +2094,7 @@ static ExitStatus trans_ds(DisasContext *ctx, uint32_= t insn, tcg_temp_free(add2); tcg_temp_free(dest); =20 - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 static const DisasInsn table_arith_log[] =3D { @@ -2126,7 +2115,7 @@ static const DisasInsn table_arith_log[] =3D { { 0x08000200u, 0xfc000320u, trans_add }, /* shladd */ }; =20 -static ExitStatus trans_addi(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_addi(DisasContext *ctx, uint32_t insn) { target_long im =3D low_sextract(insn, 0, 11); unsigned e1 =3D extract32(insn, 11, 1); @@ -2135,7 +2124,7 @@ static ExitStatus trans_addi(DisasContext *ctx, uint3= 2_t insn) unsigned r2 =3D extract32(insn, 21, 5); unsigned o1 =3D extract32(insn, 26, 1); TCGv tcg_im, tcg_r2; - ExitStatus ret; + DisasJumpType ret; =20 if (cf) { nullify_over(ctx); @@ -2148,7 +2137,7 @@ static ExitStatus trans_addi(DisasContext *ctx, uint3= 2_t insn) return nullify_end(ctx, ret); } =20 -static ExitStatus trans_subi(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_subi(DisasContext *ctx, uint32_t insn) { target_long im =3D low_sextract(insn, 0, 11); unsigned e1 =3D extract32(insn, 11, 1); @@ -2156,7 +2145,7 @@ static ExitStatus trans_subi(DisasContext *ctx, uint3= 2_t insn) unsigned rt =3D extract32(insn, 16, 5); unsigned r2 =3D extract32(insn, 21, 5); TCGv tcg_im, tcg_r2; - ExitStatus ret; + DisasJumpType ret; =20 if (cf) { nullify_over(ctx); @@ -2169,14 +2158,14 @@ static ExitStatus trans_subi(DisasContext *ctx, uin= t32_t insn) return nullify_end(ctx, ret); } =20 -static ExitStatus trans_cmpiclr(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_cmpiclr(DisasContext *ctx, uint32_t insn) { target_long im =3D low_sextract(insn, 0, 11); unsigned cf =3D extract32(insn, 12, 4); unsigned rt =3D extract32(insn, 16, 5); unsigned r2 =3D extract32(insn, 21, 5); TCGv tcg_im, tcg_r2; - ExitStatus ret; + DisasJumpType ret; =20 if (cf) { nullify_over(ctx); @@ -2189,8 +2178,8 @@ static ExitStatus trans_cmpiclr(DisasContext *ctx, ui= nt32_t insn) return nullify_end(ctx, ret); } =20 -static ExitStatus trans_ld_idx_i(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ld_idx_i(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned m =3D extract32(insn, 5, 1); @@ -2204,8 +2193,8 @@ static ExitStatus trans_ld_idx_i(DisasContext *ctx, u= int32_t insn, return do_load(ctx, rt, rb, 0, 0, disp, modify, mop); } =20 -static ExitStatus trans_ld_idx_x(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ld_idx_x(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned m =3D extract32(insn, 5, 1); @@ -2218,8 +2207,8 @@ static ExitStatus trans_ld_idx_x(DisasContext *ctx, u= int32_t insn, return do_load(ctx, rt, rb, rx, u ? sz : 0, 0, m, mop); } =20 -static ExitStatus trans_st_idx_i(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_st_idx_i(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { int disp =3D low_sextract(insn, 0, 5); unsigned m =3D extract32(insn, 5, 1); @@ -2233,8 +2222,8 @@ static ExitStatus trans_st_idx_i(DisasContext *ctx, u= int32_t insn, return do_store(ctx, rr, rb, disp, modify, mop); } =20 -static ExitStatus trans_ldcw(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ldcw(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned m =3D extract32(insn, 5, 1); @@ -2285,11 +2274,11 @@ static ExitStatus trans_ldcw(DisasContext *ctx, uin= t32_t insn, } save_gpr(ctx, rt, dest); =20 - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus trans_stby(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_stby(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { target_long disp =3D low_sextract(insn, 0, 5); unsigned m =3D extract32(insn, 5, 1); @@ -2321,7 +2310,7 @@ static ExitStatus trans_stby(DisasContext *ctx, uint3= 2_t insn, } tcg_temp_free(addr); =20 - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 static const DisasInsn table_index_mem[] =3D { @@ -2332,7 +2321,7 @@ static const DisasInsn table_index_mem[] =3D { { 0x0c001300u, 0xfc0013c0, trans_stby }, }; =20 -static ExitStatus trans_ldil(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_ldil(DisasContext *ctx, uint32_t insn) { unsigned rt =3D extract32(insn, 21, 5); target_long i =3D assemble_21(insn); @@ -2342,10 +2331,10 @@ static ExitStatus trans_ldil(DisasContext *ctx, uin= t32_t insn) save_gpr(ctx, rt, tcg_rt); cond_free(&ctx->null_cond); =20 - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus trans_addil(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_addil(DisasContext *ctx, uint32_t insn) { unsigned rt =3D extract32(insn, 21, 5); target_long i =3D assemble_21(insn); @@ -2356,10 +2345,10 @@ static ExitStatus trans_addil(DisasContext *ctx, ui= nt32_t insn) save_gpr(ctx, 1, tcg_r1); cond_free(&ctx->null_cond); =20 - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus trans_ldo(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_ldo(DisasContext *ctx, uint32_t insn) { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); @@ -2376,11 +2365,11 @@ static ExitStatus trans_ldo(DisasContext *ctx, uint= 32_t insn) save_gpr(ctx, rt, tcg_rt); cond_free(&ctx->null_cond); =20 - return NO_EXIT; + return DISAS_NEXT; } =20 -static ExitStatus trans_load(DisasContext *ctx, uint32_t insn, - bool is_mod, TCGMemOp mop) +static DisasJumpType trans_load(DisasContext *ctx, uint32_t insn, + bool is_mod, TCGMemOp mop) { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); @@ -2389,7 +2378,7 @@ static ExitStatus trans_load(DisasContext *ctx, uint3= 2_t insn, return do_load(ctx, rt, rb, 0, 0, i, is_mod ? (i < 0 ? -1 : 1) : 0, mo= p); } =20 -static ExitStatus trans_load_w(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_load_w(DisasContext *ctx, uint32_t insn) { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); @@ -2410,7 +2399,7 @@ static ExitStatus trans_load_w(DisasContext *ctx, uin= t32_t insn) } } =20 -static ExitStatus trans_fload_mod(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_fload_mod(DisasContext *ctx, uint32_t insn) { target_long i =3D assemble_16a(insn); unsigned t1 =3D extract32(insn, 1, 1); @@ -2422,8 +2411,8 @@ static ExitStatus trans_fload_mod(DisasContext *ctx, = uint32_t insn) return do_floadw(ctx, t1 * 32 + t0, rb, 0, 0, i, (a ? -1 : 1)); } =20 -static ExitStatus trans_store(DisasContext *ctx, uint32_t insn, - bool is_mod, TCGMemOp mop) +static DisasJumpType trans_store(DisasContext *ctx, uint32_t insn, + bool is_mod, TCGMemOp mop) { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); @@ -2432,7 +2421,7 @@ static ExitStatus trans_store(DisasContext *ctx, uint= 32_t insn, return do_store(ctx, rt, rb, i, is_mod ? (i < 0 ? -1 : 1) : 0, mop); } =20 -static ExitStatus trans_store_w(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_store_w(DisasContext *ctx, uint32_t insn) { unsigned rb =3D extract32(insn, 21, 5); unsigned rt =3D extract32(insn, 16, 5); @@ -2452,7 +2441,7 @@ static ExitStatus trans_store_w(DisasContext *ctx, ui= nt32_t insn) } } =20 -static ExitStatus trans_fstore_mod(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_fstore_mod(DisasContext *ctx, uint32_t insn) { target_long i =3D assemble_16a(insn); unsigned t1 =3D extract32(insn, 1, 1); @@ -2464,7 +2453,7 @@ static ExitStatus trans_fstore_mod(DisasContext *ctx,= uint32_t insn) return do_fstorew(ctx, t1 * 32 + t0, rb, 0, 0, i, (a ? -1 : 1)); } =20 -static ExitStatus trans_copr_w(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_copr_w(DisasContext *ctx, uint32_t insn) { unsigned t0 =3D extract32(insn, 0, 5); unsigned m =3D extract32(insn, 5, 1); @@ -2499,7 +2488,7 @@ static ExitStatus trans_copr_w(DisasContext *ctx, uin= t32_t insn) return gen_illegal(ctx); } =20 -static ExitStatus trans_copr_dw(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_copr_dw(DisasContext *ctx, uint32_t insn) { unsigned rt =3D extract32(insn, 0, 5); unsigned m =3D extract32(insn, 5, 1); @@ -2533,8 +2522,8 @@ static ExitStatus trans_copr_dw(DisasContext *ctx, ui= nt32_t insn) } } =20 -static ExitStatus trans_cmpb(DisasContext *ctx, uint32_t insn, - bool is_true, bool is_imm, bool is_dw) +static DisasJumpType trans_cmpb(DisasContext *ctx, uint32_t insn, + bool is_true, bool is_imm, bool is_dw) { target_long disp =3D assemble_12(insn) * 4; unsigned n =3D extract32(insn, 1, 1); @@ -2565,8 +2554,8 @@ static ExitStatus trans_cmpb(DisasContext *ctx, uint3= 2_t insn, return do_cbranch(ctx, disp, n, &cond); } =20 -static ExitStatus trans_addb(DisasContext *ctx, uint32_t insn, - bool is_true, bool is_imm) +static DisasJumpType trans_addb(DisasContext *ctx, uint32_t insn, + bool is_true, bool is_imm) { target_long disp =3D assemble_12(insn) * 4; unsigned n =3D extract32(insn, 1, 1); @@ -2607,7 +2596,7 @@ static ExitStatus trans_addb(DisasContext *ctx, uint3= 2_t insn, return do_cbranch(ctx, disp, n, &cond); } =20 -static ExitStatus trans_bb(DisasContext *ctx, uint32_t insn) +static DisasJumpType trans_bb(DisasContext *ctx, uint32_t insn) { target_long disp =3D assemble_12(insn) * 4; unsigned n =3D extract32(insn, 1, 1); @@ -2633,7 +2622,7 @@ static ExitStatus trans_bb(DisasContext *ctx, uint32_= t insn) return do_cbranch(ctx, disp, n, &cond); } =20 -static ExitStatus trans_movb(DisasContext *ctx, uint32_t insn, bool is_imm) +static DisasJumpType trans_movb(DisasContext *ctx, uint32_t insn, bool is_= imm) { target_long disp =3D assemble_12(insn) * 4; unsigned n =3D extract32(insn, 1, 1); @@ -2658,8 +2647,8 @@ static ExitStatus trans_movb(DisasContext *ctx, uint3= 2_t insn, bool is_imm) return do_cbranch(ctx, disp, n, &cond); } =20 -static ExitStatus trans_shrpw_sar(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_shrpw_sar(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned c =3D extract32(insn, 13, 3); @@ -2700,11 +2689,11 @@ static ExitStatus trans_shrpw_sar(DisasContext *ctx= , uint32_t insn, if (c) { ctx->null_cond =3D do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus trans_shrpw_imm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_shrpw_imm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned cpos =3D extract32(insn, 5, 5); @@ -2741,11 +2730,11 @@ static ExitStatus trans_shrpw_imm(DisasContext *ctx= , uint32_t insn, if (c) { ctx->null_cond =3D do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus trans_extrw_sar(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_extrw_sar(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned clen =3D extract32(insn, 0, 5); unsigned is_se =3D extract32(insn, 10, 1); @@ -2780,11 +2769,11 @@ static ExitStatus trans_extrw_sar(DisasContext *ctx= , uint32_t insn, if (c) { ctx->null_cond =3D do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus trans_extrw_imm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_extrw_imm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned clen =3D extract32(insn, 0, 5); unsigned pos =3D extract32(insn, 5, 5); @@ -2814,7 +2803,7 @@ static ExitStatus trans_extrw_imm(DisasContext *ctx, = uint32_t insn, if (c) { ctx->null_cond =3D do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 static const DisasInsn table_sh_ex[] =3D { @@ -2824,8 +2813,8 @@ static const DisasInsn table_sh_ex[] =3D { { 0xd0001800u, 0xfc001800u, trans_extrw_imm }, }; =20 -static ExitStatus trans_depw_imm_c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_depw_imm_c(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned clen =3D extract32(insn, 0, 5); unsigned cpos =3D extract32(insn, 5, 5); @@ -2865,11 +2854,11 @@ static ExitStatus trans_depw_imm_c(DisasContext *ct= x, uint32_t insn, if (c) { ctx->null_cond =3D do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus trans_depw_imm(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_depw_imm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned clen =3D extract32(insn, 0, 5); unsigned cpos =3D extract32(insn, 5, 5); @@ -2902,11 +2891,11 @@ static ExitStatus trans_depw_imm(DisasContext *ctx,= uint32_t insn, if (c) { ctx->null_cond =3D do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus trans_depw_sar(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_depw_sar(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned clen =3D extract32(insn, 0, 5); unsigned nz =3D extract32(insn, 10, 1); @@ -2954,7 +2943,7 @@ static ExitStatus trans_depw_sar(DisasContext *ctx, u= int32_t insn, if (c) { ctx->null_cond =3D do_sed_cond(c, dest); } - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 static const DisasInsn table_depw[] =3D { @@ -2963,7 +2952,7 @@ static const DisasInsn table_depw[] =3D { { 0xd4001800u, 0xfc001800u, trans_depw_imm_c }, }; =20 -static ExitStatus trans_be(DisasContext *ctx, uint32_t insn, bool is_l) +static DisasJumpType trans_be(DisasContext *ctx, uint32_t insn, bool is_l) { unsigned n =3D extract32(insn, 1, 1); unsigned b =3D extract32(insn, 21, 5); @@ -2988,8 +2977,8 @@ static ExitStatus trans_be(DisasContext *ctx, uint32_= t insn, bool is_l) } } =20 -static ExitStatus trans_bl(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_bl(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned n =3D extract32(insn, 1, 1); unsigned link =3D extract32(insn, 21, 5); @@ -2998,8 +2987,8 @@ static ExitStatus trans_bl(DisasContext *ctx, uint32_= t insn, return do_dbranch(ctx, iaoq_dest(ctx, disp), link, n); } =20 -static ExitStatus trans_bl_long(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_bl_long(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned n =3D extract32(insn, 1, 1); target_long disp =3D assemble_22(insn); @@ -3007,8 +2996,8 @@ static ExitStatus trans_bl_long(DisasContext *ctx, ui= nt32_t insn, return do_dbranch(ctx, iaoq_dest(ctx, disp), 2, n); } =20 -static ExitStatus trans_blr(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_blr(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned n =3D extract32(insn, 1, 1); unsigned rx =3D extract32(insn, 16, 5); @@ -3020,8 +3009,8 @@ static ExitStatus trans_blr(DisasContext *ctx, uint32= _t insn, return do_ibranch(ctx, tmp, link, n); } =20 -static ExitStatus trans_bv(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_bv(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned n =3D extract32(insn, 1, 1); unsigned rx =3D extract32(insn, 16, 5); @@ -3038,8 +3027,8 @@ static ExitStatus trans_bv(DisasContext *ctx, uint32_= t insn, return do_ibranch(ctx, dest, 0, n); } =20 -static ExitStatus trans_bve(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_bve(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned n =3D extract32(insn, 1, 1); unsigned rb =3D extract32(insn, 21, 5); @@ -3056,64 +3045,64 @@ static const DisasInsn table_branch[] =3D { { 0xe800d000u, 0xfc00dffcu, trans_bve }, }; =20 -static ExitStatus trans_fop_wew_0c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_wew_0c(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned ra =3D extract32(insn, 21, 5); return do_fop_wew(ctx, rt, ra, di->f.wew); } =20 -static ExitStatus trans_fop_wew_0e(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_wew_0e(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D assemble_rt64(insn); unsigned ra =3D assemble_ra64(insn); return do_fop_wew(ctx, rt, ra, di->f.wew); } =20 -static ExitStatus trans_fop_ded(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_ded(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned ra =3D extract32(insn, 21, 5); return do_fop_ded(ctx, rt, ra, di->f.ded); } =20 -static ExitStatus trans_fop_wed_0c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_wed_0c(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned ra =3D extract32(insn, 21, 5); return do_fop_wed(ctx, rt, ra, di->f.wed); } =20 -static ExitStatus trans_fop_wed_0e(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_wed_0e(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D assemble_rt64(insn); unsigned ra =3D extract32(insn, 21, 5); return do_fop_wed(ctx, rt, ra, di->f.wed); } =20 -static ExitStatus trans_fop_dew_0c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_dew_0c(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned ra =3D extract32(insn, 21, 5); return do_fop_dew(ctx, rt, ra, di->f.dew); } =20 -static ExitStatus trans_fop_dew_0e(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_dew_0e(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned ra =3D assemble_ra64(insn); return do_fop_dew(ctx, rt, ra, di->f.dew); } =20 -static ExitStatus trans_fop_weww_0c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_weww_0c(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned rb =3D extract32(insn, 16, 5); @@ -3121,8 +3110,8 @@ static ExitStatus trans_fop_weww_0c(DisasContext *ctx= , uint32_t insn, return do_fop_weww(ctx, rt, ra, rb, di->f.weww); } =20 -static ExitStatus trans_fop_weww_0e(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_weww_0e(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D assemble_rt64(insn); unsigned rb =3D assemble_rb64(insn); @@ -3130,8 +3119,8 @@ static ExitStatus trans_fop_weww_0e(DisasContext *ctx= , uint32_t insn, return do_fop_weww(ctx, rt, ra, rb, di->f.weww); } =20 -static ExitStatus trans_fop_dedd(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fop_dedd(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned rb =3D extract32(insn, 16, 5); @@ -3179,8 +3168,8 @@ static void gen_fnegabs_d(TCGv_i64 dst, TCGv_env unus= ed, TCGv_i64 src) tcg_gen_ori_i64(dst, src, INT64_MIN); } =20 -static ExitStatus do_fcmp_s(DisasContext *ctx, unsigned ra, unsigned rb, - unsigned y, unsigned c) +static DisasJumpType do_fcmp_s(DisasContext *ctx, unsigned ra, unsigned rb, + unsigned y, unsigned c) { TCGv_i32 ta, tb, tc, ty; =20 @@ -3198,11 +3187,11 @@ static ExitStatus do_fcmp_s(DisasContext *ctx, unsi= gned ra, unsigned rb, tcg_temp_free_i32(ty); tcg_temp_free_i32(tc); =20 - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus trans_fcmp_s_0c(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fcmp_s_0c(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned c =3D extract32(insn, 0, 5); unsigned y =3D extract32(insn, 13, 3); @@ -3211,8 +3200,8 @@ static ExitStatus trans_fcmp_s_0c(DisasContext *ctx, = uint32_t insn, return do_fcmp_s(ctx, ra, rb, y, c); } =20 -static ExitStatus trans_fcmp_s_0e(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fcmp_s_0e(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned c =3D extract32(insn, 0, 5); unsigned y =3D extract32(insn, 13, 3); @@ -3221,8 +3210,8 @@ static ExitStatus trans_fcmp_s_0e(DisasContext *ctx, = uint32_t insn, return do_fcmp_s(ctx, ra, rb, y, c); } =20 -static ExitStatus trans_fcmp_d(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fcmp_d(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned c =3D extract32(insn, 0, 5); unsigned y =3D extract32(insn, 13, 3); @@ -3245,11 +3234,11 @@ static ExitStatus trans_fcmp_d(DisasContext *ctx, u= int32_t insn, tcg_temp_free_i32(ty); tcg_temp_free_i32(tc); =20 - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus trans_ftest_t(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ftest_t(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned y =3D extract32(insn, 13, 3); unsigned cbit =3D (y ^ 1) - 1; @@ -3263,11 +3252,11 @@ static ExitStatus trans_ftest_t(DisasContext *ctx, = uint32_t insn, ctx->null_cond =3D cond_make_0(TCG_COND_NE, t); tcg_temp_free(t); =20 - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus trans_ftest_q(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_ftest_q(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned c =3D extract32(insn, 0, 5); int mask; @@ -3317,11 +3306,11 @@ static ExitStatus trans_ftest_q(DisasContext *ctx, = uint32_t insn, ctx->null_cond =3D cond_make_0(TCG_COND_EQ, t); } done: - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus trans_xmpyu(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_xmpyu(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned rb =3D assemble_rb64(insn); @@ -3337,7 +3326,7 @@ static ExitStatus trans_xmpyu(DisasContext *ctx, uint= 32_t insn, tcg_temp_free_i64(a); tcg_temp_free_i64(b); =20 - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 #define FOP_DED trans_fop_ded, .f.ded @@ -3512,7 +3501,8 @@ static inline int fmpyadd_s_reg(unsigned r) return (r & 16) * 2 + 16 + (r & 15); } =20 -static ExitStatus trans_fmpyadd(DisasContext *ctx, uint32_t insn, bool is_= sub) +static DisasJumpType trans_fmpyadd(DisasContext *ctx, + uint32_t insn, bool is_sub) { unsigned tm =3D extract32(insn, 0, 5); unsigned f =3D extract32(insn, 5, 1); @@ -3540,11 +3530,11 @@ static ExitStatus trans_fmpyadd(DisasContext *ctx, = uint32_t insn, bool is_sub) is_sub ? gen_helper_fsub_d : gen_helper_fadd_d); } =20 - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus trans_fmpyfadd_s(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fmpyfadd_s(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D assemble_rt64(insn); unsigned neg =3D extract32(insn, 5, 1); @@ -3568,11 +3558,11 @@ static ExitStatus trans_fmpyfadd_s(DisasContext *ct= x, uint32_t insn, tcg_temp_free_i32(c); save_frw_i32(rt, a); tcg_temp_free_i32(a); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 -static ExitStatus trans_fmpyfadd_d(DisasContext *ctx, uint32_t insn, - const DisasInsn *di) +static DisasJumpType trans_fmpyfadd_d(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) { unsigned rt =3D extract32(insn, 0, 5); unsigned neg =3D extract32(insn, 5, 1); @@ -3596,7 +3586,7 @@ static ExitStatus trans_fmpyfadd_d(DisasContext *ctx,= uint32_t insn, tcg_temp_free_i64(c); save_frd(rt, a); tcg_temp_free_i64(a); - return nullify_end(ctx, NO_EXIT); + return nullify_end(ctx, DISAS_NEXT); } =20 static const DisasInsn table_fp_fused[] =3D { @@ -3604,8 +3594,8 @@ static const DisasInsn table_fp_fused[] =3D { { 0xb8000800u, 0xfc0019c0u, trans_fmpyfadd_d } }; =20 -static ExitStatus translate_table_int(DisasContext *ctx, uint32_t insn, - const DisasInsn table[], size_t n) +static DisasJumpType translate_table_int(DisasContext *ctx, uint32_t insn, + const DisasInsn table[], size_t n) { size_t i; for (i =3D 0; i < n; ++i) { @@ -3619,7 +3609,7 @@ static ExitStatus translate_table_int(DisasContext *c= tx, uint32_t insn, #define translate_table(ctx, insn, table) \ translate_table_int(ctx, insn, table, ARRAY_SIZE(table)) =20 -static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) +static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) { uint32_t opc =3D extract32(insn, 26, 6); =20 @@ -3744,7 +3734,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) { CPUHPPAState *env =3D cs->env_ptr; DisasContext ctx; - ExitStatus ret; + DisasJumpType ret; int num_insns, max_insns, i; =20 ctx.tb =3D tb; @@ -3797,7 +3787,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) =20 if (ctx.iaoq_f < TARGET_PAGE_SIZE) { ret =3D do_page_zero(&ctx); - assert(ret !=3D NO_EXIT); + assert(ret !=3D DISAS_NEXT); } else { /* Always fetch the insn, even if nullified, so that we check the page permissions for execute. */ @@ -3816,7 +3806,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) =20 if (unlikely(ctx.null_cond.c =3D=3D TCG_COND_ALWAYS)) { ctx.null_cond.c =3D TCG_COND_NEVER; - ret =3D NO_EXIT; + ret =3D DISAS_NEXT; } else { ret =3D translate_one(&ctx, insn); assert(ctx.null_lab =3D=3D NULL); @@ -3834,7 +3824,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) /* ??? The non-linear instruction restriction is purely due to the debugging dump. Otherwise we *could* follow unconditional branches within the same page. */ - if (ret =3D=3D NO_EXIT + if (ret =3D=3D DISAS_NEXT && (ctx.iaoq_b !=3D ctx.iaoq_f + 4 || num_insns >=3D max_insns || tcg_op_buf_full())) { @@ -3842,45 +3832,42 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) || ctx.null_cond.c =3D=3D TCG_COND_ALWAYS) { nullify_set(&ctx, ctx.null_cond.c =3D=3D TCG_COND_ALWAYS); gen_goto_tb(&ctx, 0, ctx.iaoq_b, ctx.iaoq_n); - ret =3D EXIT_GOTO_TB; + ret =3D DISAS_NORETURN; } else { - ret =3D EXIT_IAQ_N_STALE; + ret =3D DISAS_IAQ_N_STALE; } } =20 ctx.iaoq_f =3D ctx.iaoq_b; ctx.iaoq_b =3D ctx.iaoq_n; - if (ret =3D=3D EXIT_NORETURN - || ret =3D=3D EXIT_GOTO_TB - || ret =3D=3D EXIT_IAQ_N_UPDATED) { + if (ret =3D=3D DISAS_NORETURN || ret =3D=3D DISAS_IAQ_N_UPDATED) { break; } if (ctx.iaoq_f =3D=3D -1) { tcg_gen_mov_tl(cpu_iaoq_f, cpu_iaoq_b); copy_iaoq_entry(cpu_iaoq_b, ctx.iaoq_n, ctx.iaoq_n_var); nullify_save(&ctx); - ret =3D EXIT_IAQ_N_UPDATED; + ret =3D DISAS_IAQ_N_UPDATED; break; } if (ctx.iaoq_b =3D=3D -1) { tcg_gen_mov_tl(cpu_iaoq_b, ctx.iaoq_n_var); } - } while (ret =3D=3D NO_EXIT); + } while (ret =3D=3D DISAS_NEXT); =20 if (tb->cflags & CF_LAST_IO) { gen_io_end(); } =20 switch (ret) { - case EXIT_GOTO_TB: - case EXIT_NORETURN: + case DISAS_NORETURN: break; - case EXIT_IAQ_N_STALE: + case DISAS_IAQ_N_STALE: copy_iaoq_entry(cpu_iaoq_f, ctx.iaoq_f, cpu_iaoq_f); copy_iaoq_entry(cpu_iaoq_b, ctx.iaoq_b, cpu_iaoq_b); nullify_save(&ctx); /* FALLTHRU */ - case EXIT_IAQ_N_UPDATED: + case DISAS_IAQ_N_UPDATED: if (ctx.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { --=20 2.13.5 From nobody Mon Apr 29 07:37:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504809999881381.635105110238; Thu, 7 Sep 2017 11:46:39 -0700 (PDT) Received: from localhost ([::1]:41744 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1p0-0005TV-Le for importer@patchew.org; Thu, 07 Sep 2017 14:46:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51194) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1nN-0004Wl-LX for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:45:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dq1nJ-0005YQ-0i for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:44:57 -0400 Received: from mail-pf0-x22f.google.com ([2607:f8b0:400e:c00::22f]:34429) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dq1nI-0005YC-R4 for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:44:52 -0400 Received: by mail-pf0-x22f.google.com with SMTP id e1so822675pfk.1 for ; Thu, 07 Sep 2017 11:44:52 -0700 (PDT) Received: from pike.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id r68sm464247pfi.7.2017.09.07.11.44.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 11:44:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JZA6b13ZN6Z7JezGfssdXb53V7vRGi8yWYPs687OK2M=; b=YNhw0Hlx/zGkc5Iv0ecJwlw7C+hn5E4P6IAELdxkDj47R212UjaRzMaDlk1sn9zWI/ MVEaqesRueLOgl9/5BEfK2vIqIILVuBNN+Vx1BdlMmkUxOwXn7R89gE9dFERxYTRT3PF +MR0Sb3XNcyBldb0YoaOyHh/AG3r6q/8DN/Jw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JZA6b13ZN6Z7JezGfssdXb53V7vRGi8yWYPs687OK2M=; b=eakvVb0qCbQ0hilXAJRa2HR15Cyk9zbp3O/kUZfdKkG1czBR7r18YdPmEeRYAChSgd Q9zt4x3PjWF9vK1Cqq98cI/PtNCvnWnahRSgROnKkh5NWeYidGKGcS49PamzIA1ZmEBu jPmPzioOJQy4EOmikYFBvoCa037UmjnJz0YX2emfhCtv97OyyZ1HNfhThxsNqlTE50vb qOdcfXsjX0BCCgcr7Trc1uB3miXLSQXryla4p9U4N/m/KZVzvNDIYr5rkEri8/GuarBG Vyd8T69jJw4uuA9VbwB88MnTpD3wxRBzQW76jDMJz3UHKZnHOlfnqjKrLRLBTjXW3u61 JaqA== X-Gm-Message-State: AHPjjUhFeu4/FgaZBMhUf72d04isNZL1U7RKD0KgGeGyVwXvSKC/aAtA aell46JMxl9qCtHzvAaQCA== X-Google-Smtp-Source: ADKCNb6dBU+vgsRhj6pF2E/+ERrSnQwdgRxby8dYjtKnqSjOmks/z0HdMln6Ydxc8Q/VYzW8esk4jw== X-Received: by 10.98.20.19 with SMTP id 19mr301157pfu.167.1504809891530; Thu, 07 Sep 2017 11:44:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 11:44:46 -0700 Message-Id: <20170907184447.22752-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907184447.22752-1-richard.henderson@linaro.org> References: <20170907184447.22752-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PULL 2/3] target/hppa: Convert to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson --- target/hppa/translate.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index cb4a3e6cb4..993438a60b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -38,7 +38,7 @@ typedef struct DisasCond { } DisasCond; =20 typedef struct DisasContext { - struct TranslationBlock *tb; + DisasContextBase base; CPUState *cs; =20 target_ulong iaoq_f; @@ -52,7 +52,6 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; =20 - bool singlestep_enabled; bool psw_n_nonzero; } DisasContext; =20 @@ -476,7 +475,7 @@ static DisasJumpType gen_illegal(DisasContext *ctx) static bool use_goto_tb(DisasContext *ctx, target_ulong dest) { /* Suppress goto_tb in the case of single-steping and IO. */ - if ((ctx->tb->cflags & CF_LAST_IO) || ctx->singlestep_enabled) { + if ((ctx->base.tb->cflags & CF_LAST_IO) || ctx->base.singlestep_enable= d) { return false; } return true; @@ -499,11 +498,11 @@ static void gen_goto_tb(DisasContext *ctx, int which, tcg_gen_goto_tb(which); tcg_gen_movi_tl(cpu_iaoq_f, f); tcg_gen_movi_tl(cpu_iaoq_b, b); - tcg_gen_exit_tb((uintptr_t)ctx->tb + which); + tcg_gen_exit_tb((uintptr_t)ctx->base.tb + which); } else { copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b); copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var); - if (ctx->singlestep_enabled) { + if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); @@ -3737,11 +3736,11 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) DisasJumpType ret; int num_insns, max_insns, i; =20 - ctx.tb =3D tb; + ctx.base.tb =3D tb; + ctx.base.singlestep_enabled =3D cs->singlestep_enabled; ctx.cs =3D cs; ctx.iaoq_f =3D tb->pc; ctx.iaoq_b =3D tb->cs_base; - ctx.singlestep_enabled =3D cs->singlestep_enabled; =20 ctx.ntemps =3D 0; for (i =3D 0; i < ARRAY_SIZE(ctx.temps); ++i) { @@ -3755,7 +3754,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } - if (ctx.singlestep_enabled || singlestep) { + if (ctx.base.singlestep_enabled || singlestep) { max_insns =3D 1; } else if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; @@ -3868,7 +3867,7 @@ void gen_intermediate_code(CPUState *cs, struct Trans= lationBlock *tb) nullify_save(&ctx); /* FALLTHRU */ case DISAS_IAQ_N_UPDATED: - if (ctx.singlestep_enabled) { + if (ctx.base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); --=20 2.13.5 From nobody Mon Apr 29 07:37:34 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504810116150985.2955786831114; Thu, 7 Sep 2017 11:48:36 -0700 (PDT) Received: from localhost ([::1]:41749 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1qt-0007BI-3F for importer@patchew.org; Thu, 07 Sep 2017 14:48:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51205) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq1nP-0004Wo-OS for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:45:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dq1nK-0005Yp-Al for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:44:59 -0400 Received: from mail-pg0-x232.google.com ([2607:f8b0:400e:c05::232]:35945) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dq1nK-0005Yd-1s for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:44:54 -0400 Received: by mail-pg0-x232.google.com with SMTP id m9so966084pgd.3 for ; Thu, 07 Sep 2017 11:44:53 -0700 (PDT) Received: from pike.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id r68sm464247pfi.7.2017.09.07.11.44.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 11:44:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z1sJABLVpXpo0CVvDQumXNOcHbVRXrgjYnx6nBnvymE=; b=k3GtQafUDxFj2uYPlClQ2NavtYZnJRbOlqZjJYIATgU7pnXFEymyxUaKAiVgpSjgnS g4u1Xx1/5xUgJZASjliG/P7a+q+R8V0+aeGbAeko2oFgYeCPxTvFRMPf8CZsnFSs/5Gq BjiDKucqaRtMnrif95L5999ZJGlDZ8bm9fffs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z1sJABLVpXpo0CVvDQumXNOcHbVRXrgjYnx6nBnvymE=; b=ffzAeQ1emohO12xsCMiIb02CMOTY/BRWOKqLA1YUrsZ8PSwa5tjI0HyckYA/v14c3c HS+aF9NGRdbTCzHyZGvhKE7qWuUgnYAyCkZ5MA3wHslTnTxuQnb5xuigGd4TmAXj8OsY rwJDf1xKmr7a23HrAC5UVsjWiqxQHcUTdaF7xHM8t3iVbIpJxeOKNQGxRlPLzOyKL3I3 Nh3+e9F5Zd8nDecSd8EqoZBMXp1QhK1IIjnlrcLxAcn1WGh/z4OnqiL6SL9HWReY/7hO km6l4xawENfF0Gug6/vmk7U/Zek4x0mpr2IEZEc51td++ahQsMa3Y126+E9E2J2glYa2 mCEw== X-Gm-Message-State: AHPjjUiPX70xembAAV5R0ZgxUcaQC/GwQr9ua6OdAs1WVNB1PCFVxpCV Jc//Y3NOZkyYvjbHanXwgg== X-Google-Smtp-Source: ADKCNb411lQdEJ+HgwpVTHQZrlYkjkXkolqQHLhkT6T4ODXtLLaqZ1lb0s6sp2FP6RjEJM95kN61VQ== X-Received: by 10.98.206.194 with SMTP id y185mr357474pfg.28.1504809892669; Thu, 07 Sep 2017 11:44:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 11:44:47 -0700 Message-Id: <20170907184447.22752-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907184447.22752-1-richard.henderson@linaro.org> References: <20170907184447.22752-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::232 Subject: [Qemu-devel] [PULL 3/3] target/hppa: Convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson --- target/hppa/translate.c | 302 +++++++++++++++++++++++++-------------------= ---- 1 file changed, 159 insertions(+), 143 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 993438a60b..b6e2652341 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3729,185 +3729,201 @@ static DisasJumpType translate_one(DisasContext *= ctx, uint32_t insn) return gen_illegal(ctx); } =20 -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) +static int hppa_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs, int max_insns) { - CPUHPPAState *env =3D cs->env_ptr; - DisasContext ctx; - DisasJumpType ret; - int num_insns, max_insns, i; + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + TranslationBlock *tb =3D ctx->base.tb; + int i, bound; =20 - ctx.base.tb =3D tb; - ctx.base.singlestep_enabled =3D cs->singlestep_enabled; - ctx.cs =3D cs; - ctx.iaoq_f =3D tb->pc; - ctx.iaoq_b =3D tb->cs_base; + ctx->cs =3D cs; + ctx->iaoq_f =3D tb->pc; + ctx->iaoq_b =3D tb->cs_base; + ctx->iaoq_n =3D -1; + TCGV_UNUSED(ctx->iaoq_n_var); =20 - ctx.ntemps =3D 0; - for (i =3D 0; i < ARRAY_SIZE(ctx.temps); ++i) { - TCGV_UNUSED(ctx.temps[i]); + ctx->ntemps =3D 0; + for (i =3D 0; i < ARRAY_SIZE(ctx->temps); ++i) { + TCGV_UNUSED(ctx->temps[i]); } =20 - /* Compute the maximum number of insns to execute, as bounded by - (1) icount, (2) single-stepping, (3) branch delay slots, or - (4) the number of insns remaining on the current page. */ - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (ctx.base.singlestep_enabled || singlestep) { - max_insns =3D 1; - } else if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } + bound =3D -(tb->pc | TARGET_PAGE_MASK) / 4; + return MIN(max_insns, bound); +} =20 - num_insns =3D 0; - gen_tb_start(tb); +static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 /* Seed the nullification status from PSW[N], as shown in TB->FLAGS. = */ - ctx.null_cond =3D cond_make_f(); - ctx.psw_n_nonzero =3D false; - if (tb->flags & 1) { - ctx.null_cond.c =3D TCG_COND_ALWAYS; - ctx.psw_n_nonzero =3D true; + ctx->null_cond =3D cond_make_f(); + ctx->psw_n_nonzero =3D false; + if (ctx->base.tb->flags & 1) { + ctx->null_cond.c =3D TCG_COND_ALWAYS; + ctx->psw_n_nonzero =3D true; } - ctx.null_lab =3D NULL; + ctx->null_lab =3D NULL; +} =20 - do { - tcg_gen_insn_start(ctx.iaoq_f, ctx.iaoq_b); - num_insns++; +static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - if (unlikely(cpu_breakpoint_test(cs, ctx.iaoq_f, BP_ANY))) { - ret =3D gen_excp(&ctx, EXCP_DEBUG); - break; - } - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } + tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b); +} + +static bool hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= s, + const CPUBreakpoint *bp) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - if (ctx.iaoq_f < TARGET_PAGE_SIZE) { - ret =3D do_page_zero(&ctx); - assert(ret !=3D DISAS_NEXT); + ctx->base.is_jmp =3D gen_excp(ctx, EXCP_DEBUG); + ctx->base.pc_next =3D ctx->iaoq_f + 4; + return true; +} + +static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPUHPPAState *env =3D cs->env_ptr; + DisasJumpType ret; + int i, n; + + /* Execute one insn. */ + if (ctx->iaoq_f < TARGET_PAGE_SIZE) { + ret =3D do_page_zero(ctx); + assert(ret !=3D DISAS_NEXT); + } else { + /* Always fetch the insn, even if nullified, so that we check + the page permissions for execute. */ + uint32_t insn =3D cpu_ldl_code(env, ctx->iaoq_f); + + /* Set up the IA queue for the next insn. + This will be overwritten by a branch. */ + if (ctx->iaoq_b =3D=3D -1) { + ctx->iaoq_n =3D -1; + ctx->iaoq_n_var =3D get_temp(ctx); + tcg_gen_addi_tl(ctx->iaoq_n_var, cpu_iaoq_b, 4); } else { - /* Always fetch the insn, even if nullified, so that we check - the page permissions for execute. */ - uint32_t insn =3D cpu_ldl_code(env, ctx.iaoq_f); - - /* Set up the IA queue for the next insn. - This will be overwritten by a branch. */ - if (ctx.iaoq_b =3D=3D -1) { - ctx.iaoq_n =3D -1; - ctx.iaoq_n_var =3D get_temp(&ctx); - tcg_gen_addi_tl(ctx.iaoq_n_var, cpu_iaoq_b, 4); - } else { - ctx.iaoq_n =3D ctx.iaoq_b + 4; - TCGV_UNUSED(ctx.iaoq_n_var); - } - - if (unlikely(ctx.null_cond.c =3D=3D TCG_COND_ALWAYS)) { - ctx.null_cond.c =3D TCG_COND_NEVER; - ret =3D DISAS_NEXT; - } else { - ret =3D translate_one(&ctx, insn); - assert(ctx.null_lab =3D=3D NULL); - } + ctx->iaoq_n =3D ctx->iaoq_b + 4; + TCGV_UNUSED(ctx->iaoq_n_var); } =20 - for (i =3D 0; i < ctx.ntemps; ++i) { - tcg_temp_free(ctx.temps[i]); - TCGV_UNUSED(ctx.temps[i]); - } - ctx.ntemps =3D 0; - - /* If we see non-linear instructions, exhaust instruction count, - or run out of buffer space, stop generation. */ - /* ??? The non-linear instruction restriction is purely due to - the debugging dump. Otherwise we *could* follow unconditional - branches within the same page. */ - if (ret =3D=3D DISAS_NEXT - && (ctx.iaoq_b !=3D ctx.iaoq_f + 4 - || num_insns >=3D max_insns - || tcg_op_buf_full())) { - if (ctx.null_cond.c =3D=3D TCG_COND_NEVER - || ctx.null_cond.c =3D=3D TCG_COND_ALWAYS) { - nullify_set(&ctx, ctx.null_cond.c =3D=3D TCG_COND_ALWAYS); - gen_goto_tb(&ctx, 0, ctx.iaoq_b, ctx.iaoq_n); - ret =3D DISAS_NORETURN; - } else { - ret =3D DISAS_IAQ_N_STALE; - } + if (unlikely(ctx->null_cond.c =3D=3D TCG_COND_ALWAYS)) { + ctx->null_cond.c =3D TCG_COND_NEVER; + ret =3D DISAS_NEXT; + } else { + ret =3D translate_one(ctx, insn); + assert(ctx->null_lab =3D=3D NULL); } + } =20 - ctx.iaoq_f =3D ctx.iaoq_b; - ctx.iaoq_b =3D ctx.iaoq_n; - if (ret =3D=3D DISAS_NORETURN || ret =3D=3D DISAS_IAQ_N_UPDATED) { - break; - } - if (ctx.iaoq_f =3D=3D -1) { - tcg_gen_mov_tl(cpu_iaoq_f, cpu_iaoq_b); - copy_iaoq_entry(cpu_iaoq_b, ctx.iaoq_n, ctx.iaoq_n_var); - nullify_save(&ctx); - ret =3D DISAS_IAQ_N_UPDATED; - break; - } - if (ctx.iaoq_b =3D=3D -1) { - tcg_gen_mov_tl(cpu_iaoq_b, ctx.iaoq_n_var); - } - } while (ret =3D=3D DISAS_NEXT); + /* Free any temporaries allocated. */ + for (i =3D 0, n =3D ctx->ntemps; i < n; ++i) { + tcg_temp_free(ctx->temps[i]); + TCGV_UNUSED(ctx->temps[i]); + } + ctx->ntemps =3D 0; =20 - if (tb->cflags & CF_LAST_IO) { - gen_io_end(); + /* Advance the insn queue. */ + /* ??? The non-linear instruction restriction is purely due to + the debugging dump. Otherwise we *could* follow unconditional + branches within the same page. */ + if (ret =3D=3D DISAS_NEXT && ctx->iaoq_b !=3D ctx->iaoq_f + 4) { + if (ctx->null_cond.c =3D=3D TCG_COND_NEVER + || ctx->null_cond.c =3D=3D TCG_COND_ALWAYS) { + nullify_set(ctx, ctx->null_cond.c =3D=3D TCG_COND_ALWAYS); + gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); + ret =3D DISAS_NORETURN; + } else { + ret =3D DISAS_IAQ_N_STALE; + } } + ctx->iaoq_f =3D ctx->iaoq_b; + ctx->iaoq_b =3D ctx->iaoq_n; + ctx->base.is_jmp =3D ret; + + if (ret =3D=3D DISAS_NORETURN || ret =3D=3D DISAS_IAQ_N_UPDATED) { + return; + } + if (ctx->iaoq_f =3D=3D -1) { + tcg_gen_mov_tl(cpu_iaoq_f, cpu_iaoq_b); + copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); + nullify_save(ctx); + ctx->base.is_jmp =3D DISAS_IAQ_N_UPDATED; + } else if (ctx->iaoq_b =3D=3D -1) { + tcg_gen_mov_tl(cpu_iaoq_b, ctx->iaoq_n_var); + } +} + +static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - switch (ret) { + switch (ctx->base.is_jmp) { case DISAS_NORETURN: break; + case DISAS_TOO_MANY: case DISAS_IAQ_N_STALE: - copy_iaoq_entry(cpu_iaoq_f, ctx.iaoq_f, cpu_iaoq_f); - copy_iaoq_entry(cpu_iaoq_b, ctx.iaoq_b, cpu_iaoq_b); - nullify_save(&ctx); + copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); + copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); + nullify_save(ctx); /* FALLTHRU */ case DISAS_IAQ_N_UPDATED: - if (ctx.base.singlestep_enabled) { + if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_iaoq_f); } break; default: - abort(); + g_assert_not_reached(); } =20 - gen_tb_end(tb, num_insns); + /* We don't actually use this during normal translation, + but we should interact with the generic main loop. */ + ctx->base.pc_next =3D ctx->base.tb->pc + 4 * ctx->base.num_insns; +} =20 - tb->size =3D num_insns * 4; - tb->icount =3D num_insns; +static void hppa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) +{ + TranslationBlock *tb =3D dcbase->tb; =20 -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(tb->pc)) { - qemu_log_lock(); - switch (tb->pc) { - case 0x00: - qemu_log("IN:\n0x00000000: (null)\n\n"); - break; - case 0xb0: - qemu_log("IN:\n0x000000b0: light-weight-syscall\n\n"); - break; - case 0xe0: - qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n\n"); - break; - case 0x100: - qemu_log("IN:\n0x00000100: syscall\n\n"); - break; - default: - qemu_log("IN: %s\n", lookup_symbol(tb->pc)); - log_target_disas(cs, tb->pc, tb->size, 1); - qemu_log("\n"); - break; - } - qemu_log_unlock(); + switch (tb->pc) { + case 0x00: + qemu_log("IN:\n0x00000000: (null)\n"); + break; + case 0xb0: + qemu_log("IN:\n0x000000b0: light-weight-syscall\n"); + break; + case 0xe0: + qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n"); + break; + case 0x100: + qemu_log("IN:\n0x00000100: syscall\n"); + break; + default: + qemu_log("IN: %s\n", lookup_symbol(tb->pc)); + log_target_disas(cs, tb->pc, tb->size, 1); + break; } -#endif +} + +static const TranslatorOps hppa_tr_ops =3D { + .init_disas_context =3D hppa_tr_init_disas_context, + .tb_start =3D hppa_tr_tb_start, + .insn_start =3D hppa_tr_insn_start, + .breakpoint_check =3D hppa_tr_breakpoint_check, + .translate_insn =3D hppa_tr_translate_insn, + .tb_stop =3D hppa_tr_tb_stop, + .disas_log =3D hppa_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) + +{ + DisasContext ctx; + translator_loop(&hppa_tr_ops, &ctx.base, cs, tb); } =20 void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb, --=20 2.13.5