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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wHWrXUvCoyl4+HP2sLpsgj4++zHbUrdBKSZ1VeXF5H0=; b=SCVQNdcJQoF/1YSCk3mBFhe6jUTH9iTXprE7kt11wdnEpAWsIQfgHh0Ui2HZI7qlZ5 lElbolg7SM0GWIvQH6X6wTnJs8xiCLfewt0hEC24kL22DKr9Fj2xY7+JQ/Xa/cmjuRY3 qW40RzRgygpEzW9xhlLdZ1kTUBH6R4ARAS23k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wHWrXUvCoyl4+HP2sLpsgj4++zHbUrdBKSZ1VeXF5H0=; b=GYnC9p4MZ9DJgKMHkfizQYm+1PB43JL5DYNtH6YcXhpSCwxwGGgaj/XREj/2IWoBwH PcALJ4H2e55N8N2ly/N2rJBWIkCEiN9W7b11R8L8zHU3fWMFL9cNxBoGD8UU6cku/EIe EJ1/cBk5Nq88FAPBcryAoZVyOYG/QN+OcBQpEv000AQdrWhLvYIfFim9UWyNgA3t9Ncb UAIz3N/H0IM35esXSA09RpzlYWyu+nbkH5qD0dSQVZXdhwSAU8gTXQsZ6bEbCd6vJ5Jn bGHXcEoXd6dFAGJ5S20NFkeEgNI7uvravvCw9HxHuMg4jzx8GG6Jq6rbbq2JlNYMS6RZ KrIg== X-Gm-Message-State: AHPjjUglZREOhZVxHNxd6pUgQiHgjsRSrVkkPLzXIxNyE7CS+wm5Q5Mn Jihu2Z6f0cp+Vl/DlZ9hHg== X-Google-Smtp-Source: ADKCNb6FEjNUMgTTJy1+VTQksaUiFoKkx9f4vQixkgwuPJ0mj+rupkL8gQzA3qL+jWqbVaBk96aWVg== X-Received: by 10.99.104.6 with SMTP id d6mr8232156pgc.168.1504714015929; Wed, 06 Sep 2017 09:06:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:11 -0700 Message-Id: <20170906160612.22769-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22d Subject: [Qemu-devel] [PULL 31/32] target/arm: Split out thumb_tr_translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson We need not check for ARM vs Thumb state in order to dispatch disassembly of every instruction. Tested-by: Emilio G. Cota Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.c | 121 ++++++++++++++++++++++++++++++++-------------= ---- 1 file changed, 80 insertions(+), 41 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0dd24aad90..9e7bfbcf0c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11981,11 +11981,8 @@ static bool arm_tr_breakpoint_check(DisasContextBa= se *dcbase, CPUState *cpu, return true; } =20 -static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +static bool arm_pre_translate_insn(DisasContext *dc) { - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUARMState *env =3D cpu->env_ptr; - #ifdef CONFIG_USER_ONLY /* Intercept jump to the magic kernel page. */ if (dc->pc >=3D 0xffff0000) { @@ -11993,7 +11990,7 @@ static void arm_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) conditional execution block. */ gen_exception_internal(EXCP_KERNEL_TRAP); dc->base.is_jmp =3D DISAS_NORETURN; - return; + return true; } #endif =20 @@ -12012,56 +12009,85 @@ static void arm_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); dc->base.is_jmp =3D DISAS_NORETURN; - return; + return true; } =20 - if (dc->thumb) { - disas_thumb_insn(env, dc); - if (dc->condexec_mask) { - dc->condexec_cond =3D (dc->condexec_cond & 0xe) - | ((dc->condexec_mask >> 4) & 1); - dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; - if (dc->condexec_mask =3D=3D 0) { - dc->condexec_cond =3D 0; - } - } - } else { - unsigned int insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); - dc->pc +=3D 4; - disas_arm_insn(dc, insn); - } + return false; +} =20 +static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc) +{ if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp =3D 0; } =20 - if (dc->base.is_jmp =3D=3D DISAS_NEXT) { - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several time= s. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. */ - - if (dc->pc >=3D dc->next_page_start || - (dc->pc >=3D dc->next_page_start - 3 && - insn_crosses_page(env, dc))) { - /* We want to stop the TB if the next insn starts in a new pag= e, - * or if it spans between this page and the next. This means t= hat - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit= insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - dc->base.is_jmp =3D DISAS_TOO_MANY; - } + /* Translation stops when a conditional branch is encountered. + * Otherwise the subsequent code could get translated several times. + * Also stop translation when a page boundary is reached. This + * ensures prefetch aborts occur at the right place. + * + * We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + if (dc->base.is_jmp =3D=3D DISAS_NEXT + && (dc->pc >=3D dc->next_page_start + || (dc->pc >=3D dc->next_page_start - 3 + && insn_crosses_page(env, dc)))) { + dc->base.is_jmp =3D DISAS_TOO_MANY; } =20 dc->base.pc_next =3D dc->pc; translator_loop_temp_check(&dc->base); } =20 +static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + unsigned int insn; + + if (arm_pre_translate_insn(dc)) { + return; + } + + insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->pc +=3D 4; + disas_arm_insn(dc, insn); + + arm_post_translate_insn(env, dc); +} + +static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + + if (arm_pre_translate_insn(dc)) { + return; + } + + disas_thumb_insn(env, dc); + + /* Advance the Thumb condexec condition. */ + if (dc->condexec_mask) { + dc->condexec_cond =3D ((dc->condexec_cond & 0xe) | + ((dc->condexec_mask >> 4) & 1)); + dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; + if (dc->condexec_mask =3D=3D 0) { + dc->condexec_cond =3D 0; + } + } + + arm_post_translate_insn(env, dc); +} + static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -12198,12 +12224,25 @@ static const TranslatorOps arm_translator_ops =3D= { .disas_log =3D arm_tr_disas_log, }; =20 +static const TranslatorOps thumb_translator_ops =3D { + .init_disas_context =3D arm_tr_init_disas_context, + .tb_start =3D arm_tr_tb_start, + .insn_start =3D arm_tr_insn_start, + .breakpoint_check =3D arm_tr_breakpoint_check, + .translate_insn =3D thumb_tr_translate_insn, + .tb_stop =3D arm_tr_tb_stop, + .disas_log =3D arm_tr_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { DisasContext dc; const TranslatorOps *ops =3D &arm_translator_ops; =20 + if (ARM_TBFLAG_THUMB(tb->flags)) { + ops =3D &thumb_translator_ops; + } #ifdef TARGET_AARCH64 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { ops =3D &aarch64_translator_ops; --=20 2.13.5