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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iQeSsig0LrUqKt2taUtiV4ym+Ibb3h0DSczL0zy/jlI=; b=hETCc4cw7yVmnPV8rZJwmsDQtApG2o8yEaFLh4XeHkHvM4aL+7k/O7DjcO2POnhINF mbpua6C7x4p/g5cZtt7GQUrgN1DxwggNrUT5zlcU1uydyf2ft8Mlp1cP2HUKZLAAOzKo vSWLgphpWlApLM7yXkGQa4EfL9rJPvv1gal+4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iQeSsig0LrUqKt2taUtiV4ym+Ibb3h0DSczL0zy/jlI=; b=d+hVqhNTckxK9OqTuUR6zv3a4ZUEmaOKO7zhAZGH+Ics/GXafaTkiIqMh1qWmcLibT iV7KkvkV+ZMjWHS+LhfGWimVO3yrKcJrMHntzdTqWu6xMlxVzuz4WUJJyYslhUMkWpVZ Rm5ylIZNapxyT5G4vcm0IFzw1U6RSBx+Lt816OnZkb5F5PmbqvMBGlLg0lHOuMNr+eXn FIWth8Le6hG1rfmeuP138DkoPIPOgp5Mp9ATBht0I1dmeDRglaUTC55hw9Ubx+ezFys+ Pgzprg7mr4kMZJH8FeWq1yYOOi5HN40bucC3RkyzA0Jfp5zsmHfHIHBDJEn9BGjP/1Kt DMEA== X-Gm-Message-State: AHPjjUgKD+O9X5UMYFNh06ipK9dtQzCzpGhNM+iG/XMFUXElMqFl2tk5 zJEXKD5w1/NFlqf13YoH2w== X-Google-Smtp-Source: ADKCNb7CnWHxlRZxLds7i6fJCeqa632A5C1gR7kMrb5beaXuP8lI7FrdGKC7lIsM1W9nNVr/6YcGFw== X-Received: by 10.99.109.142 with SMTP id i136mr8073200pgc.353.1504714003003; Wed, 06 Sep 2017 09:06:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:01 -0700 Message-Id: <20170906160612.22769-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PULL 21/32] target/arm: [tcg, a64] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002461630.22386.14827196109258040543.stgit@frigg.lan> [rth: Use DISAS_TOO_MANY for "execute only one more" after bp.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++------------= ---- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1eab10696c..e94198280d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11267,6 +11267,30 @@ static void aarch64_tr_insn_start(DisasContextBase= *dcbase, CPUState *cpu) tcg_gen_insn_start(dc->pc, 0, 0); } =20 +static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_a64_set_pc_im(dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it likely won't be executed */ + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + dc->pc +=3D 4; + dc->base.is_jmp =3D DISAS_NORETURN; + } + + return true; +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11303,25 +11327,15 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->pc) { - if (bp->flags & BP_CPU) { - gen_a64_set_pc_im(dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it likely won't be executed */ - dc->base.is_jmp =3D DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [dc->base.tb->pc, dc->base.tb->pc += dc->base.tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - dc->base.tb->size below does the right thing. = */ - dc->pc +=3D 4; - goto done_generating; + if (bp->pc =3D=3D dc->base.pc_next) { + if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) { + break; } - break; } } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } } =20 if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { @@ -11392,6 +11406,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, } else { switch (dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; case DISAS_JUMP: @@ -11429,7 +11444,6 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, } } =20 -done_generating: gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS --=20 2.13.5