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X-Received-From: 2607:f8b0:400e:c05::230 Subject: [Qemu-devel] [PULL 01/32] tcg: Add generic DISAS_NORETURN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Richard Henderson This will allow some amount of cleanup to happen before switching the backends over to enum DisasJumpType. Reviewed-by: Emilio G. Cota Reviewed-by: Llu=C3=ADs Vilanova Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 440fc31b37..b434988979 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -63,6 +63,7 @@ typedef ram_addr_t tb_page_addr_t; #define DISAS_JUMP 1 /* only pc was modified dynamically */ #define DISAS_TB_JUMP 2 /* only pc was modified statically */ #define DISAS_UPDATE 3 /* cpu state was modified dynamically */ +#define DISAS_NORETURN 4 /* the tb has already been exited */ =20 #include "qemu/log.h" =20 --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150471410709973.84143162171324; Wed, 6 Sep 2017 09:08:27 -0700 (PDT) Received: from localhost ([::1]:36962 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcsL-0001Sq-Rn for importer@patchew.org; Wed, 06 Sep 2017 12:08:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqL-0008MH-5d for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqI-0001V2-IS for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:21 -0400 Received: from mail-pf0-x22c.google.com ([2607:f8b0:400e:c00::22c]:34779) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqI-0001UB-At for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:18 -0400 Received: by mail-pf0-x22c.google.com with SMTP id m1so13484072pfk.1 for ; Wed, 06 Sep 2017 09:06:18 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oktER+wQnBzv+YFYPe9eDSwDzOT9j+VLlJ0DA6KaCfc=; b=QP4/mR22W97tNZeuIsjeUS1wcN5dzNYXiM02/CctYzMSO/pc6R24rnx0DqBLLKCl7J xo9bGZegILi3ytnnim1C2qT0XXzzKOEtsZAB0d3G0USXTFnGO7tnlTRybZcQH0Qa3lUM J8ZDNgb26Yr/yGQagGS1PjnKcFe7JRnoy2u7c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oktER+wQnBzv+YFYPe9eDSwDzOT9j+VLlJ0DA6KaCfc=; b=dOF9rxo9uwpUsAXJpCB+tFMScme/FIEEbcpLu+HsMHcuv9OA6GiDOIXUoJlZf1tNt0 4wVW8mgEGZXGa+hBxYWOuRBCT248toxFd7Dq2xubUKpteRcnjtPJ2ky5GA1AMGqYVNcF ZvZckUFIZJ6+OBoP4WwTIxqJp8JTXhDEADa5t3Kvp2BzxLiiAbK21VD9vjCusUHbCRPY jNdL6H52w8Q4CmQsFUO697Zy3jTOi0zMbXX3+Wjzgo2cp3oOafKCJXWGVnupS3QpRFy1 O3Daf2AhK1DApHKIJqN2zTmWP2u0A5FPV6xBWygAt4SvlIFZb4bE5dKuCwT2YehNm6ay sVoA== X-Gm-Message-State: AHPjjUhPHeKLDjyOeR8S5QyR9uoCL0MZ1bHVOkCyjwC3phxvQOBNqho8 ghQ6btVXaAJKtbZmJC7vSQ== X-Google-Smtp-Source: ADKCNb5HrxweZeF6botC2mBMtGXtfgFqKHrEz080ysQfRMWWPwkAAVGSZ/NtVMc1XnRr5JIaHXdSWQ== X-Received: by 10.99.126.84 with SMTP id o20mr8271426pgn.137.1504713976979; Wed, 06 Sep 2017 09:06:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:42 -0700 Message-Id: <20170906160612.22769-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PULL 02/32] target/i386: Use generic DISAS_* enumerators X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This target is not sophisticated in its use of cleanups at the end of the translation loop. For the most part, any condition that exits the TB is dealt with by emitting the exiting opcode right then and there. Therefore the only is_jmp indicator that is needed is DISAS_NORETURN. For two stack segment modifying cases, we have not yet exited the TB (therefore DISAS_NORETURN feels wrong), but intend to exit. The caller of gen_movl_seg_T0 currently checks for any non-zero value, therefore DISAS_TOO_MANY seems acceptable for that usage. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/i386/translate.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 5fdadf98cf..26e8002433 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -31,6 +31,7 @@ #include "trace-tcg.h" #include "exec/log.h" =20 +#define DISAS_TOO_MANY 5 =20 #define PREFIX_REPZ 0x01 #define PREFIX_REPNZ 0x02 @@ -2153,6 +2154,7 @@ static inline void gen_goto_tb(DisasContext *s, int t= b_num, target_ulong eip) tcg_gen_goto_tb(tb_num); gen_jmp_im(eip); tcg_gen_exit_tb((uintptr_t)s->tb + tb_num); + s->is_jmp =3D DISAS_NORETURN; } else { /* jump to another page */ gen_jmp_im(eip); @@ -2173,7 +2175,6 @@ static inline void gen_jcc(DisasContext *s, int b, =20 gen_set_label(l1); gen_goto_tb(s, 1, val); - s->is_jmp =3D DISAS_TB_JUMP; } else { l1 =3D gen_new_label(); l2 =3D gen_new_label(); @@ -2243,12 +2244,14 @@ static void gen_movl_seg_T0(DisasContext *s, int se= g_reg) because ss32 may change. For R_SS, translation must always stop as a special handling must be done to disable hardware interrupts for the next instruction */ - if (seg_reg =3D=3D R_SS || (s->code32 && seg_reg < R_FS)) - s->is_jmp =3D DISAS_TB_JUMP; + if (seg_reg =3D=3D R_SS || (s->code32 && seg_reg < R_FS)) { + s->is_jmp =3D DISAS_TOO_MANY; + } } else { gen_op_movl_seg_T0_vm(seg_reg); - if (seg_reg =3D=3D R_SS) - s->is_jmp =3D DISAS_TB_JUMP; + if (seg_reg =3D=3D R_SS) { + s->is_jmp =3D DISAS_TOO_MANY; + } } } =20 @@ -2420,7 +2423,7 @@ static void gen_exception(DisasContext *s, int trapno= , target_ulong cur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 /* Generate #UD for the current instruction. The assumption here is that @@ -2458,7 +2461,7 @@ static void gen_interrupt(DisasContext *s, int intno, gen_jmp_im(cur_eip); gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), tcg_const_i32(next_eip - cur_eip)); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_debug(DisasContext *s, target_ulong cur_eip) @@ -2466,7 +2469,7 @@ static void gen_debug(DisasContext *s, target_ulong c= ur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_debug(cpu_env); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_set_hflag(DisasContext *s, uint32_t mask) @@ -2541,7 +2544,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool= recheck_tf, TCGv jr) } else { tcg_gen_exit_tb(0); } - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 static inline void @@ -2580,7 +2583,6 @@ static void gen_jmp_tb(DisasContext *s, target_ulong = eip, int tb_num) set_cc_op(s, CC_OP_DYNAMIC); if (s->jmp_opt) { gen_goto_tb(s, tb_num, eip); - s->is_jmp =3D DISAS_TB_JUMP; } else { gen_jmp_im(eip); gen_eob(s); @@ -6943,7 +6945,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } break; case 0x9b: /* fwait */ @@ -7188,7 +7190,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } break; case 0x100: @@ -7371,7 +7373,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), tcg_const_i32(s->pc - pc_start)); tcg_gen_exit_tb(0); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; break; =20 case 0xd9: /* VMMCALL */ --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714286467777.8666962445526; Wed, 6 Sep 2017 09:11:26 -0700 (PDT) Received: from localhost ([::1]:36975 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcvF-0003u9-EQ for importer@patchew.org; Wed, 06 Sep 2017 12:11:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41616) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqU-0008PF-2L for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqK-0001bI-5d for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:30 -0400 Received: from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:35362) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqJ-0001X0-T7 for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:20 -0400 Received: by mail-pf0-x22a.google.com with SMTP id g13so13482162pfm.2 for ; Wed, 06 Sep 2017 09:06:19 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=l+8GeftkxPUaXtKmP8H3x4UyaNFhwhYJYRyE/2Xhemc=; b=J/SiTef0adAzAMrAKHufhcZAKXV0nCC67Uo8meXk6aAfOw1L5zpxVFsyQPm3frgphC /kFJUCjEZqn4SQeA2jT9BoOK8dlVvlf4MRtC3Lnef6pTWgLt/qmM3B9zd6jHpus3SZjJ cVvh1oXz49bWNjqikGEVy2nt5XSPUc6YO+rGk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l+8GeftkxPUaXtKmP8H3x4UyaNFhwhYJYRyE/2Xhemc=; b=Xcg2mlVA/cqBln0f1c+d82ty9xnpJFA54fp9uRgFdhY7yaVDp7+5lpE8/tL7bJnZd0 oRPNpe4pwx+yMJ4vwy38YqSwZSxQ7Xne28jxAtxp0AG04u9Ka8l913qtvIowZfLVwLtI XusKXZgNy6LLPcrp7EvZ6jgq2bNQPVNrj4M/BupYOj9vYlMM0Tdb2hV03B0cbDfI+ne+ qGcXhQyR5t+ENGI9A3JnNnIu5VjSILDH4yZPrjO9+GCEmLVHxu7+y8SWwxAV/8ySUGu7 8YY/VJVMkHZUqhg7UYsXuFKHk5I/hEQFZOsOW3YKE/CZCOg2wTqAp5+4SAmZcTm+QnoW gbtg== X-Gm-Message-State: AHPjjUj41x6Nj/2Jy84T2s13x76MN+Pub2flMxEO0qTA45+K13lepp5d 8Hs8QzLniwkynMr0oPL8hA== X-Google-Smtp-Source: ADKCNb4c3C5poZzM2vw+9cHzXUxyOmivWqhUCoD5Ow/eiAOXQ4dLs6iweffpoPTPphiM/c3YKvFFKg== X-Received: by 10.99.115.28 with SMTP id o28mr8351773pgc.374.1504713978512; Wed, 06 Sep 2017 09:06:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:43 -0700 Message-Id: <20170906160612.22769-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PULL 03/32] target/arm: Use DISAS_NORETURN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Fold DISAS_EXC and DISAS_TB_JUMP into DISAS_NORETURN. In both cases all following code is dead. In the first case because we have exited the TB via exception; in the second case because we have exited the TB via goto_tb and its associated machinery. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.h | 8 ++------ target/arm/translate-a64.c | 37 ++++++++++++++++++++----------------- target/arm/translate.c | 14 ++++++++------ 3 files changed, 30 insertions(+), 29 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 2fe144baa9..90f64d9716 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -124,12 +124,8 @@ static void disas_set_insn_syndrome(DisasContext *s, u= int32_t syn) * defer them until after the conditional execution state has been updated. * WFI also needs special handling when single-stepping. */ -#define DISAS_WFI 4 -#define DISAS_SWI 5 -/* For instructions which unconditionally cause an exception we can skip - * emitting unreachable code at the end of the TB in the A64 decoder - */ -#define DISAS_EXC 6 +#define DISAS_WFI 5 +#define DISAS_SWI 6 /* WFE */ #define DISAS_WFE 7 #define DISAS_HVC 8 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cb44632d16..881d3c0cbb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -304,7 +304,7 @@ static void gen_exception_internal_insn(DisasContext *s= , int offset, int excp) { gen_a64_set_pc_im(s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -312,7 +312,7 @@ static void gen_exception_insn(DisasContext *s, int off= set, int excp, { gen_a64_set_pc_im(s->pc - offset); gen_exception(excp, syndrome, target_el); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_ss_advance(DisasContext *s) @@ -340,7 +340,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) @@ -371,7 +371,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, = uint64_t dest) tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); tcg_gen_exit_tb((intptr_t)tb + n); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } else { gen_a64_set_pc_im(dest); if (s->ss_active) { @@ -380,7 +380,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, = uint64_t dest) gen_exception_internal(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_pc); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } } } @@ -11326,7 +11326,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) assert(num_insns =3D=3D 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - dc->is_jmp =3D DISAS_EXC; + dc->is_jmp =3D DISAS_NORETURN; break; } =20 @@ -11353,21 +11353,25 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) gen_io_end(); } =20 - if (unlikely(cs->singlestep_enabled || dc->ss_active) - && dc->is_jmp !=3D DISAS_EXC) { + if (unlikely(cs->singlestep_enabled || dc->ss_active)) { /* Note that this means single stepping WFI doesn't halt the CPU. * For conditional branch insns this is harmless unreachable code = as * gen_goto_tb() has already handled emitting the debug exception * (and thus a tb-jump is not possible when singlestepping). */ - assert(dc->is_jmp !=3D DISAS_TB_JUMP); - if (dc->is_jmp !=3D DISAS_JUMP) { + switch (dc->is_jmp) { + default: gen_a64_set_pc_im(dc->pc); - } - if (cs->singlestep_enabled) { - gen_exception_internal(EXCP_DEBUG); - } else { - gen_step_complete_exception(dc); + /* fall through */ + case DISAS_JUMP: + if (cs->singlestep_enabled) { + gen_exception_internal(EXCP_DEBUG); + } else { + gen_step_complete_exception(dc); + } + break; + case DISAS_NORETURN: + break; } } else { switch (dc->is_jmp) { @@ -11377,8 +11381,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) case DISAS_JUMP: tcg_gen_lookup_and_goto_ptr(cpu_pc); break; - case DISAS_TB_JUMP: - case DISAS_EXC: + case DISAS_NORETURN: case DISAS_SWI: break; case DISAS_WFE: diff --git a/target/arm/translate.c b/target/arm/translate.c index e52a6d7622..b14329dc27 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -297,7 +297,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_singlestep_exception(DisasContext *s) @@ -1184,7 +1184,7 @@ static void gen_exception_internal_insn(DisasContext = *s, int offset, int excp) gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -1193,7 +1193,7 @@ static void gen_exception_insn(DisasContext *s, int o= ffset, int excp, gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception(excp, syn, target_el); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 /* Force a TB lookup after an instruction that changes the CPU state. */ @@ -11974,7 +11974,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) /* We always get here via a jump, so know we are not in a conditional execution block. */ gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp =3D DISAS_EXC; + dc->is_jmp =3D DISAS_NORETURN; break; } #endif @@ -12119,6 +12119,9 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) default: /* FIXME: Single stepping a WFI insn will not halt the CPU. */ gen_singlestep_exception(dc); + break; + case DISAS_NORETURN: + break; } } else { /* While branches must always occur at the end of an IT block, @@ -12143,8 +12146,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) /* indicate that the hash table must be used to find the next = TB */ tcg_gen_exit_tb(0); break; - case DISAS_TB_JUMP: - case DISAS_EXC: + case DISAS_NORETURN: /* nothing more to generate */ break; case DISAS_WFI: --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KGLbiRgGM9Mz5zskuosarjAY1Dtzs6FkBr2PJb4ER/8=; b=eZ/rXieZAjS8ur6a7W0VGqdXGvYotGdfpHNKjVpm7zFuPejuGXZR6FspB7LYKje0Uj ZBxRnS8GvyFdu78YzRInj80F6GlF891ON5dTbv358w1J924XatYVc09NaR692Nnx3g7o dDGLRKVGYxRxDpFdWRHEF/LhG18Be7o6LTwdU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KGLbiRgGM9Mz5zskuosarjAY1Dtzs6FkBr2PJb4ER/8=; b=aRvCDeH/H1stiPrM82+YVW7FJWhofoO/Y74BrmSoimIi6VBchxCG2CxDhtteZe+oDi OXaah1BlMpRl02rOXd6fTSZf3zNzl7DI5tkDzuYPojShZhL0DMDz7UTVYLDercrnBqmd QU97iQL1wWhVTz5pge40TPor6RiJ6eKCDxRuc3+mLQ0rlFBqb8hPTYzd7s4fx1kmdYPI vUSuGjgrIldx10+Hw9hNjhYVHYvjB4IKtl8TtBAQoE+rHvuJdfTepoJ40pmHe6uOfdoR TPJjz4XYGG05Z8FQy2Ac9NrWig4mVqkISoa/tnOGlxcIOsVq3Cck8LEGtqCbPOf1ikmW 7q2w== X-Gm-Message-State: AHPjjUia3RbsXh+468gLXw+vBilhnjeqxsFWZahBXeUcBHs1NAFZw7wu ukx5f5sWJIkLKu/OYMYbSw== X-Google-Smtp-Source: ADKCNb4tR+Xlfo6HotxXVxzi+L49UV0cgopjfs0W3o7MfvQFUihdZ71PbzImBvDfBqQPuwbcr5gs+A== X-Received: by 10.101.75.136 with SMTP id t8mr7867259pgq.359.1504713979834; Wed, 06 Sep 2017 09:06:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:44 -0700 Message-Id: <20170906160612.22769-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PULL 04/32] target: [tcg] Use a generic enum for DISAS_ values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Used later. An enum makes expected values explicit and bounds the value space of switches. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id: <150002049746.22386.2316077281615710615.stgit@frigg.lan> Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 30 ------------------------------ include/exec/translator.h | 40 ++++++++++++++++++++++++++++++++++++++++ target/arm/translate.h | 23 ++++++++++++++--------- target/arm/translate.c | 2 +- target/cris/translate.c | 7 ++++++- target/i386/translate.c | 3 +-- target/lm32/translate.c | 6 ++++++ target/m68k/translate.c | 7 ++++++- target/microblaze/translate.c | 6 ++++++ target/nios2/translate.c | 6 ++++++ target/openrisc/translate.c | 6 ++++++ target/s390x/translate.c | 3 ++- target/unicore32/translate.c | 7 ++++++- target/xtensa/translate.c | 4 ++++ 14 files changed, 104 insertions(+), 46 deletions(-) create mode 100644 include/exec/translator.h diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b434988979..ff8fbe423d 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -35,36 +35,6 @@ typedef abi_ulong tb_page_addr_t; typedef ram_addr_t tb_page_addr_t; #endif =20 -/* DisasContext is_jmp field values - * - * is_jmp starts as DISAS_NEXT. The translator will keep processing - * instructions until an exit condition is reached. If we reach the - * exit condition and is_jmp is still DISAS_NEXT (because of some - * other condition) we simply "jump" to the next address. - * The remaining exit cases are: - * - * DISAS_JUMP - Only the PC was modified dynamically (e.g computed) - * DISAS_TB_JUMP - Only the PC was modified statically (e.g. branch) - * - * In these cases as long as the PC is updated we can chain to the - * next TB either by exiting the loop or looking up the next TB via - * the loookup helper. - * - * DISAS_UPDATE - CPU State was modified dynamically - * - * This covers any other CPU state which necessities us exiting the - * TCG code to the main run-loop. Typically this includes anything - * that might change the interrupt state. - * - * Individual translators may define additional exit cases to deal - * with per-target special conditions. - */ -#define DISAS_NEXT 0 /* next instruction can be analyzed */ -#define DISAS_JUMP 1 /* only pc was modified dynamically */ -#define DISAS_TB_JUMP 2 /* only pc was modified statically */ -#define DISAS_UPDATE 3 /* cpu state was modified dynamically */ -#define DISAS_NORETURN 4 /* the tb has already been exited */ - #include "qemu/log.h" =20 void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb); diff --git a/include/exec/translator.h b/include/exec/translator.h new file mode 100644 index 0000000000..b51b8f8a4e --- /dev/null +++ b/include/exec/translator.h @@ -0,0 +1,40 @@ +/* + * Generic intermediate code generation. + * + * Copyright (C) 2016-2017 Llu=C3=ADs Vilanova + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef EXEC__TRANSLATOR_H +#define EXEC__TRANSLATOR_H + +/** + * DisasJumpType: + * @DISAS_NEXT: Next instruction in program order. + * @DISAS_TOO_MANY: Too many instructions translated. + * @DISAS_NORETURN: Following code is dead. + * @DISAS_TARGET_*: Start of target-specific conditions. + * + * What instruction to disassemble next. + */ +typedef enum DisasJumpType { + DISAS_NEXT, + DISAS_TOO_MANY, + DISAS_NORETURN, + DISAS_TARGET_0, + DISAS_TARGET_1, + DISAS_TARGET_2, + DISAS_TARGET_3, + DISAS_TARGET_4, + DISAS_TARGET_5, + DISAS_TARGET_6, + DISAS_TARGET_7, + DISAS_TARGET_8, + DISAS_TARGET_9, + DISAS_TARGET_10, + DISAS_TARGET_11, +} DisasJumpType; + +#endif /* EXEC__TRANSLATOR_H */ diff --git a/target/arm/translate.h b/target/arm/translate.h index 90f64d9716..1eb432dc2c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -1,6 +1,9 @@ #ifndef TARGET_ARM_TRANSLATE_H #define TARGET_ARM_TRANSLATE_H =20 +#include "exec/translator.h" + + /* internal defines */ typedef struct DisasContext { target_ulong pc; @@ -119,29 +122,31 @@ static void disas_set_insn_syndrome(DisasContext *s, = uint32_t syn) s->insn_start_idx =3D 0; } =20 -/* target-specific extra values for is_jmp */ +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically= */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamical= ly */ /* These instructions trap after executing, so the A32/T32 decoder must * defer them until after the conditional execution state has been updated. * WFI also needs special handling when single-stepping. */ -#define DISAS_WFI 5 -#define DISAS_SWI 6 +#define DISAS_WFI DISAS_TARGET_2 +#define DISAS_SWI DISAS_TARGET_3 /* WFE */ -#define DISAS_WFE 7 -#define DISAS_HVC 8 -#define DISAS_SMC 9 -#define DISAS_YIELD 10 +#define DISAS_WFE DISAS_TARGET_4 +#define DISAS_HVC DISAS_TARGET_5 +#define DISAS_SMC DISAS_TARGET_6 +#define DISAS_YIELD DISAS_TARGET_7 /* M profile branch which might be an exception return (and so needs * custom end-of-TB code) */ -#define DISAS_BX_EXCRET 11 +#define DISAS_BX_EXCRET DISAS_TARGET_8 /* For instructions which want an immediate exit to the main loop, * as opposed to attempting to use lookup_and_goto_ptr. Unlike * DISAS_UPDATE this doesn't write the PC on exiting the translation * loop so you need to ensure something (gen_a64_set_pc_im or runtime * helper) has done so before we reach return from cpu_tb_exec. */ -#define DISAS_EXIT 12 +#define DISAS_EXIT DISAS_TARGET_9 =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); diff --git a/target/arm/translate.c b/target/arm/translate.c index b14329dc27..0c39c2b996 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4174,7 +4174,7 @@ static void gen_goto_tb(DisasContext *s, int n, targe= t_ulong dest) gen_set_pc_im(s, dest); gen_goto_ptr(); } - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 static inline void gen_jmp (DisasContext *s, uint32_t dest) diff --git a/target/cris/translate.c b/target/cris/translate.c index 12b96eb68f..38a999e6f1 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -31,6 +31,7 @@ #include "exec/helper-proto.h" #include "mmu.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "crisv32-decode.h" =20 #include "exec/helper-gen.h" @@ -50,7 +51,11 @@ #define BUG() (gen_BUG(dc, __FILE__, __LINE__)) #define BUG_ON(x) ({if (x) BUG();}) =20 -#define DISAS_SWI 5 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ +#define DISAS_SWI DISAS_TARGET_3 =20 /* Used by the decoder. */ #define EXTRACT_FIELD(src, start, end) \ diff --git a/target/i386/translate.c b/target/i386/translate.c index 26e8002433..a0d8788c57 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -31,8 +32,6 @@ #include "trace-tcg.h" #include "exec/log.h" =20 -#define DISAS_TOO_MANY 5 - #define PREFIX_REPZ 0x01 #define PREFIX_REPNZ 0x02 #define PREFIX_LOCK 0x04 diff --git a/target/lm32/translate.c b/target/lm32/translate.c index f68f372f15..65bc9c0bf6 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -22,6 +22,7 @@ #include "disas/disas.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translator.h" #include "tcg-op.h" =20 #include "exec/cpu_ldst.h" @@ -47,6 +48,11 @@ =20 #define MEM_INDEX 0 =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + static TCGv_env cpu_env; static TCGv cpu_R[32]; static TCGv cpu_pc; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index be24355080..d738f32f9c 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -25,6 +25,7 @@ #include "tcg-op.h" #include "qemu/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -173,7 +174,11 @@ static void do_writebacks(DisasContext *s) } } =20 -#define DISAS_JUMP_NEXT 4 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically= */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamical= ly */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically = */ +#define DISAS_JUMP_NEXT DISAS_TARGET_3 =20 #if defined(CONFIG_USER_ONLY) #define IS_USER(s) 1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 83e2ef4960..067b0878d6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -27,6 +27,7 @@ #include "microblaze-decode.h" #include "exec/cpu_ldst.h" #include "exec/helper-gen.h" +#include "exec/translator.h" =20 #include "trace-tcg.h" #include "exec/log.h" @@ -46,6 +47,11 @@ #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + static TCGv env_debug; static TCGv_env cpu_env; static TCGv cpu_R[32]; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 8b97d6585f..6b0961837d 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -29,6 +29,12 @@ #include "exec/helper-gen.h" #include "exec/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" + +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ =20 #define INSTRUCTION_FLG(func, flags) { (func), (flags) } #define INSTRUCTION(func) \ diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a01413113b..112db1ad0f 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -27,6 +27,7 @@ #include "qemu/log.h" #include "qemu/bitops.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -37,6 +38,11 @@ #define LOG_DIS(str, ...) \ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->pc, ## __VA_ARGS__) =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + typedef struct DisasContext { TranslationBlock *tb; target_ulong pc; diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 4b0db7b7bd..909b12818d 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -77,7 +77,8 @@ typedef struct { } u; } DisasCompare; =20 -#define DISAS_EXCP 4 +/* is_jmp field values */ +#define DISAS_EXCP DISAS_TARGET_0 =20 #ifdef DEBUG_INLINE_BRANCHES static uint64_t inline_branch_hit[CC_OP_MAX]; diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 8f30cff932..6c094d59d7 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -16,6 +16,7 @@ #include "tcg-op.h" #include "qemu/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -45,9 +46,13 @@ typedef struct DisasContext { #define IS_USER(s) 1 #endif =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ /* These instructions trap after executing, so defer them until after the conditional executions state has been updated. */ -#define DISAS_SYSCALL 5 +#define DISAS_SYSCALL DISAS_TARGET_3 =20 static TCGv_env cpu_env; static TCGv_i32 cpu_R[32]; diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index f3f0ff589c..d7bf07e8e6 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -38,6 +38,7 @@ #include "sysemu/sysemu.h" #include "exec/cpu_ldst.h" #include "exec/semihost.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -46,6 +47,9 @@ #include "exec/log.h" =20 =20 +/* is_jmp field values */ +#define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically= */ + typedef struct DisasContext { const XtensaConfig *config; TranslationBlock *tb; --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714581713177.11920295970913; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1QHcEjTLfMJkurWFMJ47TbFcFe8SFh914sj8uv7xMjI=; b=SofYr54nbQCV9eS2oWNzTNAYVRZ26dCZjaHxVYWWKjaPDKn4ijjXWS1ZXHqrovUKqa Hvt0PMafPddB+nd1GkLSMwcMnYJ+iShsL2JO7tWfKJe+Ih7/y9SLsqgEd5ErFZQzUElq i+b6nswquSptT6NDSUTqjHrUZzFcSqQWEccrA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1QHcEjTLfMJkurWFMJ47TbFcFe8SFh914sj8uv7xMjI=; b=gBfTnW0MqAUrL9lRLQZ2chlkFLtYEfGgwxe+Ohap6thveDeZq3lTFnIgz4dumgtc/P xy+GUI9f/07iN5GdWdPCtgqTxgpl7ko+//itRxE5iLs5q6tcBSfKxqlDD24EPZSr3ZaK Wm30hiBALA8/ZFCXe5qDGy997vgpYSV2MbBO/YTf62XJuijJYyyEOKaOTxtEzfnWLzAv WPhBg9tHkqydzkRPLaUFi9jaX2/TsBOM4jlLzqNQvqnOhGoUavIh5qMrpHca91/QrRPV sI25crqFlZocWN4bnW4QKChLvWPRrGu012m+87ScGZ7DOR48DxfGqcxUvLeFZHS9p6mY J81Q== X-Gm-Message-State: AHPjjUiIPuU07hCuJVrYJdkCg9qS2+xl0/pZJK2q5+XAViD8rf8IUD5H DcIwUM9qISKaX9ZJb+GMTA== X-Google-Smtp-Source: ADKCNb4S7XhQ9jn9INySl5t7PFFrCW4IbZkG7YqWrkOVzuJUMoQJ6FJRIcS7D6wzFi26hHSXrDW2cQ== X-Received: by 10.99.109.142 with SMTP id i136mr8071762pgc.353.1504713981117; Wed, 06 Sep 2017 09:06:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:45 -0700 Message-Id: <20170906160612.22769-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PULL 05/32] target/arm: Delay check for magic kernel page X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson There's nothing magic about the exception that we generate in order to execute the magic kernel page. We can and should allow gdb to set a breakpoint at this location. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0c39c2b996..746193eebc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11968,17 +11968,6 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) 0); num_insns++; =20 -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >=3D 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp =3D DISAS_NORETURN; - break; - } -#endif - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { @@ -12010,6 +11999,17 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) gen_io_start(); } =20 +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >=3D 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->is_jmp =3D DISAS_NORETURN; + break; + } +#endif + if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714265639670.3801846468647; Wed, 6 Sep 2017 09:11:05 -0700 (PDT) Received: from localhost ([::1]:36973 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcuu-0003dj-FE for importer@patchew.org; Wed, 06 Sep 2017 12:11:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41578) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqP-0008Mb-NW for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqO-0001hB-3O for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:25 -0400 Received: from mail-pg0-x229.google.com ([2607:f8b0:400e:c05::229]:37870) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqN-0001gn-R4 for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:24 -0400 Received: by mail-pg0-x229.google.com with SMTP id d8so15974014pgt.4 for ; Wed, 06 Sep 2017 09:06:23 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R62/TouQaAsAwTFblPipbaD9zB1SKMXzhPWYt2bTtDQ=; b=aabH3fkfUYAsgy0ADf21qgP0VeVLYh4acSwqNWnLDP4uH0Qko4XonddyxNLaqFBRWx O4i1BEWQAPodQXYoiA5YVdDSLhnCCWEhphNo9Zkjma9SbwiFjHZ8SlizVHaqD14sRTcn uSYOp0NttRFBp6sJ+tijeI84Gy5J3zs0j7exw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R62/TouQaAsAwTFblPipbaD9zB1SKMXzhPWYt2bTtDQ=; b=WhIQlQqgWc/DyEmKp5ulT6owpeT8V+XN9WV5hKF4eNKaZxipSNDWICc157ipXPIkDI 1DSh7B+RBrwTyJE8KmP7Xz0AMOhW703bFUR2GrjJYp9gbmrUzfSettZbmi6ocvppgc5V m9iUMkcDI2qEimBlQu0N8EyhXYbRcACmErzfiU/93Xx0TCppZ/4vKVDw+azhpnNJYSTW rtcSNhtZSuICg+9cxUx7QpkqLgz9ofjDVHDXmUPhV4DBq5nKTwrEDudw/9qyzksAzYA6 aNJRgzbKZzI+dL7pvWyKG4IfIsx4KDWXiXD4IDEMrZXiPuPHFzOltVcDv2uNQYSdAMyM NJAw== X-Gm-Message-State: AHPjjUjdow4VYFlxn7w8ealy8IL8axnoQMH64nKWRoCskbLQtdOQRKgQ bDFX1+Ut/XxuqoAXBVmI7Q== X-Google-Smtp-Source: ADKCNb6xEgj9vjQ9h1pbonaEngW9HkjJK1+Z3w8CmoFrSRSLXuUTqxhZOAk+DO2smRx35aZcz8ey0g== X-Received: by 10.101.66.139 with SMTP id j11mr8237803pgp.132.1504713982443; Wed, 06 Sep 2017 09:06:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:46 -0700 Message-Id: <20170906160612.22769-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::229 Subject: [Qemu-devel] [PULL 06/32] tcg: Add generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002073981.22386.9870422422367410100.stgit@frigg.lan> [rth: Moved max_insns adjustment from tb_start to init_disas_context. Removed pc_next return from translate_insn. Removed tcg_check_temp_count from generic loop. Moved gen_io_end to exactly match gen_io_start. Use qemu_log instead of error_report for temporary leaks. Moved TB size/icount assignments before disas_log.] Signed-off-by: Richard Henderson --- include/exec/translator.h | 104 ++++++++++++++++++++++++++++++++++ accel/tcg/translator.c | 138 ++++++++++++++++++++++++++++++++++++++++++= ++++ accel/tcg/Makefile.objs | 1 + 3 files changed, 243 insertions(+) create mode 100644 accel/tcg/translator.c diff --git a/include/exec/translator.h b/include/exec/translator.h index b51b8f8a4e..e2dc2a04ae 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -10,6 +10,19 @@ #ifndef EXEC__TRANSLATOR_H #define EXEC__TRANSLATOR_H =20 +/* + * Include this header from a target-specific file, and add a + * + * DisasContextBase base; + * + * member in your target-specific DisasContext. + */ + + +#include "exec/exec-all.h" +#include "tcg/tcg.h" + + /** * DisasJumpType: * @DISAS_NEXT: Next instruction in program order. @@ -37,4 +50,95 @@ typedef enum DisasJumpType { DISAS_TARGET_11, } DisasJumpType; =20 +/** + * DisasContextBase: + * @tb: Translation block for this disassembly. + * @pc_first: Address of first guest instruction in this TB. + * @pc_next: Address of next guest instruction in this TB (current during + * disassembly). + * @is_jmp: What instruction to disassemble next. + * @num_insns: Number of translated instructions (including current). + * @singlestep_enabled: "Hardware" single stepping enabled. + * + * Architecture-agnostic disassembly context. + */ +typedef struct DisasContextBase { + TranslationBlock *tb; + target_ulong pc_first; + target_ulong pc_next; + DisasJumpType is_jmp; + unsigned int num_insns; + bool singlestep_enabled; +} DisasContextBase; + +/** + * TranslatorOps: + * @init_disas_context: + * Initialize the target-specific portions of DisasContext struct. + * The generic DisasContextBase has already been initialized. + * Return max_insns, modified as necessary by db->tb->flags. + * + * @tb_start: + * Emit any code required before the start of the main loop, + * after the generic gen_tb_start(). + * + * @insn_start: + * Emit the tcg_gen_insn_start opcode. + * + * @breakpoint_check: + * When called, the breakpoint has already been checked to match the = PC, + * but the target may decide the breakpoint missed the address + * (e.g., due to conditions encoded in their flags). Return true to + * indicate that the breakpoint did hit, in which case no more breakp= oints + * are checked. If the breakpoint did hit, emit any code required to + * signal the exception, and set db->is_jmp as necessary to terminate + * the main loop. + * + * @translate_insn: + * Disassemble one instruction and set db->pc_next for the start + * of the following instruction. Set db->is_jmp as necessary to + * terminate the main loop. + * + * @tb_stop: + * Emit any opcodes required to exit the TB, based on db->is_jmp. + * + * @disas_log: + * Print instruction disassembly to log. + */ +typedef struct TranslatorOps { + int (*init_disas_context)(DisasContextBase *db, CPUState *cpu, + int max_insns); + void (*tb_start)(DisasContextBase *db, CPUState *cpu); + void (*insn_start)(DisasContextBase *db, CPUState *cpu); + bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu, + const CPUBreakpoint *bp); + void (*translate_insn)(DisasContextBase *db, CPUState *cpu); + void (*tb_stop)(DisasContextBase *db, CPUState *cpu); + void (*disas_log)(const DisasContextBase *db, CPUState *cpu); +} TranslatorOps; + +/** + * translator_loop: + * @ops: Target-specific operations. + * @db: Disassembly context. + * @cpu: Target vCPU. + * @tb: Translation block. + * + * Generic translator loop. + * + * Translation will stop in the following cases (in order): + * - When is_jmp set by #TranslatorOps::breakpoint_check. + * - set to DISAS_TOO_MANY exits after translating one more insn + * - set to any other value than DISAS_NEXT exits immediately. + * - When is_jmp set by #TranslatorOps::translate_insn. + * - set to any value other than DISAS_NEXT exits immediately. + * - When the TCG operation buffer is full. + * - When single-stepping is enabled (system-wide or on the current vCPU). + * - When too many instructions have been translated. + */ +void translator_loop(const TranslatorOps *ops, DisasContextBase *db, + CPUState *cpu, TranslationBlock *tb); + +void translator_loop_temp_check(DisasContextBase *db); + #endif /* EXEC__TRANSLATOR_H */ diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c new file mode 100644 index 0000000000..afa3af478a --- /dev/null +++ b/accel/tcg/translator.c @@ -0,0 +1,138 @@ +/* + * Generic intermediate code generation. + * + * Copyright (C) 2016-2017 Llu=C3=ADs Vilanova + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "tcg/tcg.h" +#include "tcg/tcg-op.h" +#include "exec/exec-all.h" +#include "exec/gen-icount.h" +#include "exec/log.h" +#include "exec/translator.h" + +/* Pairs with tcg_clear_temp_count. + To be called by #TranslatorOps.{translate_insn,tb_stop} if + (1) the target is sufficiently clean to support reporting, + (2) as and when all temporaries are known to be consumed. + For most targets, (2) is at the end of translate_insn. */ +void translator_loop_temp_check(DisasContextBase *db) +{ + if (tcg_check_temp_count()) { + qemu_log("warning: TCG temporary leaks before " + TARGET_FMT_lx "\n", db->pc_next); + } +} + +void translator_loop(const TranslatorOps *ops, DisasContextBase *db, + CPUState *cpu, TranslationBlock *tb) +{ + int max_insns; + + /* Initialize DisasContext */ + db->tb =3D tb; + db->pc_first =3D tb->pc; + db->pc_next =3D db->pc_first; + db->is_jmp =3D DISAS_NEXT; + db->num_insns =3D 0; + db->singlestep_enabled =3D cpu->singlestep_enabled; + + /* Instruction counting */ + max_insns =3D db->tb->cflags & CF_COUNT_MASK; + if (max_insns =3D=3D 0) { + max_insns =3D CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns =3D TCG_MAX_INSNS; + } + if (db->singlestep_enabled || singlestep) { + max_insns =3D 1; + } + + max_insns =3D ops->init_disas_context(db, cpu, max_insns); + tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ + + /* Reset the temp count so that we can identify leaks */ + tcg_clear_temp_count(); + + /* Start translating. */ + gen_tb_start(db->tb); + ops->tb_start(db, cpu); + tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ + + while (true) { + db->num_insns++; + ops->insn_start(db, cpu); + tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit = */ + + /* Pass breakpoint hits to target for further processing */ + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (bp->pc =3D=3D db->pc_next) { + if (ops->breakpoint_check(db, cpu, bp)) { + break; + } + } + } + /* The breakpoint_check hook may use DISAS_TOO_MANY to indicate + that only one more instruction is to be executed. Otherwise + it should use DISAS_NORETURN when generating an exception, + but may use a DISAS_TARGET_* value for Something Else. */ + if (db->is_jmp > DISAS_TOO_MANY) { + break; + } + } + + /* Disassemble one instruction. The translate_insn hook should + update db->pc_next and db->is_jmp to indicate what should be + done next -- either exiting this loop or locate the start of + the next instruction. */ + if (db->num_insns =3D=3D max_insns && (db->tb->cflags & CF_LAST_IO= )) { + /* Accept I/O on the last instruction. */ + gen_io_start(); + ops->translate_insn(db, cpu); + gen_io_end(); + } else { + ops->translate_insn(db, cpu); + } + + /* Stop translation if translate_insn so indicated. */ + if (db->is_jmp !=3D DISAS_NEXT) { + break; + } + + /* Stop translation if the output buffer is full, + or we have executed all of the allowed instructions. */ + if (tcg_op_buf_full() || db->num_insns >=3D max_insns) { + db->is_jmp =3D DISAS_TOO_MANY; + break; + } + } + + /* Emit code to exit the TB, as indicated by db->is_jmp. */ + ops->tb_stop(db, cpu); + gen_tb_end(db->tb, db->num_insns); + + /* The disas_log hook may use these values rather than recompute. */ + db->tb->size =3D db->pc_next - db->pc_first; + db->tb->icount =3D db->num_insns; + +#ifdef DEBUG_DISAS + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) + && qemu_log_in_addr_range(db->pc_first)) { + qemu_log_lock(); + qemu_log("----------------\n"); + ops->disas_log(db, cpu); + qemu_log("\n"); + qemu_log_unlock(); + } +#endif +} diff --git a/accel/tcg/Makefile.objs b/accel/tcg/Makefile.objs index 70cd474c01..22642e6f75 100644 --- a/accel/tcg/Makefile.objs +++ b/accel/tcg/Makefile.objs @@ -1,3 +1,4 @@ obj-$(CONFIG_SOFTMMU) +=3D tcg-all.o obj-$(CONFIG_SOFTMMU) +=3D cputlb.o obj-y +=3D cpu-exec.o cpu-exec-common.o translate-all.o +obj-y +=3D translator.o --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714605096381.72359610318995; Wed, 6 Sep 2017 09:16:45 -0700 (PDT) Received: from localhost ([::1]:36996 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpd0N-0000CR-SO for importer@patchew.org; Wed, 06 Sep 2017 12:16:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41659) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqX-0008SD-7w for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqP-0001kY-OJ for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:33 -0400 Received: from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:37870) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqP-0001ie-Ew for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:25 -0400 Received: by mail-pg0-x22c.google.com with SMTP id d8so15974157pgt.4 for ; Wed, 06 Sep 2017 09:06:25 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cXA05z5fG9qfN0kUotbukGjmdFLQPzYcmOBDIAbbPvM=; b=D5kqiBHk1MHowei7daC310KcVMEG2CuSjqOCPwdaRsaPVYNhKrdNZzA6X0HGMA2UOt cvaN80pTcem79OD8K1e4vSj5IAysv7aYVUTkNWglSQpLDiM/c1o2wZj2QLLBncfXFvZl 6W9SFjT7HBPqWXA+6oEHt4vbgud2vw/J4ZJcE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cXA05z5fG9qfN0kUotbukGjmdFLQPzYcmOBDIAbbPvM=; b=PppTtlPekJWidrkt27WEAuwUkAk1yG8A2LgkdzMuaek0vZO9xbeWaDxZiTMj3Zcrxq Ab+FYX0gZLNUwQmTKS2NCRptpD8Ky8tsDLswFUTy3o9OR1sJBJS0MNL1glnyhii4XBi2 I+/+qFbtr3D0qEENGMmY9EwlapHYKidJyBICV+9wpJx8CXZ8ZP3AAQH3MTpk9V5l9kS2 GXqNLNlj8DDLE1LiZo5vsYdR5MRXgCKKV7gIzClKKatIUvbmQZaM6As9NMbi9SSFTC0q 37bIaEKJ3MPl7bQqgwdkQbryjylFOxngIQFSZ8e3bb8LghsnM983AhE5t4t4pl+dPdCV gJuw== X-Gm-Message-State: AHPjjUgjjmEmLl1fMlmc8DLTOoqWPm7UprGjqHwl5zeFYRdizYPEQ84m OzEBlP0zivKiqncf/fr91A== X-Google-Smtp-Source: ADKCNb7dDu367SwwgxtV6np56U30dIJ3lAb++fLl74idTS9ic7b2tlWU7e+kSTMKYENv+cTtDulT+g== X-Received: by 10.99.110.141 with SMTP id j135mr8396746pgc.242.1504713983821; Wed, 06 Sep 2017 09:06:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:47 -0700 Message-Id: <20170906160612.22769-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PULL 07/32] target/i386: [tcg] Port to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002098212.22386.17313318023406046314.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 140 ++++++++++++++++++++++++--------------------= ---- 1 file changed, 69 insertions(+), 71 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index a0d8788c57..3a3d91c4d7 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -95,6 +95,8 @@ static int x86_64_hregs; #endif =20 typedef struct DisasContext { + DisasContextBase base; + /* current insn context */ int override; /* -1 if no override */ int prefix; @@ -102,8 +104,6 @@ typedef struct DisasContext { TCGMemOp dflag; target_ulong pc_start; target_ulong pc; /* pc =3D eip + cs_base */ - int is_jmp; /* 1 =3D means jump (stop translation), 2 means CPU - static state change (stop translation) */ /* current block context */ target_ulong cs_base; /* base of CS segment */ int pe; /* protected mode */ @@ -124,12 +124,10 @@ typedef struct DisasContext { int cpl; int iopl; int tf; /* TF cpu flag */ - int singlestep_enabled; /* "hardware" single step enabled */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ uint64_t flags; /* all execution flags */ - struct TranslationBlock *tb; int popl_esp_hack; /* for correct popl with esp base handling */ int rip_offset; /* only used in x86_64, but left for simplicity */ int cpuid_features; @@ -1119,7 +1117,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_po= rt, int ot) =20 static inline void gen_ins(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_EDI(s); @@ -1134,14 +1132,14 @@ static inline void gen_ins(DisasContext *s, TCGMemO= p ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } =20 static inline void gen_outs(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_ESI(s); @@ -1154,7 +1152,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp= ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_ESI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } @@ -2137,7 +2135,7 @@ static inline int insn_const_size(TCGMemOp ot) static inline bool use_goto_tb(DisasContext *s, target_ulong pc) { #ifndef CONFIG_USER_ONLY - return (pc & TARGET_PAGE_MASK) =3D=3D (s->tb->pc & TARGET_PAGE_MASK) || + return (pc & TARGET_PAGE_MASK) =3D=3D (s->base.tb->pc & TARGET_PAGE_MA= SK) || (pc & TARGET_PAGE_MASK) =3D=3D (s->pc_start & TARGET_PAGE_MASK); #else return true; @@ -2152,8 +2150,8 @@ static inline void gen_goto_tb(DisasContext *s, int t= b_num, target_ulong eip) /* jump to same page: we can use a direct jump */ tcg_gen_goto_tb(tb_num); gen_jmp_im(eip); - tcg_gen_exit_tb((uintptr_t)s->tb + tb_num); - s->is_jmp =3D DISAS_NORETURN; + tcg_gen_exit_tb((uintptr_t)s->base.tb + tb_num); + s->base.is_jmp =3D DISAS_NORETURN; } else { /* jump to another page */ gen_jmp_im(eip); @@ -2244,12 +2242,12 @@ static void gen_movl_seg_T0(DisasContext *s, int se= g_reg) stop as a special handling must be done to disable hardware interrupts for the next instruction */ if (seg_reg =3D=3D R_SS || (s->code32 && seg_reg < R_FS)) { - s->is_jmp =3D DISAS_TOO_MANY; + s->base.is_jmp =3D DISAS_TOO_MANY; } } else { gen_op_movl_seg_T0_vm(seg_reg); if (seg_reg =3D=3D R_SS) { - s->is_jmp =3D DISAS_TOO_MANY; + s->base.is_jmp =3D DISAS_TOO_MANY; } } } @@ -2422,7 +2420,7 @@ static void gen_exception(DisasContext *s, int trapno= , target_ulong cur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 /* Generate #UD for the current instruction. The assumption here is that @@ -2460,7 +2458,7 @@ static void gen_interrupt(DisasContext *s, int intno, gen_jmp_im(cur_eip); gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), tcg_const_i32(next_eip - cur_eip)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_debug(DisasContext *s, target_ulong cur_eip) @@ -2468,7 +2466,7 @@ static void gen_debug(DisasContext *s, target_ulong c= ur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_debug(cpu_env); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_set_hflag(DisasContext *s, uint32_t mask) @@ -2524,10 +2522,10 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bo= ol recheck_tf, TCGv jr) gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK); } =20 - if (s->tb->flags & HF_RF_MASK) { + if (s->base.tb->flags & HF_RF_MASK) { gen_helper_reset_rf(cpu_env); } - if (s->singlestep_enabled) { + if (s->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else if (recheck_tf) { gen_helper_rechecking_single_step(cpu_env); @@ -2543,7 +2541,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool= recheck_tf, TCGv jr) } else { tcg_gen_exit_tb(0); } - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static inline void @@ -4417,7 +4415,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, } } =20 -/* convert one instruction. s->is_jmp is set if the translation must +/* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, target_ulong pc_start) @@ -5377,7 +5375,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_movl_seg_T0(s, reg); gen_pop_update(s, ot); /* Note that reg =3D=3D R_SS in gen_movl_seg_T0 always sets is_jmp= . */ - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); if (reg =3D=3D R_SS) { s->tf =3D 0; @@ -5392,7 +5390,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, ot =3D gen_pop_T0(s); gen_movl_seg_T0(s, (b >> 3) & 7); gen_pop_update(s, ot); - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -5443,7 +5441,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_movl_seg_T0(s, reg); /* Note that reg =3D=3D R_SS in gen_movl_seg_T0 always sets is_jmp= . */ - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); if (reg =3D=3D R_SS) { s->tf =3D 0; @@ -5652,7 +5650,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_movl_seg_T0(s, op); /* then put the data */ gen_op_mov_reg_v(ot, reg, cpu_T1); - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -6308,7 +6306,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_ins(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6323,7 +6321,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base= ); } else { gen_outs(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6339,14 +6337,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, tcg_gen_movi_tl(cpu_T0, val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6360,14 +6358,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); =20 - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6378,14 +6376,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6398,14 +6396,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); =20 - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6944,7 +6942,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } break; case 0x9b: /* fwait */ @@ -7113,11 +7111,11 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, case 0x131: /* rdtsc */ gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtsc(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7189,7 +7187,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } break; case 0x100: @@ -7372,7 +7370,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), tcg_const_i32(s->pc - pc_start)); tcg_gen_exit_tb(0); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; break; =20 case 0xd9: /* VMMCALL */ @@ -7572,11 +7570,11 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, } gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtscp(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7941,24 +7939,24 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); if (b & 2) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_op_mov_v_reg(ot, cpu_T0, rm); gen_helper_write_crN(cpu_env, tcg_const_i32(reg), cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_read_crN(cpu_T0, cpu_env, tcg_const_i32(reg= )); gen_op_mov_reg_v(ot, rm, cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } @@ -8384,15 +8382,13 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) { CPUX86State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; - target_ulong pc_ptr; uint32_t flags; - target_ulong pc_start; target_ulong cs_base; int num_insns; int max_insns; =20 /* generate intermediate code */ - pc_start =3D tb->pc; + dc->base.pc_first =3D tb->pc; cs_base =3D tb->cs_base; flags =3D tb->flags; =20 @@ -8405,11 +8401,11 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) dc->cpl =3D (flags >> HF_CPL_SHIFT) & 3; dc->iopl =3D (flags >> IOPL_SHIFT) & 3; dc->tf =3D (flags >> TF_SHIFT) & 1; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; dc->cc_op =3D CC_OP_DYNAMIC; dc->cc_op_dirty =3D false; dc->cs_base =3D cs_base; - dc->tb =3D tb; + dc->base.tb =3D tb; dc->popl_esp_hack =3D 0; /* select memory access functions */ dc->mem_index =3D 0; @@ -8459,8 +8455,8 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) cpu_ptr1 =3D tcg_temp_new_ptr(); cpu_cc_srcT =3D tcg_temp_local_new(); =20 - dc->is_jmp =3D DISAS_NEXT; - pc_ptr =3D pc_start; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.pc_next =3D dc->base.pc_first; num_insns =3D 0; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { @@ -8472,37 +8468,38 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) =20 gen_tb_start(tb); for(;;) { - tcg_gen_insn_start(pc_ptr, dc->cc_op); + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); num_insns++; =20 /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cs, pc_ptr, + if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY))) { - gen_debug(dc, pc_ptr - dc->cs_base); + gen_debug(dc, dc->base.pc_next - dc->cs_base); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - pc_ptr +=3D 1; + dc->base.pc_next +=3D 1; goto done_generating; } if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } =20 - pc_ptr =3D disas_insn(env, dc, pc_ptr); + dc->base.pc_next =3D disas_insn(env, dc, dc->base.pc_next); /* stop translation if indicated */ - if (dc->is_jmp) + if (dc->base.is_jmp) { break; + } /* if single step mode, we generate only one instruction and generate an exception */ /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear the flag and abort the translation to give the irqs a change to be happen */ - if (dc->tf || dc->singlestep_enabled || + if (dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } @@ -8513,23 +8510,23 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) because an exception hasn't stopped this code. */ if ((tb->cflags & CF_USE_ICOUNT) - && ((pc_ptr & TARGET_PAGE_MASK) - !=3D ((pc_ptr + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MA= SK) - || (pc_ptr & ~TARGET_PAGE_MASK) =3D=3D 0)) { - gen_jmp_im(pc_ptr - dc->cs_base); + && ((dc->base.pc_next & TARGET_PAGE_MASK) + !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARG= ET_PAGE_MASK) + || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || - (pc_ptr - pc_start) >=3D (TARGET_PAGE_SIZE - 32) || + (dc->base.pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE = - 32) || num_insns >=3D max_insns) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } if (singlestep) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } @@ -8541,24 +8538,25 @@ done_generating: =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { + && qemu_log_in_addr_range(dc->base.pc_first)) { int disas_flags; qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); #ifdef TARGET_X86_64 if (dc->code64) disas_flags =3D 2; else #endif disas_flags =3D !dc->code32; - log_target_disas(cs, pc_start, pc_ptr - pc_start, disas_flags); + log_target_disas(cs, dc->base.pc_first, dc->base.pc_next - dc->bas= e.pc_first, + disas_flags); qemu_log("\n"); qemu_log_unlock(); } #endif =20 - tb->size =3D pc_ptr - pc_start; + tb->size =3D dc->base.pc_next - dc->base.pc_first; tb->icount =3D num_insns; } =20 --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714267450549.0615902923461; Wed, 6 Sep 2017 09:11:07 -0700 (PDT) Received: from localhost ([::1]:36974 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcuw-0003ep-8k for importer@patchew.org; Wed, 06 Sep 2017 12:11:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41658) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqX-0008SC-7u for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqQ-0001p8-WD for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:33 -0400 Received: from mail-pg0-x231.google.com ([2607:f8b0:400e:c05::231]:33605) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqQ-0001oG-NQ for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:26 -0400 Received: by mail-pg0-x231.google.com with SMTP id t3so16078080pgt.0 for ; Wed, 06 Sep 2017 09:06:26 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0yLW7ctcPD/DWG7PrJMW3lLrukj18jAqXKN1J9zeHP8=; b=j6epNIpBJPws696wzHJeQSNm0013QBV4JxNZ4PSB0lTNEJGYSMq9js8R/Ski8n1ltQ ocunFyDXZLNU1I9gA7oaBbphGu3we0zmbb6FCvt5fUuYeDghQdhNGN22WEmrzGpdbFGw svh44ahdhoswWEtlZmSi22flB+6rUqT5F5vsg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0yLW7ctcPD/DWG7PrJMW3lLrukj18jAqXKN1J9zeHP8=; b=lz7DLUwddkUOULRaMCMVIECUyoNGu0tQBABdDdUDTzHlav+LEZRl3Bjy3sc4ejD+sR DmdfWO04dIK4SVzXeT8iYJH9rWPTFimV3tDaysGzCT0VOBcbkqIhuqbv2e1q+AtJ0PD3 n468elWw98uzwHSjOKuQiJkkXO2C9OCbspFah9tYDxMCj0Xk8RZrgX460JdFP6gHTeQr kHN9iMc6Y52yz1BEgWA2ywRMLxLfW8AFajReV468pmvmiUkUkaRfXok+y+aBUrTq2fSW E2kDBV6ESqfp2g07RxkGp0EQvONfshYJpxmoGqcEgyNQEwFJWn9ky8DF/bKvNDuj5hZ1 ho7Q== X-Gm-Message-State: AHPjjUhxxvvKuUD5PimUK1iZa3V/deFIx6a8nR5vLHAeFxOAnho6QKND ZsGb5qrEsHWMIQSKkHQupQ== X-Google-Smtp-Source: ADKCNb4aMrf5UWcX8z4WvPP0srlrpSR5Hoi14MGmnxTRApX2oZFz4Z6bZvUKCC6N3HdLL6JfHSGu4g== X-Received: by 10.99.143.89 with SMTP id r25mr8067193pgn.224.1504713985475; Wed, 06 Sep 2017 09:06:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:48 -0700 Message-Id: <20170906160612.22769-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::231 Subject: [Qemu-devel] [PULL 08/32] target/i386: [tcg] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002122448.22386.16854673576827449259.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson --- target/i386/translate.c | 46 +++++++++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 3a3d91c4d7..4281e9bc56 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8377,20 +8377,13 @@ void tcg_x86_init(void) } } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cpu, + int max_insns) { - CPUX86State *env =3D cs->env_ptr; - DisasContext dc1, *dc =3D &dc1; - uint32_t flags; - target_ulong cs_base; - int num_insns; - int max_insns; - - /* generate intermediate code */ - dc->base.pc_first =3D tb->pc; - cs_base =3D tb->cs_base; - flags =3D tb->flags; + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUX86State *env =3D cpu->env_ptr; + uint32_t flags =3D dc->base.tb->flags; + target_ulong cs_base =3D dc->base.tb->cs_base; =20 dc->pe =3D (flags >> HF_PE_SHIFT) & 1; dc->code32 =3D (flags >> HF_CS32_SHIFT) & 1; @@ -8401,11 +8394,9 @@ void gen_intermediate_code(CPUState *cs, Translation= Block *tb) dc->cpl =3D (flags >> HF_CPL_SHIFT) & 3; dc->iopl =3D (flags >> IOPL_SHIFT) & 3; dc->tf =3D (flags >> TF_SHIFT) & 1; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; dc->cc_op =3D CC_OP_DYNAMIC; dc->cc_op_dirty =3D false; dc->cs_base =3D cs_base; - dc->base.tb =3D tb; dc->popl_esp_hack =3D 0; /* select memory access functions */ dc->mem_index =3D 0; @@ -8423,7 +8414,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) dc->code64 =3D (flags >> HF_CS64_SHIFT) & 1; #endif dc->flags =3D flags; - dc->jmp_opt =3D !(dc->tf || cs->singlestep_enabled || + dc->jmp_opt =3D !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because rep movsS instructions are execured with different paths @@ -8435,7 +8426,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) record/replay modes and there will always be an additional step for ecx=3D0 when icount is enabled. */ - dc->repz_opt =3D !dc->jmp_opt && !(tb->cflags & CF_USE_ICOUNT); + dc->repz_opt =3D !dc->jmp_opt && !(dc->base.tb->cflags & CF_USE_ICOUNT= ); #if 0 /* check addseg logic */ if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) @@ -8455,9 +8446,24 @@ void gen_intermediate_code(CPUState *cs, Translation= Block *tb) cpu_ptr1 =3D tcg_temp_new_ptr(); cpu_cc_srcT =3D tcg_temp_local_new(); =20 + return max_insns; +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + CPUX86State *env =3D cs->env_ptr; + DisasContext dc1, *dc =3D &dc1; + int num_insns; + int max_insns; + + /* generate intermediate code */ + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + dc->base.tb =3D tb; dc->base.is_jmp =3D DISAS_NEXT; + dc->base.pc_first =3D tb->pc; dc->base.pc_next =3D dc->base.pc_first; - num_insns =3D 0; + max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -8465,7 +8471,9 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + max_insns =3D i386_tr_init_disas_context(&dc->base, cs, max_insns); =20 + num_insns =3D 0; gen_tb_start(tb); for(;;) { tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); @@ -8498,7 +8506,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) the flag and abort the translation to give the irqs a change to be happen */ if (dc->tf || dc->base.singlestep_enabled || - (flags & HF_INHIBIT_IRQ_MASK)) { + (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rXe4UUaCAEVK2Z3jt3XkW9x0BAsyfuihj6enBy9EZXg=; b=O9PnlgYcA0Bqet83vNuDFW9fqJqa7ytwFMBe/Sb7CRk7UBnPqbUT82sGmRb6UnvSlq ZX1bt8xc9vNumksGxCsFO5nQFlNmxk2gLsK0Dc1GYBJAmH73jAsH0HRdg3s/rw7RN6W0 1rRSmDn9CMxH8RJUvhmNJS3z/CUIPkHDg+1Ls= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rXe4UUaCAEVK2Z3jt3XkW9x0BAsyfuihj6enBy9EZXg=; b=l6E262OAz86Ztgp5fPfGR8ZU2Mfw7p9E1KO2U2z0czg7i1pcFAdB1juU8+BtYD1qTL FDWfAQTHt3kDI3NnCH346dc5eqIW6uR03LWZ2htMkVc4bqxvxEYLxUcvjuktlEjaobUJ BVOdWckqy5DjSi4NOiiN7WLwykwjnHHaW8n2hCFV7hrpCAhNQkktXTpVPwihcUWM+GDv d2Au/LeQXoIJ6gwFLLowm8+nEwpsVZHukfRdVCJjd+jdZUUxszGPlP01XQsqGrS1XntS x4PbDAGjjAEpFMv/8tLHOL4CiakjRhcwMG9r+gWUCr4aRcVJXGwQY15n3LnDJuXI9gym e5LA== X-Gm-Message-State: AHPjjUgqhdocchvi6CWKKJO4cwV2Mmpqgmx/gl3otq4DAIrbHQ0aQ1Do aMAYTzFzMTtj5aI7bfi/DQ== X-Google-Smtp-Source: ADKCNb4tdkDYDdBBZTMLfKNUFKoj64IJ5zEPaZ8DXauL95toTu4V84czqfI4Bu9vOY0dLvuCdEHSWw== X-Received: by 10.98.201.197 with SMTP id l66mr7635419pfk.135.1504713986730; Wed, 06 Sep 2017 09:06:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:49 -0700 Message-Id: <20170906160612.22769-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::232 Subject: [Qemu-devel] [PULL 09/32] target/i386: [tcg] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002146647.22386.13380064201042141261.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 4281e9bc56..b7e5854513 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8449,6 +8449,13 @@ static int i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu, return max_insns; } =20 +static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8476,7 +8483,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) num_insns =3D 0; gen_tb_start(tb); for(;;) { - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); + i386_tr_insn_start(&dc->base, cs); num_insns++; =20 /* If RF is set, suppress an internally generated breakpoint. */ --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714442288402.81574451229596; Wed, 6 Sep 2017 09:14:02 -0700 (PDT) Received: from localhost ([::1]:36984 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcxl-0006MD-3a for importer@patchew.org; Wed, 06 Sep 2017 12:14:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41665) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqX-0008Sd-KS for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqT-0001xj-Lv for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:33 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:36480) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqT-0001tQ-GT for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:29 -0400 Received: by mail-pf0-x233.google.com with SMTP id e199so13452448pfh.3 for ; Wed, 06 Sep 2017 09:06:29 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JBnESfPgluCNjUoEQc0wVDgPrUzhAwV+Ja6vru/3p1M=; b=kicp4aicUPjK7UYk/jlnG1tj7L73e5Kten9U4b8eUxsggKt1quOQkGr8o5/N9Slr22 tkkaptN1a3eLTnXfsIPmoz4t+B7P4TFhyE9elp9TCn2WmWD8mqpRvd2q/L36G8g2zN6N vZpw8DEZ2T4mNuTXJ9sswMr25k07zceZG7or0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JBnESfPgluCNjUoEQc0wVDgPrUzhAwV+Ja6vru/3p1M=; b=fzlbRiNX4NekHIjnAGdvXbAcoK/bClpnW5ypFRvYwLdGOkOy4F8AIGo7UoaKUWC7Vy qHsaVLIazv7N92J99ywz9Xzyw6C2E2NURax6FKP5JFcjfQANEduYt6RdgyTFON8NJB9u I25G8u7Tx8WG3J/mlTqBYJ0VYDuDJGhf1aJ4pDwJ9ENYvqUoctF7gpzsd+ZoqY9ekfhV 3faPS8kCYty3DUtkAFrATLXb8eA6LoYDlKZ6Y99WjG9h8hSHdZs+H5Qx1Ldis4ZULuJr S3iijYtd473Ahld0FH1tzAVqSy5154BHQMD+cQl0krg9F4Z+8fxMCUf1RT/Eq892wsia OBCQ== X-Gm-Message-State: AHPjjUgMXE8x36ZMSVejXz31TNTjIQ/aVuc6cgU0BP3VPC1WRk3oQHON XAtHzRku2Qy2zMUg7heDQw== X-Google-Smtp-Source: ADKCNb5ClKmw2bA9ZI8FnbdoGRv3I5ZK0oTlYXWGTYZyvi22eLPPBef0WROQ64ql96BMTkChHyhFNA== X-Received: by 10.98.14.213 with SMTP id 82mr8030353pfo.274.1504713988119; Wed, 06 Sep 2017 09:06:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:50 -0700 Message-Id: <20170906160612.22769-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PULL 10/32] target/i386: [tcg] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Message-Id: <150002170871.22386.2172835658104140576.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 46 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index b7e5854513..4d4083fe30 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8456,6 +8456,26 @@ static void i386_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } =20 +static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= pu, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + /* If RF is set, suppress an internally generated breakpoint. */ + int flags =3D dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; + if (bp->flags & flags) { + gen_debug(dc, dc->base.pc_next - dc->cs_base); + dc->base.is_jmp =3D DISAS_NORETURN; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + dc->base.pc_next +=3D 1; + return true; + } else { + return false; + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8486,18 +8506,21 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) i386_tr_insn_start(&dc->base, cs); num_insns++; =20 - /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, - tb->flags & HF_RF_MASK - ? BP_GDB : BP_ANY))) { - gen_debug(dc, dc->base.pc_next - dc->cs_base); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 1; - goto done_generating; + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc =3D=3D dc->base.pc_next) { + if (i386_tr_breakpoint_check(&dc->base, cs, bp)) { + break; + } + } + } + + if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { + break; + } } + if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -8548,7 +8571,6 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) } if (tb->cflags & CF_LAST_IO) gen_io_end(); -done_generating: gen_tb_end(tb, num_insns); =20 #ifdef DEBUG_DISAS --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714426298557.4389773256135; Wed, 6 Sep 2017 09:13:46 -0700 (PDT) Received: from localhost ([::1]:36983 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcxV-00067g-45 for importer@patchew.org; Wed, 06 Sep 2017 12:13:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41696) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqa-0008VA-1D for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqU-0001zM-Vv for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:36 -0400 Received: from mail-pg0-x22b.google.com ([2607:f8b0:400e:c05::22b]:37871) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqU-0001z0-Nv for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:30 -0400 Received: by mail-pg0-x22b.google.com with SMTP id d8so15974594pgt.4 for ; Wed, 06 Sep 2017 09:06:30 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::22b Subject: [Qemu-devel] [PULL 11/32] target/i386: [tcg] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Message-Id: <150002195074.22386.16195894320027075398.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 66 +++++++++++++++++++++++++++++++--------------= ---- 1 file changed, 42 insertions(+), 24 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 4d4083fe30..0f38896f17 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -4417,15 +4417,16 @@ static void gen_sse(CPUX86State *env, DisasContext = *s, int b, =20 /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ -static target_ulong disas_insn(CPUX86State *env, DisasContext *s, - target_ulong pc_start) +static target_ulong disas_insn(DisasContext *s, CPUState *cpu) { + CPUX86State *env =3D cpu->env_ptr; int b, prefixes; int shift; TCGMemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; int rex_w, rex_r; + target_ulong pc_start =3D s->base.pc_next; =20 s->pc_start =3D s->pc =3D pc_start; prefixes =3D 0; @@ -8476,10 +8477,46 @@ static bool i386_tr_breakpoint_check(DisasContextBa= se *dcbase, CPUState *cpu, } } =20 +static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong pc_next =3D disas_insn(dc, cpu); + + if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { + /* if single step mode, we generate only one instruction and + generate an exception */ + /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear + the flag and abort the translation to give the irqs a + chance to happen */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) + && ((dc->base.pc_next & TARGET_PAGE_MASK) + !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) + & TARGET_PAGE_MASK) + || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + /* Do not cross the boundary of the pages in icount mode, + it can cause an exception. Do it only when boundary is + crossed by the first instruction in the block. + If current instruction already crossed the bound - it's ok, + because an exception hasn't stopped this code. + */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else if ((pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE - 32))= { + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + + dc->base.pc_next =3D pc_next; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - CPUX86State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; int num_insns; int max_insns; @@ -8525,39 +8562,20 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_io_start(); } =20 - dc->base.pc_next =3D disas_insn(env, dc, dc->base.pc_next); + i386_tr_translate_insn(&dc->base, cs); /* stop translation if indicated */ if (dc->base.is_jmp) { break; } /* if single step mode, we generate only one instruction and generate an exception */ - /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear - the flag and abort the translation to give the irqs a - change to be happen */ - if (dc->tf || dc->base.singlestep_enabled || - (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); - break; - } - /* Do not cross the boundary of the pages in icount mode, - it can cause an exception. Do it only when boundary is - crossed by the first instruction in the block. - If current instruction already crossed the bound - it's ok, - because an exception hasn't stopped this code. - */ - if ((tb->cflags & CF_USE_ICOUNT) - && ((dc->base.pc_next & TARGET_PAGE_MASK) - !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARG= ET_PAGE_MASK) - || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + if (dc->base.singlestep_enabled) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || - (dc->base.pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE = - 32) || num_insns >=3D max_insns) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714423025289.26934676444796; Wed, 6 Sep 2017 09:13:43 -0700 (PDT) Received: from localhost ([::1]:36981 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcxQ-00064V-If for importer@patchew.org; Wed, 06 Sep 2017 12:13:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41663) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqX-0008SX-Ie for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqW-00021w-Ar for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:33 -0400 Received: from mail-pg0-x22d.google.com ([2607:f8b0:400e:c05::22d]:34479) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqW-00020a-3s for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:32 -0400 Received: by mail-pg0-x22d.google.com with SMTP id q68so157402pgq.1 for ; Wed, 06 Sep 2017 09:06:32 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/hs5DJ5ZOYzeGcPj2CaJWFBYCthdShVyhxl4UMKX3/s=; b=VTv20rXAv/yU273uHMQMIJ4c6Xibi4EyV9LUmMU9j+GYhUqW/5NA+3P0tLtqQYz/KQ TAEIqk/0mPEZKtRKixH5YjRavHPs/NnSMDNaSBHTif1MeoROL38naH6AgJr5X0llg8wF E+1gmcGdO6d4fZWMGSbSFVbVOyaG5s9NChW7c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/hs5DJ5ZOYzeGcPj2CaJWFBYCthdShVyhxl4UMKX3/s=; b=DKtm7Xhy2OD/z0WVLHHZI50+0gk6k4etgJ4/nmPbVbiovGiLK3l+ogPK6uj+5aMp8o d9gm37vbIU+HfS0xRgflmgWNQ3y27FMPNNrGPw8z0itut8l/tGGi3bEeyUA7hofeuVyz x/nyN3v1NcHtmbOzHU1n3Eq7mJNFDBjMGgfG0yATYuKEl/fTio5wMvZB7+lQOaUyssy+ R3pU69L0NFKZkVXMy6F1kC1pHoxNSjzhRCPhuvf/gzp8uNSnjJMdpm52jHtgNUyT4TX6 JNtlq+Pgr/E4SERsHJDZk3cHMNPBhJp3OX8h8Qt/MIHJrPbqNIXHR7A4z9mMgSUNSA81 TeTw== X-Gm-Message-State: AHPjjUg9YIX6CuTnZ70C5T9Ksx7Wqs2p50QQ4UuiAFHC10C/nqjQXmfe hG3Ev9kuWI+JOLkP7tqdmw== X-Google-Smtp-Source: ADKCNb6ZELyvx9oCnZxMuzVBk/TSbDtonY5gWURJtBwxCGqXNu2EIXgz3hvSbkByVOnzRgJWZzifwQ== X-Received: by 10.99.121.194 with SMTP id u185mr8433851pgc.314.1504713990798; Wed, 06 Sep 2017 09:06:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:52 -0700 Message-Id: <20170906160612.22769-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: [Qemu-devel] [PULL 12/32] target/i386: [tcg] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id: <150002219289.22386.17959138704858928730.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 0f38896f17..9872f84a03 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8488,8 +8488,6 @@ static void i386_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cpu) /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear the flag and abort the translation to give the irqs a chance to happen */ - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp =3D DISAS_TOO_MANY; } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) && ((dc->base.pc_next & TARGET_PAGE_MASK) @@ -8502,18 +8500,24 @@ static void i386_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) If current instruction already crossed the bound - it's ok, because an exception hasn't stopped this code. */ - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp =3D DISAS_TOO_MANY; } else if ((pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE - 32))= { - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp =3D DISAS_TOO_MANY; } =20 dc->base.pc_next =3D pc_next; } =20 +static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (dc->base.is_jmp =3D=3D DISAS_TOO_MANY) { + gen_jmp_im(dc->base.pc_next - dc->cs_base); + gen_eob(dc); + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8570,23 +8574,21 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) /* if single step mode, we generate only one instruction and generate an exception */ if (dc->base.singlestep_enabled) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || num_insns >=3D max_insns) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; break; } if (singlestep) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; break; } } + i386_tr_tb_stop(&dc->base, cs); if (tb->cflags & CF_LAST_IO) gen_io_end(); gen_tb_end(tb, num_insns); --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714924907508.15667714043684; Wed, 6 Sep 2017 09:22:04 -0700 (PDT) Received: from localhost ([::1]:37016 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpd5X-0004SL-Q6 for importer@patchew.org; Wed, 06 Sep 2017 12:22:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41754) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqd-00009G-RJ for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqX-00029c-W1 for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:39 -0400 Received: from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:36202) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqX-00027w-QD for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:33 -0400 Received: by mail-pg0-x235.google.com with SMTP id m9so16046038pgd.3 for ; Wed, 06 Sep 2017 09:06:33 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PULL 13/32] target/i386: [tcg] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id: <150002243497.22386.8888053391875656102.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson --- target/i386/translate.c | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 9872f84a03..ad4b2735f4 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8518,6 +8518,21 @@ static void i386_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) } } =20 +static void i386_tr_disas_log(const DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + int disas_flags =3D !dc->code32; + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); +#ifdef TARGET_X86_64 + if (dc->code64) { + disas_flags =3D 2; + } +#endif + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flag= s); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8593,28 +8608,19 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_io_end(); gen_tb_end(tb, num_insns); =20 + tb->size =3D dc->base.pc_next - dc->base.pc_first; + tb->icount =3D num_insns; + #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { - int disas_flags; qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); -#ifdef TARGET_X86_64 - if (dc->code64) - disas_flags =3D 2; - else -#endif - disas_flags =3D !dc->code32; - log_target_disas(cs, dc->base.pc_first, dc->base.pc_next - dc->bas= e.pc_first, - disas_flags); + i386_tr_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } #endif - - tb->size =3D dc->base.pc_next - dc->base.pc_first; - tb->icount =3D num_insns; } =20 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714751477346.7963859842009; Wed, 6 Sep 2017 09:19:11 -0700 (PDT) Received: from localhost ([::1]:37005 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpd2j-0002Cx-SL for importer@patchew.org; Wed, 06 Sep 2017 12:19:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41700) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqa-0008W7-J3 for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqZ-0002BM-7u for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:36 -0400 Received: from mail-pf0-x22c.google.com ([2607:f8b0:400e:c00::22c]:33132) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqY-0002A9-Vs for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:35 -0400 Received: by mail-pf0-x22c.google.com with SMTP id y68so13495970pfd.0 for ; Wed, 06 Sep 2017 09:06:34 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::22c Subject: [Qemu-devel] [PULL 14/32] target/i386: [tcg] Port to generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Tested-by: Emilio G. Cota Message-Id: <150002267714.22386.5095442346868988808.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 106 +++++++++-----------------------------------= ---- 1 file changed, 19 insertions(+), 87 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index ad4b2735f4..de0c989763 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8450,6 +8450,10 @@ static int i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu, return max_insns; } =20 +static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -8469,7 +8473,7 @@ static bool i386_tr_breakpoint_check(DisasContextBase= *dcbase, CPUState *cpu, /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ + the generic logic setting tb->size later does the right thing. = */ dc->base.pc_next +=3D 1; return true; } else { @@ -8533,94 +8537,22 @@ static void i386_tr_disas_log(const DisasContextBas= e *dcbase, log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flag= s); } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) -{ - DisasContext dc1, *dc =3D &dc1; - int num_insns; - int max_insns; - - /* generate intermediate code */ - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - dc->base.tb =3D tb; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.pc_first =3D tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - max_insns =3D i386_tr_init_disas_context(&dc->base, cs, max_insns); - - num_insns =3D 0; - gen_tb_start(tb); - for(;;) { - i386_tr_insn_start(&dc->base, cs); - num_insns++; - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (i386_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - - if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { - break; - } - } - - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - i386_tr_translate_insn(&dc->base, cs); - /* stop translation if indicated */ - if (dc->base.is_jmp) { - break; - } - /* if single step mode, we generate only one instruction and - generate an exception */ - if (dc->base.singlestep_enabled) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - break; - } - /* if too long translation, stop generation too */ - if (tcg_op_buf_full() || - num_insns >=3D max_insns) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - break; - } - if (singlestep) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - break; - } - } - i386_tr_tb_stop(&dc->base, cs); - if (tb->cflags & CF_LAST_IO) - gen_io_end(); - gen_tb_end(tb, num_insns); +static const TranslatorOps i386_tr_ops =3D { + .init_disas_context =3D i386_tr_init_disas_context, + .tb_start =3D i386_tr_tb_start, + .insn_start =3D i386_tr_insn_start, + .breakpoint_check =3D i386_tr_breakpoint_check, + .translate_insn =3D i386_tr_translate_insn, + .tb_stop =3D i386_tr_tb_stop, + .disas_log =3D i386_tr_disas_log, +}; =20 - tb->size =3D dc->base.pc_next - dc->base.pc_first; - tb->icount =3D num_insns; +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc; =20 -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - i386_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif + translator_loop(&i386_tr_ops, &dc.base, cpu, tb); } =20 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504715248397598.6515761710695; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kyTRkJwFuA3Qacic/EBTpNf7SPJB42Dv4aek8t3omQ8=; b=VSm6HNOauVeyX2hUL1azgQk1b75UCuKxGxzYM2a/n+e7PaMM0DEOnKaPN1p5yG6fx9 R5C6CIz2zkgnsB4KO+9Szf1yoXdcbVYX5ZfcfJVuAAyVziaYeQd1K4ip2ynz6yjtqfSi dKbN4cbDC4fqCoMtgt+H+irrvCxRmTzePxrWA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kyTRkJwFuA3Qacic/EBTpNf7SPJB42Dv4aek8t3omQ8=; b=UGup2f756uxxIuxMOyizP0PgD31LX2KogPlMrsl5rRjvyTK6wFLLnuNrh3ib8ch0Uj sZlE8aRUXAXa9YvtngWsgFLLv473NJGTQ2PnbByvAL0q/lcGpsKE26g+hfC3EC+pcYPz kaJYxtXFc8rRuXRDqI+1UH2M3Wbkv/wgJwhhDAL7wbu2mnEq3L1iovxt6Gt+Jj83d4hb l8FuMCr52i6geoTpYmYwjbWfqGG2ISlJzDpQ2dgPis3LQexEpKigHMEWatoE/c+SLnTn ntI4FoAeaSvAXz1cLHSzZBqi1mvUsA0mIQV66zG+M+KrEkoee7Y8O7Tp4ZXy3ZKT1Qiz QqnA== X-Gm-Message-State: AHPjjUhHhyBK4J93OG8Ag+FB5WTTOYbfsStVL1HTF9zuVVjsZu57v3z6 hMzTsXt+rWUpdapaD4DxUA== X-Google-Smtp-Source: ADKCNb6/bBO0OrjWW3frpuiyfDYqwqUW0RyJW4eXMbpYsKiAHVJfC4pl63iMMUnKryxrq2QLRAchKA== X-Received: by 10.99.151.73 with SMTP id d9mr8117818pgo.13.1504713995084; Wed, 06 Sep 2017 09:06:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:55 -0700 Message-Id: <20170906160612.22769-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PULL 15/32] target/arm: [tcg] Port to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002291931.22386.11441154993010495674.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.h | 11 +++-- target/arm/translate-a64.c | 113 ++++++++++++++++++++++-------------------= -- target/arm/translate.c | 117 ++++++++++++++++++++++-------------------= ---- 3 files changed, 120 insertions(+), 121 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 1eb432dc2c..a804ff65ac 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -6,9 +6,10 @@ =20 /* internal defines */ typedef struct DisasContext { + DisasContextBase base; + target_ulong pc; uint32_t insn; - int is_jmp; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; /* The label that will be jumped to when the instruction is skipped. = */ @@ -16,8 +17,6 @@ typedef struct DisasContext { /* Thumb-2 conditional execution bits. */ int condexec_mask; int condexec_cond; - struct TranslationBlock *tb; - int singlestep_enabled; int thumb; int sctlr_b; TCGMemOp be_data; @@ -150,7 +149,8 @@ static void disas_set_insn_syndrome(DisasContext *s, ui= nt32_t syn) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb); +void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, + TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); @@ -159,7 +159,8 @@ static inline void a64_translate_init(void) { } =20 -static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlo= ck *tb) +static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUStat= e *cpu, + TranslationBlock *tb) { } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 881d3c0cbb..f5c678ef25 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -304,7 +304,7 @@ static void gen_exception_internal_insn(DisasContext *s= , int offset, int excp) { gen_a64_set_pc_im(s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -312,7 +312,7 @@ static void gen_exception_insn(DisasContext *s, int off= set, int excp, { gen_a64_set_pc_im(s->pc - offset); gen_exception(excp, syndrome, target_el); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_ss_advance(DisasContext *s) @@ -340,7 +340,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) @@ -348,13 +348,13 @@ static inline bool use_goto_tb(DisasContext *s, int n= , uint64_t dest) /* No direct tb linking with singlestep (either QEMU's or the ARM * debug architecture kind) or deterministic io */ - if (s->singlestep_enabled || s->ss_active || (s->tb->cflags & CF_LAST_= IO)) { + if (s->base.singlestep_enabled || s->ss_active || (s->base.tb->cflags = & CF_LAST_IO)) { return false; } =20 #ifndef CONFIG_USER_ONLY /* Only link tbs from inside the same guest page */ - if ((s->tb->pc & TARGET_PAGE_MASK) !=3D (dest & TARGET_PAGE_MASK)) { + if ((s->base.tb->pc & TARGET_PAGE_MASK) !=3D (dest & TARGET_PAGE_MASK)= ) { return false; } #endif @@ -366,21 +366,21 @@ static inline void gen_goto_tb(DisasContext *s, int n= , uint64_t dest) { TranslationBlock *tb; =20 - tb =3D s->tb; + tb =3D s->base.tb; if (use_goto_tb(s, n, dest)) { tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); tcg_gen_exit_tb((intptr_t)tb + n); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } else { gen_a64_set_pc_im(dest); if (s->ss_active) { gen_step_complete_exception(s); - } else if (s->singlestep_enabled) { + } else if (s->base.singlestep_enabled) { gen_exception_internal(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_pc); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } } } @@ -1331,16 +1331,16 @@ static void handle_hint(DisasContext *s, uint32_t i= nsn, case 0: /* NOP */ return; case 3: /* WFI */ - s->is_jmp =3D DISAS_WFI; + s->base.is_jmp =3D DISAS_WFI; return; case 1: /* YIELD */ if (!parallel_cpus) { - s->is_jmp =3D DISAS_YIELD; + s->base.is_jmp =3D DISAS_YIELD; } return; case 2: /* WFE */ if (!parallel_cpus) { - s->is_jmp =3D DISAS_WFE; + s->base.is_jmp =3D DISAS_WFE; } return; case 4: /* SEV */ @@ -1424,7 +1424,7 @@ static void handle_msr_i(DisasContext *s, uint32_t in= sn, tcg_temp_free_i32(tcg_op); /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ gen_a64_set_pc_im(s->pc); - s->is_jmp =3D (op =3D=3D 0x1f ? DISAS_EXIT : DISAS_JUMP); + s->base.is_jmp =3D (op =3D=3D 0x1f ? DISAS_EXIT : DISAS_JUMP); break; } default: @@ -1559,7 +1559,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, break; } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } =20 @@ -1590,16 +1590,16 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, } } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } } =20 @@ -1789,7 +1789,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) } gen_helper_exception_return(cpu_env); /* Must exit loop to check un-masked IRQs */ - s->is_jmp =3D DISAS_EXIT; + s->base.is_jmp =3D DISAS_EXIT; return; case 5: /* DRPS */ if (rn !=3D 0x1f) { @@ -1803,7 +1803,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) return; } =20 - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; } =20 /* C3.2 Branches, exception generating and system instructions */ @@ -11200,23 +11200,23 @@ static void disas_a64_insn(CPUARMState *env, Disa= sContext *s) free_tmp_a64(s); } =20 -void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, + TranslationBlock *tb) { CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D arm_env_get_cpu(env); - DisasContext dc1, *dc =3D &dc1; - target_ulong pc_start; + DisasContext *dc =3D container_of(dcbase, DisasContext, base); target_ulong next_page_start; - int num_insns; int max_insns; =20 - pc_start =3D tb->pc; + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - dc->tb =3D tb; - - dc->is_jmp =3D DISAS_NEXT; - dc->pc =3D pc_start; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; =20 dc->aarch64 =3D 1; @@ -11227,17 +11227,17 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) !arm_el_is_aa64(env, 3); dc->thumb =3D 0; dc->sctlr_b =3D 0; - dc->be_data =3D ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; + dc->be_data =3D ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; dc->condexec_mask =3D 0; dc->condexec_cond =3D 0; - dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); - dc->tbi0 =3D ARM_TBFLAG_TBI0(tb->flags); - dc->tbi1 =3D ARM_TBFLAG_TBI1(tb->flags); + dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb= ->flags)); + dc->tbi0 =3D ARM_TBFLAG_TBI0(dc->base.tb->flags); + dc->tbi1 =3D ARM_TBFLAG_TBI1(dc->base.tb->flags); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(tb->flags); + dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D cpu->cp_regs; @@ -11258,16 +11258,15 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); + dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex =3D false; dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 init_tmp_a64_array(dc); =20 - next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; + max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -11280,9 +11279,9 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) tcg_clear_temp_count(); =20 do { + dc->base.num_insns++; dc->insn_start_idx =3D tcg_op_buf_count(); tcg_gen_insn_start(dc->pc, 0, 0); - num_insns++; =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; @@ -11292,14 +11291,14 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) gen_a64_set_pc_im(dc->pc); gen_helper_check_breakpoints(cpu_env); /* End the TB early; it likely won't be executed */ - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; } else { gen_exception_internal_insn(dc, 0, EXCP_DEBUG); /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order + included in [dc->base.tb->pc, dc->base.tb->pc += dc->base.tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting - tb->size below does the right thing. */ + dc->base.tb->size below does the right thing. = */ dc->pc +=3D 4; goto done_generating; } @@ -11308,7 +11307,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) } } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { gen_io_start(); } =20 @@ -11323,10 +11322,10 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns =3D=3D 1); + assert(dc->base.num_insns =3D=3D 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; break; } =20 @@ -11342,14 +11341,14 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - } while (!dc->is_jmp && !tcg_op_buf_full() && + } while (!dc->base.is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && !dc->ss_active && dc->pc < next_page_start && - num_insns < max_insns); + dc->base.num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (dc->base.tb->cflags & CF_LAST_IO) { gen_io_end(); } =20 @@ -11359,7 +11358,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) * gen_goto_tb() has already handled emitting the debug exception * (and thus a tb-jump is not possible when singlestepping). */ - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { default: gen_a64_set_pc_im(dc->pc); /* fall through */ @@ -11374,7 +11373,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) break; } } else { - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, dc->pc); break; @@ -11414,20 +11413,20 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) } =20 done_generating: - gen_tb_end(tb, num_insns); + gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(pc_start)) { + qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size =3D dc->pc - pc_start; - tb->icount =3D num_insns; + dc->base.tb->size =3D dc->pc - dc->base.pc_first; + dc->base.tb->icount =3D dc->base.num_insns; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 746193eebc..4db8978a93 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -224,7 +224,7 @@ static void store_reg(DisasContext *s, int reg, TCGv_i3= 2 var) * We choose to ignore [1:0] in ARM mode for all architecture vers= ions. */ tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; } tcg_gen_mov_i32(cpu_R[reg], var); tcg_temp_free_i32(var); @@ -297,7 +297,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_singlestep_exception(DisasContext *s) @@ -321,7 +321,7 @@ static inline bool is_singlestepping(DisasContext *s) * misnamed as it only means "one instruction per TB" and doesn't * affect the code we generate. */ - return s->singlestep_enabled || s->ss_active; + return s->base.singlestep_enabled || s->ss_active; } =20 static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) @@ -930,7 +930,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t = addr) { TCGv_i32 tmp; =20 - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; if (s->thumb !=3D (addr & 1)) { tmp =3D tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, addr & 1); @@ -943,7 +943,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t = addr) /* Set PC and Thumb state from var. var is marked as dead. */ static inline void gen_bx(DisasContext *s, TCGv_i32 var) { - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; tcg_gen_andi_i32(cpu_R[15], var, ~1); tcg_gen_andi_i32(var, var, 1); store_cpu_field(var, thumb); @@ -957,11 +957,11 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 v= ar) static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var) { /* Generate the same code here as for a simple bx, but flag via - * s->is_jmp that we need to do the rest of the work later. + * s->base.is_jmp that we need to do the rest of the work later. */ gen_bx(s, var); if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) { - s->is_jmp =3D DISAS_BX_EXCRET; + s->base.is_jmp =3D DISAS_BX_EXCRET; } } =20 @@ -1161,7 +1161,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) */ s->svc_imm =3D imm16; gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_HVC; + s->base.is_jmp =3D DISAS_HVC; } =20 static inline void gen_smc(DisasContext *s) @@ -1176,7 +1176,7 @@ static inline void gen_smc(DisasContext *s) gen_helper_pre_smc(cpu_env, tmp); tcg_temp_free_i32(tmp); gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_SMC; + s->base.is_jmp =3D DISAS_SMC; } =20 static void gen_exception_internal_insn(DisasContext *s, int offset, int e= xcp) @@ -1184,7 +1184,7 @@ static void gen_exception_internal_insn(DisasContext = *s, int offset, int excp) gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -1193,14 +1193,14 @@ static void gen_exception_insn(DisasContext *s, int= offset, int excp, gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception(excp, syn, target_el); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { tcg_gen_movi_i32(cpu_R[15], s->pc & ~1); - s->is_jmp =3D DISAS_EXIT; + s->base.is_jmp =3D DISAS_EXIT; } =20 static inline void gen_hlt(DisasContext *s, int imm) @@ -4145,7 +4145,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) static inline bool use_goto_tb(DisasContext *s, target_ulong dest) { #ifndef CONFIG_USER_ONLY - return (s->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MASK)= || + return (s->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_= MASK) || ((s->pc - 1) & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MAS= K); #else return true; @@ -4169,12 +4169,12 @@ static void gen_goto_tb(DisasContext *s, int n, tar= get_ulong dest) if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); - tcg_gen_exit_tb((uintptr_t)s->tb + n); + tcg_gen_exit_tb((uintptr_t)s->base.tb + n); } else { gen_set_pc_im(s, dest); gen_goto_ptr(); } - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static inline void gen_jmp (DisasContext *s, uint32_t dest) @@ -4436,7 +4436,7 @@ static void gen_msr_banked(DisasContext *s, int r, in= t sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); tcg_temp_free_i32(tcg_reg); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } =20 static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) @@ -4458,7 +4458,7 @@ static void gen_mrs_banked(DisasContext *s, int r, in= t sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); store_reg(s, rn, tcg_reg); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } =20 /* Store value to PC as for an exception return (ie don't @@ -4482,7 +4482,7 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCG= v_i32 cpsr) gen_helper_cpsr_write_eret(cpu_env, cpsr); tcg_temp_free_i32(cpsr); /* Must exit loop to check un-masked IRQs */ - s->is_jmp =3D DISAS_EXIT; + s->base.is_jmp =3D DISAS_EXIT; } =20 /* Generate an old-style exception return. Marks pc as dead. */ @@ -4505,17 +4505,17 @@ static void gen_nop_hint(DisasContext *s, int val) case 1: /* yield */ if (!parallel_cpus) { gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_YIELD; + s->base.is_jmp =3D DISAS_YIELD; } break; case 3: /* wfi */ gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_WFI; + s->base.is_jmp =3D DISAS_WFI; break; case 2: /* wfe */ if (!parallel_cpus) { gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_WFE; + s->base.is_jmp =3D DISAS_WFE; } break; case 4: /* sev */ @@ -7654,13 +7654,13 @@ static int disas_coproc_insn(DisasContext *s, uint3= 2_t insn) return 1; } gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_WFI; + s->base.is_jmp =3D DISAS_WFI; return 0; default: break; } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)= ) { gen_io_start(); } =20 @@ -7751,7 +7751,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) } } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)= ) { /* I/O operations must end the TB here (whether read or write)= */ gen_io_end(); gen_lookup_tb(s); @@ -8065,7 +8065,7 @@ static void gen_srs(DisasContext *s, tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) @@ -8153,7 +8153,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) /* setend */ if (((insn >> 9) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { gen_helper_setend(cpu_env); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } return; } else if ((insn & 0x0fffff00) =3D=3D 0x057ff000) { @@ -9527,7 +9527,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) gen_helper_cpsr_write_eret(cpu_env, tmp); tcg_temp_free_i32(tmp); /* Must exit loop to check un-masked IRQs */ - s->is_jmp =3D DISAS_EXIT; + s->base.is_jmp =3D DISAS_EXIT; } } break; @@ -9565,7 +9565,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) /* swi */ gen_set_pc_im(s, s->pc); s->svc_imm =3D extract32(insn, 0, 24); - s->is_jmp =3D DISAS_SWI; + s->base.is_jmp =3D DISAS_SWI; break; default: illegal_op: @@ -11657,7 +11657,7 @@ static void disas_thumb_insn(CPUARMState *env, Disa= sContext *s) ARCH(6); if (((insn >> 3) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { gen_helper_setend(cpu_env); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } break; case 3: @@ -11751,7 +11751,7 @@ static void disas_thumb_insn(CPUARMState *env, Disa= sContext *s) /* swi */ gen_set_pc_im(s, s->pc); s->svc_imm =3D extract32(insn, 0, 8); - s->is_jmp =3D DISAS_SWI; + s->base.is_jmp =3D DISAS_SWI; break; } /* generate a conditional jump to next instruction */ @@ -11830,9 +11830,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D arm_env_get_cpu(env); DisasContext dc1, *dc =3D &dc1; - target_ulong pc_start; target_ulong next_page_start; - int num_insns; int max_insns; bool end_of_page; =20 @@ -11842,17 +11840,18 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. */ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(cs, tb); + gen_intermediate_code_a64(&dc->base, cs, tb); return; } =20 - pc_start =3D tb->pc; + dc->base.tb =3D tb; + dc->base.pc_first =3D tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - dc->tb =3D tb; - - dc->is_jmp =3D DISAS_NEXT; - dc->pc =3D pc_start; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; =20 dc->aarch64 =3D 0; @@ -11909,8 +11908,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) cpu_V1 =3D cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 =3D tcg_temp_new_i64(); - next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns =3D 0; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -11962,11 +11960,11 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) store_cpu_field(tmp, condexec_bits); } do { + dc->base.num_insns++; dc->insn_start_idx =3D tcg_op_buf_count(); tcg_gen_insn_start(dc->pc, (dc->condexec_cond << 4) | (dc->condexec_mask >= > 1), 0); - num_insns++; =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; @@ -11977,7 +11975,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_set_pc_im(dc, dc->pc); gen_helper_check_breakpoints(cpu_env); /* End the TB early; it's likely not going to be e= xecuted */ - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; } else { gen_exception_internal_insn(dc, 0, EXCP_DEBUG); /* The address covered by the breakpoint must be @@ -11995,7 +11993,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) } } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { gen_io_start(); } =20 @@ -12005,7 +12003,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) /* We always get here via a jump, so know we are not in a conditional execution block. */ gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; break; } #endif @@ -12021,10 +12019,11 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns =3D=3D 1); + assert(dc->base.num_insns =3D=3D 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - goto done_generating; + dc->base.is_jmp =3D DISAS_NORETURN; + break; } =20 if (dc->thumb) { @@ -12043,7 +12042,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) disas_arm_insn(dc, insn); } =20 - if (dc->condjmp && !dc->is_jmp) { + if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp =3D 0; } @@ -12070,11 +12069,11 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) end_of_page =3D (dc->pc >=3D next_page_start) || ((dc->pc >=3D next_page_start - 3) && insn_crosses_page(env, d= c)); =20 - } while (!dc->is_jmp && !tcg_op_buf_full() && + } while (!dc->base.is_jmp && !tcg_op_buf_full() && !is_singlestepping(dc) && !singlestep && !end_of_page && - num_insns < max_insns); + dc->base.num_insns < max_insns); =20 if (tb->cflags & CF_LAST_IO) { if (dc->condjmp) { @@ -12089,7 +12088,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) instruction was a conditional branch or trap, and the PC has already been written. */ gen_set_condexec(dc); - if (dc->is_jmp =3D=3D DISAS_BX_EXCRET) { + if (dc->base.is_jmp =3D=3D DISAS_BX_EXCRET) { /* Exception return branches need some special case code at the * end of the TB, which is complex enough that it has to * handle the single-step vs not and the condition-failed @@ -12098,7 +12097,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_bx_excret_final_code(dc); } else if (unlikely(is_singlestepping(dc))) { /* Unconditional and "condition passed" instruction codepath. */ - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_SWI: gen_ss_advance(dc); gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), @@ -12132,7 +12131,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) - Hardware watchpoints. Hardware breakpoints have already been handled and skip this co= de. */ - switch(dc->is_jmp) { + switch(dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, dc->pc); break; @@ -12188,22 +12187,22 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) } =20 done_generating: - gen_tb_end(tb, num_insns); + gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(pc_start)) { + qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, dc->thumb | (dc->sctlr_b << 1)); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size =3D dc->pc - pc_start; - tb->icount =3D num_insns; + tb->size =3D dc->pc - dc->base.pc_first; + tb->icount =3D dc->base.num_insns; } =20 static const char *cpu_mode_names[16] =3D { --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504715380156987.2229013249002; Wed, 6 Sep 2017 09:29:40 -0700 (PDT) Received: from localhost ([::1]:37060 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpdCs-00030r-Rz for importer@patchew.org; Wed, 06 Sep 2017 12:29:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41807) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqi-0000Hn-AN for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqb-0002Kd-RD for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:44 -0400 Received: from mail-pg0-x230.google.com ([2607:f8b0:400e:c05::230]:37872) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqb-0002Js-J7 for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:37 -0400 Received: by mail-pg0-x230.google.com with SMTP id d8so15975225pgt.4 for ; Wed, 06 Sep 2017 09:06:37 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c05::230 Subject: [Qemu-devel] [PULL 16/32] target/arm: [tcg] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002316201.22386.12115078843605656029.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 88 ++++++++++++++++++++++++++++------------------= ---- 1 file changed, 50 insertions(+), 38 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4db8978a93..a95c183cee 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11824,32 +11824,12 @@ static bool insn_crosses_page(CPUARMState *env, D= isasContext *s) return false; } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static int arm_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs, int max_insns) { + DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D arm_env_get_cpu(env); - DisasContext dc1, *dc =3D &dc1; - target_ulong next_page_start; - int max_insns; - bool end_of_page; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; @@ -11860,23 +11840,23 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) */ dc->secure_routed_to_el3 =3D arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb =3D ARM_TBFLAG_THUMB(tb->flags); - dc->sctlr_b =3D ARM_TBFLAG_SCTLR_B(tb->flags); - dc->be_data =3D ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; - dc->condexec_mask =3D (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; - dc->condexec_cond =3D ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; - dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); + dc->thumb =3D ARM_TBFLAG_THUMB(dc->base.tb->flags); + dc->sctlr_b =3D ARM_TBFLAG_SCTLR_B(dc->base.tb->flags); + dc->be_data =3D ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; + dc->condexec_mask =3D (ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) & 0xf) = << 1; + dc->condexec_cond =3D ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) >> 4; + dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb= ->flags)); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->ns =3D ARM_TBFLAG_NS(tb->flags); - dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(tb->flags); - dc->vfp_enabled =3D ARM_TBFLAG_VFPEN(tb->flags); - dc->vec_len =3D ARM_TBFLAG_VECLEN(tb->flags); - dc->vec_stride =3D ARM_TBFLAG_VECSTRIDE(tb->flags); - dc->c15_cpar =3D ARM_TBFLAG_XSCALE_CPAR(tb->flags); - dc->v7m_handler_mode =3D ARM_TBFLAG_HANDLER(tb->flags); + dc->ns =3D ARM_TBFLAG_NS(dc->base.tb->flags); + dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); + dc->vfp_enabled =3D ARM_TBFLAG_VFPEN(dc->base.tb->flags); + dc->vec_len =3D ARM_TBFLAG_VECLEN(dc->base.tb->flags); + dc->vec_stride =3D ARM_TBFLAG_VECSTRIDE(dc->base.tb->flags); + dc->c15_cpar =3D ARM_TBFLAG_XSCALE_CPAR(dc->base.tb->flags); + dc->v7m_handler_mode =3D ARM_TBFLAG_HANDLER(dc->base.tb->flags); dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; =20 @@ -11895,11 +11875,12 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); + dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex =3D false; dc->ss_same_el =3D false; /* Can't be true since EL_d must be AArch64 = */ =20 + cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); cpu_F0d =3D tcg_temp_new_i64(); @@ -11908,6 +11889,36 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) cpu_V1 =3D cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 =3D tcg_temp_new_i64(); + + return max_insns; +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + CPUARMState *env =3D cs->env_ptr; + DisasContext dc1, *dc =3D &dc1; + target_ulong next_page_start; + int max_insns; + bool end_of_page; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cs, tb); + return; + } + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { @@ -11916,6 +11927,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); =20 gen_tb_start(tb); =20 --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714950051799.8460726387319; Wed, 6 Sep 2017 09:22:30 -0700 (PDT) Received: from localhost ([::1]:37019 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpd5w-0004pF-Jz for importer@patchew.org; Wed, 06 Sep 2017 12:22:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41885) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcql-0000Je-IF for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqd-0002Qu-EG for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:47 -0400 Received: from mail-pf0-x230.google.com ([2607:f8b0:400e:c00::230]:34782) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqd-0002Mh-4r for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:39 -0400 Received: by mail-pf0-x230.google.com with SMTP id m1so13485441pfk.1 for ; Wed, 06 Sep 2017 09:06:39 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uZN6Az7gZPVb4WSjnLDcTNF9gV7xLS6OAi0/yMa5ABU=; b=TCBhE9C3L4eNvhojKApqPnrXy5uoOqLGYEEqYBUnYzRg7T55eep2nReK4TiTe+UhQZ ICeR0fmA4cL9WrRBlbr0LTNx3SyJ59rBuY1yOd2ZWdMZgoQhEXUjlV4hyWiT2rJyWtg9 TnJJ/5NAx+Y/Uo7jj0ejuaDXuxepjg2HkwiIQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uZN6Az7gZPVb4WSjnLDcTNF9gV7xLS6OAi0/yMa5ABU=; b=oloO2X+cH/XFN632OioSDd9hqPoLXGaVY1OOxQBJxa/ewdNL6MEkMxC9Dk1aZdnOCD Xxv1QK5zZfUANWRa1jub4XO3xRWkWudllJkTjD4TarZjDCi9BQ+mqknWAHkj+OYL76jw qHJq1yS+tWolECCs0RxP+hFMV8bzVeAvPsrQfoHmUlXC8jXDJNSteme2Km0V+MFPxlI4 WhErCuOnY6TVFJD96CyaWYPgJdziu11FyyOazbt6CvOFD7UNGQ1GXsQz6v1B+zLw1TWW nf0SzmZXPCecrpmavG0BpgBUciisKQQNX3HJf1sVYYa71780q2jTLuf38QZ4vf9LxX1V MlIA== X-Gm-Message-State: AHPjjUj/TwwTvJtq03RShRRA+Hv6pbdSPLr9wa8rfBhfcYQlduoBWr+b T0CxnEpGsnuctc/eQau3xQ== X-Google-Smtp-Source: ADKCNb4grL0UBTs6Z0NyJgJ2zN4YFUOlDzDzSUyHjL7GEWBWDfj/AfpeMsdq5lm14esRMetHU+ic8w== X-Received: by 10.84.130.97 with SMTP id 88mr9072991plc.138.1504713997938; Wed, 06 Sep 2017 09:06:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:57 -0700 Message-Id: <20170906160612.22769-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::230 Subject: [Qemu-devel] [PULL 17/32] target/arm: [tcg, a64] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002340430.22386.10889954302345646107.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 38 ++++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f5c678ef25..e8dc96c28a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11200,21 +11200,12 @@ static void disas_a64_insn(CPUARMState *env, Disa= sContext *s) free_tmp_a64(s); } =20 -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) +static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu, int max_insns) { - CPUARMState *env =3D cs->env_ptr; - ARMCPU *cpu =3D arm_env_get_cpu(env); DisasContext *dc =3D container_of(dcbase, DisasContext, base); - target_ulong next_page_start; - int max_insns; - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; + CPUARMState *env =3D cpu->env_ptr; + ARMCPU *arm_cpu =3D arm_env_get_cpu(env); =20 dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; @@ -11240,7 +11231,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len =3D 0; dc->vec_stride =3D 0; - dc->cp_regs =3D cpu->cp_regs; + dc->cp_regs =3D arm_cpu->cp_regs; dc->features =3D env->features; =20 /* Single step state. The code-generation logic here is: @@ -11265,6 +11256,24 @@ void gen_intermediate_code_a64(DisasContextBase *d= cbase, CPUState *cs, =20 init_tmp_a64_array(dc); =20 + return max_insns; +} + +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, + TranslationBlock *tb) +{ + CPUARMState *env =3D cs->env_ptr; + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong next_page_start; + int max_insns; + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { @@ -11273,6 +11282,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + max_insns =3D aarch64_tr_init_disas_context(&dc->base, cs, max_insns); =20 gen_tb_start(tb); =20 --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714773039972.6091213593073; Wed, 6 Sep 2017 09:19:33 -0700 (PDT) Received: from localhost ([::1]:37008 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpd35-0002WS-SF for importer@patchew.org; Wed, 06 Sep 2017 12:19:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41776) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqf-0000DA-UX for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqe-0002T5-LT for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:41 -0400 Received: from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:38905) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqe-0002Ss-Ck for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:40 -0400 Received: by mail-pg0-x235.google.com with SMTP id v66so15891614pgb.5 for ; Wed, 06 Sep 2017 09:06:40 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RBpPMCfof5ruZ/5aJuF/nc5V26lehfTdsSHm+aLUbHg=; b=kWQ1BaLlERsbz7Ey1Y9RJALRZYvkSSw/YWk/PdOLQq4BeP9iw9AxLJ3A7om0Cz/aMz htYwoK20j8eNrXJVH8zMP0WRc61/pyc5dZy8JwWcHRBnnBIIjHxXkwOvblB5UzltHHE+ kQnD5rXGRoTtmRw05iOSuch36gEAgDSPjnBrE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RBpPMCfof5ruZ/5aJuF/nc5V26lehfTdsSHm+aLUbHg=; b=qnSQ6ZLd/0GC4wN2RUy5KaiTwXnqy0c7A5nZm9IGJU+S5yfTRccnW4btKTUkbjytQe weWsohKNd4gzcN5QyakfJIXnA5STS1krj9EY+Vnxru11VLo0uQxDXJ0NCAMzSR9aAy+p zbtGt3cAmFC6W1M5wWo+95oONxIxuka3GKUZqQruEODt7tFRyKhZIDe89Ypyd71ng8Xx JO3/c4OD6x37I3dnbKx/n1u1YSHfx6m0fyN1qmfE1l70VMHBTti/ubHkdeZ/gEl8csXL PgBBJnARscHB4zcN6Q+R0iKP+kQEeeLVRyRX1anr2ffKBvpcNpuPMLDyHaPi0aMNTVNh NYew== X-Gm-Message-State: AHPjjUhv8u6oVK7kYC1TvOTjsE5/3abGC98SYP6xbOQesOu4N+pQDToc p26kiuEQ+UvgVWBOHGUrGA== X-Google-Smtp-Source: ADKCNb7EdBDftqeTlNT6qU2yshBr6Fod5ttKsPvQ9S9nFhBAA+Md7WRw8mdEWiULxVO1X2xzvfIQoQ== X-Received: by 10.84.130.42 with SMTP id 39mr9090288plc.239.1504713999160; Wed, 06 Sep 2017 09:06:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:58 -0700 Message-Id: <20170906160612.22769-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PULL 18/32] target/arm: [tcg] Port to tb_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002364681.22386.1701754996184325808.stgit@frigg.lan> [rth: Adjust for tb_start interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 82 +++++++++++++++++++++++++++-------------------= ---- 1 file changed, 44 insertions(+), 38 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index a95c183cee..3138a23e0c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11893,6 +11893,49 @@ static int arm_tr_init_disas_context(DisasContextB= ase *dcbase, return max_insns; } =20 +static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + /* A note on handling of the condexec (IT) bits: + * + * We want to avoid the overhead of having to write the updated condex= ec + * bits back to the CPUARMState for every instruction in an IT block. = So: + * (1) if the condexec bits are not already zero then we write + * zero back into the CPUARMState now. This avoids complications trying + * to do it at the end of the block. (For example if we don't do this + * it's hard to identify whether we can safely skip writing condexec + * at the end of the TB, which we definitely want to do for the case + * where a TB doesn't do anything with the IT state at all.) + * (2) if we are going to leave the TB then we call gen_set_condexec() + * which will write the correct value into CPUARMState if zero is wron= g. + * This is done both for leaving the TB at the end, and for leaving + * it because of an exception we know will happen, which is done in + * gen_exception_insn(). The latter is necessary because we need to + * leave the TB with the PC/IT state just prior to execution of the + * instruction which caused the exception. + * (3) if we leave the TB unexpectedly (eg a data abort on a load) + * then the CPUARMState will be wrong and we need to reset it. + * This is handled in the same way as restoration of the + * PC in these situations; we save the value of the condexec bits + * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() + * then uses this to restore them after an exception. + * + * Note that there are no instructions which can read the condexec + * bits, and none which can write non-static values to them, so + * we don't need to care about whether CPUARMState is correct in the + * middle of a TB. + */ + + /* Reset the conditional execution bits immediately. This avoids + complications trying to do it at the end of the block. */ + if (dc->condexec_mask || dc->condexec_cond) { + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(tmp, 0); + store_cpu_field(tmp, condexec_bits); + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11932,45 +11975,8 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) gen_tb_start(tb); =20 tcg_clear_temp_count(); + arm_tr_tb_start(&dc->base, cs); =20 - /* A note on handling of the condexec (IT) bits: - * - * We want to avoid the overhead of having to write the updated condex= ec - * bits back to the CPUARMState for every instruction in an IT block. = So: - * (1) if the condexec bits are not already zero then we write - * zero back into the CPUARMState now. This avoids complications trying - * to do it at the end of the block. (For example if we don't do this - * it's hard to identify whether we can safely skip writing condexec - * at the end of the TB, which we definitely want to do for the case - * where a TB doesn't do anything with the IT state at all.) - * (2) if we are going to leave the TB then we call gen_set_condexec() - * which will write the correct value into CPUARMState if zero is wron= g. - * This is done both for leaving the TB at the end, and for leaving - * it because of an exception we know will happen, which is done in - * gen_exception_insn(). The latter is necessary because we need to - * leave the TB with the PC/IT state just prior to execution of the - * instruction which caused the exception. - * (3) if we leave the TB unexpectedly (eg a data abort on a load) - * then the CPUARMState will be wrong and we need to reset it. - * This is handled in the same way as restoration of the - * PC in these situations; we save the value of the condexec bits - * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() - * then uses this to restore them after an exception. - * - * Note that there are no instructions which can read the condexec - * bits, and none which can write non-static values to them, so - * we don't need to care about whether CPUARMState is correct in the - * middle of a TB. - */ - - /* Reset the conditional execution bits immediately. This avoids - complications trying to do it at the end of the block. */ - if (dc->condexec_mask || dc->condexec_cond) - { - TCGv_i32 tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - store_cpu_field(tmp, condexec_bits); - } do { dc->base.num_insns++; dc->insn_start_idx =3D tcg_op_buf_count(); --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504715095425100.3802442954609; Wed, 6 Sep 2017 09:24:55 -0700 (PDT) Received: from localhost ([::1]:37029 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpd8I-0007I9-9R for importer@patchew.org; Wed, 06 Sep 2017 12:24:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41863) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqk-0000JX-2p for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqf-0002Ub-TQ for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:46 -0400 Received: from mail-pf0-x229.google.com ([2607:f8b0:400e:c00::229]:35366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqf-0002TM-Nt for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:41 -0400 Received: by mail-pf0-x229.google.com with SMTP id g13so13483540pfm.2 for ; Wed, 06 Sep 2017 09:06:41 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mV9q2OZFA8DKM3HzKR5SvCdCSSgw5pdh1P+rBA4ZOSE=; b=cilY5cuqj3E6xrFOdq+jEBJyOrlOA04CQEGfzawOytlf5ypjR3snd5GGWKaZqbWB8N DeFJAV+XnT7jgjGanvb0TDqFX8oYnw2qKUaYYJY/mG3wYIG6pvy6Xn7+H2FpdYbDmAny Rd8YxAu7s57NM5pRT3dDW8h8JoQM0CTyhfB+o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mV9q2OZFA8DKM3HzKR5SvCdCSSgw5pdh1P+rBA4ZOSE=; b=mzZHskps9lhPpt/SqihTdgiEjsX3LijG9+Fwta1x3CnQ9+muDvMSKkAtgDXbJ6x1s0 M9M3kqd4ii4G8J9CmTPTf0utgRGAfcXj7SDcqI55QrXqLG7aSLcbdB5LbqnwgCjwiCtN /6ip91kRcailyLsUevWzqi/mwZLW689G6TtgKPgdS/YfirbOh9+vADuJh9notBs0k0Ie 5wrPCkTvrkgSwyr2qpVpsiPGG88gpCnRfrde4XkRKGY3yEyj9Hp+5RCy8hkmFPaL4sBN lwEK/yoGiDXBty3tMbb+NTFFmOvPcWEDQ0PMONnxcjruPqd0BblZvw4Q7LZzoomwxXvf Rw9Q== X-Gm-Message-State: AHPjjUiERyJmdVQpKnTb3PubHZnn+O19NDdteRPw47VEdzrktZhvT7zs 8xFYSfDnFHqpUfXRexqTsg== X-Google-Smtp-Source: ADKCNb7bT984lKfrrL348k3UTtBh1sB7xGX3THak22iWkW8L3Lo09kCwi9RTFYSVx0yS+3iSjsP9IQ== X-Received: by 10.101.75.136 with SMTP id t8mr7868604pgq.359.1504714000576; Wed, 06 Sep 2017 09:06:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:59 -0700 Message-Id: <20170906160612.22769-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::229 Subject: [Qemu-devel] [PULL 19/32] target/arm: [tcg] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002388959.22386.12439646324427589940.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3138a23e0c..005157225c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11936,6 +11936,16 @@ static void arm_tr_tb_start(DisasContextBase *dcba= se, CPUState *cpu) } } =20 +static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + dc->insn_start_idx =3D tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), + 0); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11979,10 +11989,7 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) =20 do { dc->base.num_insns++; - dc->insn_start_idx =3D tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask >= > 1), - 0); + arm_tr_insn_start(&dc->base, cs); =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714342323843.8024276505087; Wed, 6 Sep 2017 09:12:22 -0700 (PDT) Received: from localhost ([::1]:36976 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcw9-0004j1-5O for importer@patchew.org; Wed, 06 Sep 2017 12:12:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41811) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqi-0000Hu-E2 for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqh-0002b4-8D for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:44 -0400 Received: from mail-pf0-x233.google.com ([2607:f8b0:400e:c00::233]:33133) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqh-0002Yz-1G for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:43 -0400 Received: by mail-pf0-x233.google.com with SMTP id y68so13496497pfd.0 for ; Wed, 06 Sep 2017 09:06:42 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rK5vcMmer/3Wux+HRmWMOMZFIkyWPjSSJlQhe5ZOLqw=; b=DvCXQqsuUJlIoLi1JUMTYobUzTnYw6mQhbXdDUHjNqkrZE+FAYcaC7kpT7kPs+oQ8V YA3nMuQz16+xu59WCF2El+QFXWsfYVFEVjwWMB7GVHPO3A9KbEw/y1cwJTp7MrHjNF45 K8Kso7qsCxmxoctn0WsTLp+nXbH0svLWlOBHw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rK5vcMmer/3Wux+HRmWMOMZFIkyWPjSSJlQhe5ZOLqw=; b=cmE9aXB5SqpY9sTujft6PepHFDn41i8gF+FJYaPSTUrdn8JYNytjiehFnGS5fH5SDe ssWFFHYQ2cMPy+HLrqB827bPd0Kbf4Xrhz6Q9hEqgJBIgyk9H7Oa2ns4N23SZMiZqVoB 2HKR6GA+3Va00Zmfeeg5XMj1MClOS0FfN1P839TNDwG+EyULYz94h47GlUHqxlKXRZ9T PZ+LWT4jxJ6aKCVupXLkN3fFWVe69z4oNdTeeYrHYDAKcM3P3tmmAzJ0Iluk8240rjSy w39lHPHLffGpTFaDLN+85k7KZlEBLLPVgZdauyQwxzuo9YBoSpqPbF5QSjktfLysKHRt ouSg== X-Gm-Message-State: AHPjjUh5Fe2jW2OiVAFR4WdJRhIgjfqiuE81hf5l80Aew7pYjGtoAhEn DUg1SVYLtgFrzBDHc3MJgQ== X-Google-Smtp-Source: ADKCNb7wzgf1HF9Z/BUaBwMBrDuDTPjObMDZ9R1OW5FmrhI8MFJvYZtF69hYz/lNSTxsUpPT4Ic/UA== X-Received: by 10.98.158.201 with SMTP id f70mr8035014pfk.162.1504714001862; Wed, 06 Sep 2017 09:06:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:00 -0700 Message-Id: <20170906160612.22769-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::233 Subject: [Qemu-devel] [PULL 20/32] target/arm: [tcg, a64] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002413187.22386.156315485813606121.stgit@frigg.lan> [rth: Use DISAS_TOO_MANY for "execute only one more" after bp.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 11 ++++++++-- target/arm/translate.c | 55 +++++++++++++++++++++++++++++-------------= ---- 2 files changed, 44 insertions(+), 22 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e8dc96c28a..1eab10696c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11259,6 +11259,14 @@ static int aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, return max_insns; } =20 +static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + dc->insn_start_idx =3D tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, 0, 0); +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11290,8 +11298,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, =20 do { dc->base.num_insns++; - dc->insn_start_idx =3D tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, 0, 0); + aarch64_tr_insn_start(&dc->base, cs); =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; diff --git a/target/arm/translate.c b/target/arm/translate.c index 005157225c..2f5f65310d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11946,6 +11946,33 @@ static void arm_tr_insn_start(DisasContextBase *dc= base, CPUState *cpu) 0); } =20 +static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cp= u, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_set_condexec(dc); + gen_set_pc_im(dc, dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it's likely not going to be executed */ + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + /* TODO: Advance PC by correct instruction length to + * avoid disassembler error messages */ + dc->pc +=3D 2; + dc->base.is_jmp =3D DISAS_NORETURN; + } + + return true; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11994,28 +12021,15 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->pc) { - if (bp->flags & BP_CPU) { - gen_set_condexec(dc); - gen_set_pc_im(dc, dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it's likely not going to be e= xecuted */ - dc->base.is_jmp =3D DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length = to - * avoid disassembler error messages */ - dc->pc +=3D 2; - goto done_generating; + if (bp->pc =3D=3D dc->base.pc_next) { + if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { + break; } - break; } } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } } =20 if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { @@ -12137,6 +12151,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_exception(EXCP_SMC, syn_aa32_smc(), 3); break; case DISAS_NEXT: + case DISAS_TOO_MANY: case DISAS_UPDATE: gen_set_pc_im(dc, dc->pc); /* fall through */ @@ -12158,6 +12173,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) */ switch(dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; case DISAS_JUMP: @@ -12211,7 +12227,6 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) } } =20 -done_generating: gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PULL 21/32] target/arm: [tcg, a64] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002461630.22386.14827196109258040543.stgit@frigg.lan> [rth: Use DISAS_TOO_MANY for "execute only one more" after bp.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++------------= ---- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1eab10696c..e94198280d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11267,6 +11267,30 @@ static void aarch64_tr_insn_start(DisasContextBase= *dcbase, CPUState *cpu) tcg_gen_insn_start(dc->pc, 0, 0); } =20 +static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_a64_set_pc_im(dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it likely won't be executed */ + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + dc->pc +=3D 4; + dc->base.is_jmp =3D DISAS_NORETURN; + } + + return true; +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11303,25 +11327,15 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->pc) { - if (bp->flags & BP_CPU) { - gen_a64_set_pc_im(dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it likely won't be executed */ - dc->base.is_jmp =3D DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [dc->base.tb->pc, dc->base.tb->pc += dc->base.tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - dc->base.tb->size below does the right thing. = */ - dc->pc +=3D 4; - goto done_generating; + if (bp->pc =3D=3D dc->base.pc_next) { + if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) { + break; } - break; } } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } } =20 if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { @@ -11392,6 +11406,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, } else { switch (dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; case DISAS_JUMP: @@ -11429,7 +11444,6 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, } } =20 -done_generating: gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504715510498984.6406553007105; Wed, 6 Sep 2017 09:31:50 -0700 (PDT) Received: from localhost ([::1]:37073 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpdEz-0004jm-7r for importer@patchew.org; Wed, 06 Sep 2017 12:31:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41915) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqn-0000MH-BZ for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqk-0002fj-0s for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:49 -0400 Received: from mail-pg0-x22d.google.com ([2607:f8b0:400e:c05::22d]:35580) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqj-0002dc-Ml for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:45 -0400 Received: by mail-pg0-x22d.google.com with SMTP id 188so12738604pgb.2 for ; Wed, 06 Sep 2017 09:06:45 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Tmhd7lJTCptCpYf1L1lrkBjfQN41pZppSXIWh62yW1E=; b=XCaqWd0/hr5vjFWUqqmiVMsr9ot7IdCA+NTNNeHf/6Oo5WvqEd1bRxYraEVzf2wVOz EOj9XTa5ZlZKVLu1eDy1j5gxy+q2//O3Koxdh5hnZLVgG3QG3DrNZJH+C6/QC3nC2II3 3IJ1e+W9iYNl7rrUWmh4hU0jW3DHc0H+KklxM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Tmhd7lJTCptCpYf1L1lrkBjfQN41pZppSXIWh62yW1E=; b=ljTnK1lF/py/drcXvuVLLgZ0e8yOORWyheqPpsdsgzlsvWX1XhEnTCGFRuyjBuJJaM FOGUobCDib1PHFyBc25sL6qSxjEEAdxfn/PVhqqhQEiKeqK5hBa9PHzM8Uypmsxxy4f5 ROylJQMxqDaKYl8VQZhB/7Hdb10ShqDPS71iNaBSkvr/zQ6mxy0IBZFwF2La4Wi89pWd NSegH9yqKzc9BppcJe+BXeWL9gHJi8GIL/6qVwI9kX/wKJf01AcP5uWZFs8Hzq+X8ehr vMBXP1lKgMvZMMcJ6Oj0eLzBCB8HSyIYrdiLDwmaCnu0ZVZmmw/0hauwFPMNEQ67i/3W WHpQ== X-Gm-Message-State: AHPjjUgqYgXsSW7AL2+tgYrEjFkEgY0F7vgA0nbwFTk5kJJ1OzL5488r f3WuyIJUYt1EQGLafv8yfw== X-Google-Smtp-Source: ADKCNb7tLq93Qz5aZWCd8RbFy9EJa6dJTf2LfOxrdUVMHoDwiUw3ifHE2p6EhjduMmkwSVFmd0Z9hA== X-Received: by 10.98.35.210 with SMTP id q79mr7817950pfj.340.1504714004230; Wed, 06 Sep 2017 09:06:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:02 -0700 Message-Id: <20170906160612.22769-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: [Qemu-devel] [PULL 22/32] target/arm: [tcg] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002485863.22386.13949856269576226529.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.h | 1 + target/arm/translate.c | 165 +++++++++++++++++++++++++++------------------= ---- 2 files changed, 91 insertions(+), 75 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index a804ff65ac..e8dcec51ac 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -9,6 +9,7 @@ typedef struct DisasContext { DisasContextBase base; =20 target_ulong pc; + target_ulong next_page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; diff --git a/target/arm/translate.c b/target/arm/translate.c index 2f5f65310d..5737299943 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11880,6 +11880,8 @@ static int arm_tr_init_disas_context(DisasContextBa= se *dcbase, dc->is_ldex =3D false; dc->ss_same_el =3D false; /* Can't be true since EL_d must be AArch64 = */ =20 + dc->next_page_start =3D + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; =20 cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); @@ -11973,14 +11975,93 @@ static bool arm_tr_breakpoint_check(DisasContextB= ase *dcbase, CPUState *cpu, return true; } =20 +static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >=3D 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->base.is_jmp =3D DISAS_NORETURN; + return; + } +#endif + + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns =3D=3D 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp =3D DISAS_NORETURN; + return; + } + + if (dc->thumb) { + disas_thumb_insn(env, dc); + if (dc->condexec_mask) { + dc->condexec_cond =3D (dc->condexec_cond & 0xe) + | ((dc->condexec_mask >> 4) & 1); + dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; + if (dc->condexec_mask =3D=3D 0) { + dc->condexec_cond =3D 0; + } + } + } else { + unsigned int insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->pc +=3D 4; + disas_arm_insn(dc, insn); + } + + if (dc->condjmp && !dc->base.is_jmp) { + gen_set_label(dc->condlabel); + dc->condjmp =3D 0; + } + + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { + /* Translation stops when a conditional branch is encountered. + * Otherwise the subsequent code could get translated several time= s. + * Also stop translation when a page boundary is reached. This + * ensures prefetch aborts occur at the right place. */ + + if (is_singlestepping(dc)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else if ((dc->pc >=3D dc->next_page_start) || + ((dc->pc >=3D dc->next_page_start - 3) && + insn_crosses_page(env, dc))) { + /* We want to stop the TB if the next insn starts in a new pag= e, + * or if it spans between this page and the next. This means t= hat + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit= insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } + + dc->base.pc_next =3D dc->pc; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - CPUARMState *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; - target_ulong next_page_start; int max_insns; - bool end_of_page; =20 /* generate intermediate code */ =20 @@ -11999,7 +12080,6 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) dc->base.num_insns =3D 0; dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -12036,83 +12116,18 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) gen_io_start(); } =20 -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >=3D 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - } -#endif - - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debug= ged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(dc->base.num_insns =3D=3D 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - } - - if (dc->thumb) { - disas_thumb_insn(env, dc); - if (dc->condexec_mask) { - dc->condexec_cond =3D (dc->condexec_cond & 0xe) - | ((dc->condexec_mask >> 4) & 1); - dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; - if (dc->condexec_mask =3D=3D 0) { - dc->condexec_cond =3D 0; - } - } - } else { - unsigned int insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); - dc->pc +=3D 4; - disas_arm_insn(dc, insn); - } - - if (dc->condjmp && !dc->base.is_jmp) { - gen_set_label(dc->condlabel); - dc->condjmp =3D 0; - } + arm_tr_translate_insn(&dc->base, cs); =20 if (tcg_check_temp_count()) { fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", dc->pc); } =20 - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several time= s. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. */ - - /* We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - end_of_page =3D (dc->pc >=3D next_page_start) || - ((dc->pc >=3D next_page_start - 3) && insn_crosses_page(env, d= c)); - - } while (!dc->base.is_jmp && !tcg_op_buf_full() && - !is_singlestepping(dc) && - !singlestep && - !end_of_page && - dc->base.num_insns < max_insns); + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >=3D max_insns)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); =20 if (tb->cflags & CF_LAST_IO) { if (dc->condjmp) { --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504715012333973.7126170296771; Wed, 6 Sep 2017 09:23:32 -0700 (PDT) Received: from localhost ([::1]:37022 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpd6x-0005oN-3P for importer@patchew.org; Wed, 06 Sep 2017 12:23:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41941) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqp-0000Pg-3Q for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqk-0002jS-Nu for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:51 -0400 Received: from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:34784) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqk-0002g9-GF for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:46 -0400 Received: by mail-pf0-x22a.google.com with SMTP id m1so13485921pfk.1 for ; Wed, 06 Sep 2017 09:06:46 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xElHN/zfdPbhnMF3R21WRLSn0KBWPuHQqnySWytQRsM=; b=OEq4M0Y3GNXnaooOb9izY3AxbUALVbVgEJP0ZFGWFCTuuLMwDk9nHN3fOERsvB5wic /vF24fUxXYDmF8g9E1plHUrEOWlw+WjkvCpG1DQ4vT8jTK4WRXc9dBIJTyOhOxv6oLLE we4tep2AxCLHWx6biSJErfToFQwHfq8RX3cpc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xElHN/zfdPbhnMF3R21WRLSn0KBWPuHQqnySWytQRsM=; b=IgnHoKkOx5OvV07nT0GZdowwFp9660ctaNSQRiLi1jbATbI6wFbhL4uJj3C1CarYhW IPkb0Tqd7bbOdCxPn0OLaS5mph2xF3ei/GyhWVpLZgg0dVkH/oFbAKXbbmKKTF9l61FX 0KaXBG61xqv7PRL18ccSKBo0ce9yNxJzkBBdxjqoI7jY1eMGI7sslCdJJ29ZBf8DZf5x Ti/bx7bUQR4vbkRFZlBRup4fJ6aPth+BpiYCFDy+nOyjMQW+w196aS0sw2/d7s9OesF0 MNzYcl762r4mEzevCOkMk0tyMHTGCxTYHdePdBioxgAm3p6zbOsPKCzbTU1fYiW3mnoY x+aw== X-Gm-Message-State: AHPjjUhndRIBs4weD45jlcuvHx8t7B5qjTJuRYbAnjcnP1h4EqLr72O7 IoCHNBTJsIkGpVP0NQHS6g== X-Google-Smtp-Source: ADKCNb6sV6V5nGz89otRgPFmobQosMDHBLs2SMUZ9N0B2abvHqpj4/vChMZvxvmQ/YcqvZ7n29g/bg== X-Received: by 10.84.234.197 with SMTP id i5mr8829617plt.184.1504714005315; Wed, 06 Sep 2017 09:06:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:03 -0700 Message-Id: <20170906160612.22769-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PULL 23/32] target/arm: [tcg, a64] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002510079.22386.10164419868911710218.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++--------------= ---- 1 file changed, 43 insertions(+), 28 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e94198280d..f959f4469a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11254,6 +11254,9 @@ static int aarch64_tr_init_disas_context(DisasConte= xtBase *dcbase, dc->is_ldex =3D false; dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 + dc->next_page_start =3D + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + init_tmp_a64_array(dc); =20 return max_insns; @@ -11291,12 +11294,43 @@ static bool aarch64_tr_breakpoint_check(DisasCont= extBase *dcbase, CPUState *cpu, return true; } =20 +static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns =3D=3D 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp =3D DISAS_NORETURN; + } else { + disas_a64_insn(env, dc); + } + + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { + if (dc->ss_active || dc->pc >=3D dc->next_page_start) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } + + dc->base.pc_next =3D dc->pc; +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { - CPUARMState *env =3D cs->env_ptr; DisasContext *dc =3D container_of(dcbase, DisasContext, base); - target_ulong next_page_start; int max_insns; =20 dc->base.tb =3D tb; @@ -11306,7 +11340,6 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, dc->base.num_insns =3D 0; dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -11342,42 +11375,24 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, gen_io_start(); } =20 - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debug= ged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(dc->base.num_insns =3D=3D 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - } - - disas_a64_insn(env, dc); + aarch64_tr_translate_insn(&dc->base, cs); =20 if (tcg_check_temp_count()) { fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", dc->pc); } =20 + if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabl= ed || + singlestep || dc->base.num_insns >=3D max_insn= s)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + /* Translation stops when a conditional branch is encountered. * Otherwise the subsequent code could get translated several time= s. * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - } while (!dc->base.is_jmp && !tcg_op_buf_full() && - !cs->singlestep_enabled && - !singlestep && - !dc->ss_active && - dc->pc < next_page_start && - dc->base.num_insns < max_insns); + } while (!dc->base.is_jmp); =20 if (dc->base.tb->cflags & CF_LAST_IO) { gen_io_end(); --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714668936812.1303196913118; Wed, 6 Sep 2017 09:17:48 -0700 (PDT) Received: from localhost ([::1]:37001 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpd1P-00018T-Ox for importer@patchew.org; Wed, 06 Sep 2017 12:17:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41973) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqr-0000Uc-DQ for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqm-0002k9-4b for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:53 -0400 Received: from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:34481) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcql-0002jr-T8 for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:48 -0400 Received: by mail-pg0-x235.google.com with SMTP id q68so158773pgq.1 for ; Wed, 06 Sep 2017 09:06:47 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=udUFVDShR2S/ublVBwFZxFSZzoHnpVkH6YgeO1JXXp4=; b=XLrOqJqlYaim7/bUYgt6j+tYAP+oG0MMShSn/NCaN4LrhZLd4HGsgIp6BCARIrJ5rb UNhCkGBAIuUoCPMdZmf901+czVxeMCO1oSBk6DmfI1I1ibt0NKsGO2gIzsR5z7OXWUDK KZcrn3sbmSQRzYyuY4xPeqhlPzjH0Cxr2jIWE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=udUFVDShR2S/ublVBwFZxFSZzoHnpVkH6YgeO1JXXp4=; b=B67ryNT1puuz9HRj7/0nrU5Lo29YCbPlRynCviboyGl5fpBFrg2EKvY7m1J+3kDFi3 0jc8KRPwb+SKp/cgkJ+K6eaRHVFYCQPspY44DlF8sKt7XJKZF/ENLbLaDkm/Ounsr1Op 9H2zctcGd0W1oTqDtSKtiFde5cRFvzQg7FXupMr2A03SNjPLHz1E6PlQg+yyr4ED4Qde tB4E3C9cKL30Fgmc3UPMEWtIlZKsJY1PL7LMSl8aofa/0t8njBGMa5Sfsoq6XgwROZRf SijOiB2A5WzFjHawTu12iODr3HQ7hBGyrnQ8ew8YulD90u7LgSirDX6BmZw2qIIfBzxO ridg== X-Gm-Message-State: AHPjjUjT0LV2pP3JoVDsPIv8p1lYgpmYyMpmHMkRkayBRKtuLK5YXwOv HydMhsyaV7ay5OSbcvG1Tw== X-Google-Smtp-Source: ADKCNb4zHeSs4rgl2PkXxdtg8hVWMceurk7I0fENU9aF3tzh0mAdXFIH9VkpRGA1YVuFAyjOyCLOkw== X-Received: by 10.98.69.137 with SMTP id n9mr6788038pfi.164.1504714006495; Wed, 06 Sep 2017 09:06:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:04 -0700 Message-Id: <20170906160612.22769-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PULL 24/32] target/arm: [tcg] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002534291.22386.13499916738708680298.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.c | 161 ++++++++++++++++++++++++++-------------------= ---- 1 file changed, 84 insertions(+), 77 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5737299943..10527b50c8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12057,85 +12057,13 @@ static void arm_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) dc->base.pc_next =3D dc->pc; } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { - DisasContext dc1, *dc =3D &dc1; - int max_insns; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_tr_tb_start(&dc->base, cs); - - do { - dc->base.num_insns++; - arm_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { - gen_io_start(); - } - - arm_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >=3D max_insns)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - if (tb->cflags & CF_LAST_IO) { - if (dc->condjmp) { - /* FIXME: This can theoretically happen with self-modifying - code. */ - cpu_abort(cs, "IO on conditional branch instruction"); - } - gen_io_end(); + if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) { + /* FIXME: This can theoretically happen with self-modifying code. = */ + cpu_abort(cpu, "IO on conditional branch instruction"); } =20 /* At this stage dc->condjmp will only be set when the skipped @@ -12241,6 +12169,85 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) gen_goto_tb(dc, 1, dc->pc); } } +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext dc1, *dc =3D &dc1; + int max_insns; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cs, tb); + return; + } + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + + max_insns =3D tb->cflags & CF_COUNT_MASK; + if (max_insns =3D=3D 0) { + max_insns =3D CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns =3D TCG_MAX_INSNS; + } + max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); + + gen_tb_start(tb); + + tcg_clear_temp_count(); + arm_tr_tb_start(&dc->base, cs); + + do { + dc->base.num_insns++; + arm_tr_insn_start(&dc->base, cs); + + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc =3D=3D dc->base.pc_next) { + if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { + break; + } + } + } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } + } + + if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { + gen_io_start(); + } + + arm_tr_translate_insn(&dc->base, cs); + + if (tcg_check_temp_count()) { + fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", + dc->pc); + } + + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >=3D max_insns)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); + + if (dc->base.tb->cflags & CF_LAST_IO) { + gen_io_end(); + } + + arm_tr_tb_stop(&dc->base, cs); =20 gen_tb_end(tb, dc->base.num_insns); =20 --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Kl1r5WRPXIH5biKfH0poWfuspGHN5gu/mN6HurZuXOA=; b=ScF8CEj+/7PwoGDDP5512SqRznakWZEUO0qi54V1orAcI63rCTdn/BXwZ+94/vwuqO Ssh7EBDWI5FRxYHYiJEehMonjqWMszQRmFALny8oOeGXucpm8nRfKzUyryrmf9+XPsOC J9A/kni8zKB5nspuGW6OCC635v9Mmsky2AVN4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kl1r5WRPXIH5biKfH0poWfuspGHN5gu/mN6HurZuXOA=; b=VxzQE7yuhcxLaoB2sq9DtAxkJgSCy2qOwI52bnalCFJCPMhdT1Ba+pEkFQQrSwyag3 gvqgAOHONEboCWJIy3hQgCxbIZtghswtcA0OYPHDNhrNQ3H51l9nnr6aeN/04EZJce6t GyNPtVbTBbGObSpsdHB4QTPLI/r+/MTktlu8D1uqrY84mU0LpwjtoEgoXbVNHJOlNLB1 3Ka0ee8lbZdKIQUJdjx9+YsmspmdrhuOhj134P0He52f0/iUl4ZjqzpsjNUpyCKaFMT5 oEpGL+ZoRM24kZLI5AJ2Wa/PyEAqtcggOuxTjSH6f6bF2123gMuUS+sbqTuYUOSMY9Wj ofEg== X-Gm-Message-State: AHPjjUhgIGsaRvTMY2sEUQ9Jo5StInDe0vATX3LBcIrjKa7PM5HY1cP+ eRU+rPOuZCKvovNS8dEKCw== X-Google-Smtp-Source: ADKCNb4hiHMct9SHgkQ27TgPBx2XSl5IKRiFEJcTNFjZM0QU8I6YNN1rBGfty5c3/Td73qtXE1+3PA== X-Received: by 10.84.211.106 with SMTP id b97mr8799686pli.148.1504714008014; Wed, 06 Sep 2017 09:06:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:05 -0700 Message-Id: <20170906160612.22769-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::236 Subject: [Qemu-devel] [PULL 25/32] target/arm: [tcg,a64] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002558503.22386.1149037590886263349.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 127 ++++++++++++++++++++++++-----------------= ---- 1 file changed, 67 insertions(+), 60 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f959f4469a..723e86c976 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11327,6 +11327,72 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) dc->base.pc_next =3D dc->pc; } =20 +static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) { + /* Note that this means single stepping WFI doesn't halt the CPU. + * For conditional branch insns this is harmless unreachable code = as + * gen_goto_tb() has already handled emitting the debug exception + * (and thus a tb-jump is not possible when singlestepping). + */ + switch (dc->base.is_jmp) { + default: + gen_a64_set_pc_im(dc->pc); + /* fall through */ + case DISAS_JUMP: + if (dc->base.singlestep_enabled) { + gen_exception_internal(EXCP_DEBUG); + } else { + gen_step_complete_exception(dc); + } + break; + case DISAS_NORETURN: + break; + } + } else { + switch (dc->base.is_jmp) { + case DISAS_NEXT: + case DISAS_TOO_MANY: + gen_goto_tb(dc, 1, dc->pc); + break; + default: + case DISAS_UPDATE: + gen_a64_set_pc_im(dc->pc); + /* fall through */ + case DISAS_JUMP: + tcg_gen_lookup_and_goto_ptr(cpu_pc); + break; + case DISAS_EXIT: + tcg_gen_exit_tb(0); + break; + case DISAS_NORETURN: + case DISAS_SWI: + break; + case DISAS_WFE: + gen_a64_set_pc_im(dc->pc); + gen_helper_wfe(cpu_env); + break; + case DISAS_YIELD: + gen_a64_set_pc_im(dc->pc); + gen_helper_yield(cpu_env); + break; + case DISAS_WFI: + /* This is a special case because we don't want to just halt t= he CPU + * if trying to debug across a WFI. + */ + gen_a64_set_pc_im(dc->pc); + gen_helper_wfi(cpu_env); + /* The helper doesn't necessarily throw an exception, but we + * must go back to the main loop to check for interrupts anywa= y. + */ + tcg_gen_exit_tb(0); + break; + } + } +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11398,66 +11464,7 @@ void gen_intermediate_code_a64(DisasContextBase *d= cbase, CPUState *cs, gen_io_end(); } =20 - if (unlikely(cs->singlestep_enabled || dc->ss_active)) { - /* Note that this means single stepping WFI doesn't halt the CPU. - * For conditional branch insns this is harmless unreachable code = as - * gen_goto_tb() has already handled emitting the debug exception - * (and thus a tb-jump is not possible when singlestepping). - */ - switch (dc->base.is_jmp) { - default: - gen_a64_set_pc_im(dc->pc); - /* fall through */ - case DISAS_JUMP: - if (cs->singlestep_enabled) { - gen_exception_internal(EXCP_DEBUG); - } else { - gen_step_complete_exception(dc); - } - break; - case DISAS_NORETURN: - break; - } - } else { - switch (dc->base.is_jmp) { - case DISAS_NEXT: - case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->pc); - break; - case DISAS_JUMP: - tcg_gen_lookup_and_goto_ptr(cpu_pc); - break; - case DISAS_NORETURN: - case DISAS_SWI: - break; - case DISAS_WFE: - gen_a64_set_pc_im(dc->pc); - gen_helper_wfe(cpu_env); - break; - case DISAS_YIELD: - gen_a64_set_pc_im(dc->pc); - gen_helper_yield(cpu_env); - break; - case DISAS_WFI: - /* This is a special case because we don't want to just halt t= he CPU - * if trying to debug across a WFI. - */ - gen_a64_set_pc_im(dc->pc); - gen_helper_wfi(cpu_env); - /* The helper doesn't necessarily throw an exception, but we - * must go back to the main loop to check for interrupts anywa= y. - */ - tcg_gen_exit_tb(0); - break; - case DISAS_UPDATE: - gen_a64_set_pc_im(dc->pc); - /* fall through */ - case DISAS_EXIT: - default: - tcg_gen_exit_tb(0); - break; - } - } + aarch64_tr_tb_stop(&dc->base, cs); =20 gen_tb_end(tb, dc->base.num_insns); =20 --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pEMSMV5Z7pScAAcMP+yKs/Gg5lY3QrUgOjrToUNpIiA=; b=DYEOaXnQqzDP5qiNQIzU59g1TIyI5m3U1tI+gxHhAIpoFfrOjdomeOedJnu1V4Kag5 FBhWGb7jeDLfHV5ko2Cm3LHQcZzMfyBoWtIN0vgzpYOugtOjClT10zD/HGIQs9ze64aW vSSxK5rj9O4Ipbn1dUltL6OXExjGG4iZNjQAQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pEMSMV5Z7pScAAcMP+yKs/Gg5lY3QrUgOjrToUNpIiA=; b=GbldSpfDMMF7MpW3mRlOCtQUhBvaEP2uTLk9/RMUU2ehcMP/cVG0Yj/yNcazMd1eUM 5BpMtzeAe3HmbLpmrFTkkju1tQ4LiF7PsiCbKc3pLKsoeGwIYRqSJXIwBCgav6EdvBBL 5szeyGgc/LnmN+TZrmAShK1YaYo/1oyNc4M/gPcmGR6yV2iUsBaCeBy7fKT01K/WLXAW YQi752eNEznOBGjZPQZxdQWdDAtGoF5JaK2w9uD7fGtVUpVKIXiGcfxJHQke9EeEuqo4 ibKFsl0oBJF3oiII9Khfg/WyuJIDxK7U2Th1NbLVDfX30NCSt4+pEyn7UlgaTwO1HO/p yO7A== X-Gm-Message-State: AHPjjUhQQly9CzapSPa237soYVNT4xzIpG1/471SXGikX5uawhwhrlIl l9FLbRbCafst7VKAKGJ35A== X-Google-Smtp-Source: ADKCNb4Dasx45YMUyouWpU3jqHiuZV6WRT0kQOtKJg6dou8cexlrVPASQ3m0Kj4ofGl8nKJnQ6uHGw== X-Received: by 10.98.201.197 with SMTP id l66mr7636810pfk.135.1504714009257; Wed, 06 Sep 2017 09:06:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:06 -0700 Message-Id: <20170906160612.22769-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PULL 26/32] target/arm: [tcg] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002582711.22386.191527630537864599.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 10527b50c8..2dca196e17 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12171,6 +12171,15 @@ static void arm_tr_tb_stop(DisasContextBase *dcbas= e, CPUState *cpu) } } =20 +static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, + dc->thumb | (dc->sctlr_b << 1)); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -12251,20 +12260,19 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) =20 gen_tb_end(tb, dc->base.num_insns); =20 + tb->size =3D dc->pc - dc->base.pc_first; + tb->icount =3D dc->base.num_insns; + #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); - log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, - dc->thumb | (dc->sctlr_b << 1)); + arm_tr_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size =3D dc->pc - dc->base.pc_first; - tb->icount =3D dc->base.num_insns; } =20 static const char *cpu_mode_names[16] =3D { --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504715873268270.79390728655915; Wed, 6 Sep 2017 09:37:53 -0700 (PDT) Received: from localhost ([::1]:37101 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpdKp-0000yl-TO for importer@patchew.org; Wed, 06 Sep 2017 12:37:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42005) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqv-0000Xt-LO for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:07:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqp-0002ss-QY for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:57 -0400 Received: from mail-pg0-x22d.google.com ([2607:f8b0:400e:c05::22d]:35581) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqp-0002rK-Kg for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:51 -0400 Received: by mail-pg0-x22d.google.com with SMTP id 188so12739150pgb.2 for ; Wed, 06 Sep 2017 09:06:51 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zTHnNo4fpTvvHZYmEhurskvtWnhzILXVy4UhrbbCYXM=; b=D8pQR9sjA5G9Qmb99cbnG6iurAxDYUp6rNJJ/BSXWoY30IyraUOjhaflF+E27mNMQE ZlHhBBkD41BneLfWDjpZY6kRGpQ9U8ibj4ZjWH38rWsGWhTMq+VfLumR+23L+gExGvVY t0h+DsGkB0CmZz8w2TNp9o4baqWldlE+0Wi3U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zTHnNo4fpTvvHZYmEhurskvtWnhzILXVy4UhrbbCYXM=; b=EmzhB1PcciKfZ9vSW0ApQNDrkydeevcbtAWEZstwKWKtNxzVrti6ZXAEAuEB8KgIwg Ne9XGAidRfYi0vBI2TRGBchEfxMEEJXzy4y8Q2M9RLNDlSfJa+5QiF64w7abg1vNHcXP +zkIhHrssGpicmtv9WvxXXX6KDLursFu0McoOz2/1Rsdnyn0STPKQxacKZdn9NDTTslE OflsNGsEf8H9trsZ1zTP8wvXgF2NptTwiAIuyOSkLEnZVI22K2zc+fM+XqAboBggzsE2 WzzB78YzoJZNYGmZ9j0auWKXsCM5dbdn6pxkngSyq521KhVBh7fG4gvJYfw03aiRtaru f1YA== X-Gm-Message-State: AHPjjUgv2NW80vxecW/kWwkievxUS5Y/SZbGEXkFFoIzG/rNUgrcB++C 9ODgAMRgaNsoNb5pPT3e/w== X-Google-Smtp-Source: ADKCNb4CrrQ7YiaRh0+wocy6gk7wDoTf23/pb3scbXyfuyR5GXWhZoguk0g5z4pxW+OLLcfbky/C8w== X-Received: by 10.84.131.109 with SMTP id 100mr8848919pld.122.1504714010503; Wed, 06 Sep 2017 09:06:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:07 -0700 Message-Id: <20170906160612.22769-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22d Subject: [Qemu-devel] [PULL 27/32] target/arm: [tcg,a64] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002606914.22386.15524101311003685068.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 723e86c976..1973a36462 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11393,6 +11393,16 @@ static void aarch64_tr_tb_stop(DisasContextBase *d= cbase, CPUState *cpu) } } =20 +static void aarch64_tr_disas_log(const DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, + 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11468,18 +11478,17 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, =20 gen_tb_end(tb, dc->base.num_insns); =20 + dc->base.tb->size =3D dc->pc - dc->base.pc_first; + dc->base.tb->icount =3D dc->base.num_insns; + #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); - log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, - 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); + aarch64_tr_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } #endif - dc->base.tb->size =3D dc->pc - dc->base.pc_first; - dc->base.tb->icount =3D dc->base.num_insns; } --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714762591677.169784840864; Wed, 6 Sep 2017 09:19:22 -0700 (PDT) Received: from localhost ([::1]:37007 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpd2v-0002MN-E2 for importer@patchew.org; Wed, 06 Sep 2017 12:19:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqw-0000Yd-5F for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:07:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqr-0002z0-79 for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:58 -0400 Received: from mail-pf0-x231.google.com ([2607:f8b0:400e:c00::231]:35367) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqq-0002tv-Ua for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:53 -0400 Received: by mail-pf0-x231.google.com with SMTP id g13so13484239pfm.2 for ; Wed, 06 Sep 2017 09:06:52 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ih77dH1LlHs+t4aUfyHaKRK6r0XUJB+LahRMCCHcq1E=; b=diQlWe4jN69bnvdHuAF59iYnA79GfQJH5EjXOdUNg9pzyABscHAsO4DYbKQbLEN2+l QMCMMZoA+CIw5eFhQzo6ejH19FCo2Eu4rWEaBWXB/AUKWg+dIwhiFA6ah5N/wZvsCVf9 ONTU4XJIleI02cUL61RuoMo+NOiv9iYhoPaW4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ih77dH1LlHs+t4aUfyHaKRK6r0XUJB+LahRMCCHcq1E=; b=pYx6adBfG3ZcohoUdybUwaEoRjwq/C9Kz4YqGIJc28w9+PDEtxGobrmKZ5H4d/W+4s C5b9bpKlqgs9MW8ylm/Aki43/4f3bIdIqkXcYDlgyUfGm6fr4OXrKqK1Cvmsb/SgxBMc WXWqV+AtYsafpITtO7ckQSMFWmvVYaFv38livSHpi87RiMJFfWo9bq3QP23eB0tLKp7I e4JPgKzS6NXZFYdz/qTIaxrwTwVAH+IroPQokAT8Ldz5WQD4MgNUX/3tj06KM7K14+Si 9HogqRgqmXUvMWw8sujA+knlA56OW+ZpaXeuDaIWKkJeTNfiaYUUpqrYDFAdwUSmvzG1 KXtg== X-Gm-Message-State: AHPjjUivmMVi+kmiGt5iishYz3efQbIxtC+O1n4ZgJ+8KFNSBdH4rtLi taxTHK+CFWiEoRbbxx3IMg== X-Google-Smtp-Source: ADKCNb4RtUgg2EYCldK5RVwd5zW93aOSbJMBK84ZsPmub8s4KJmtpQ0Ry0EqdBDKvpRQNPSqYuNRVA== X-Received: by 10.84.232.135 with SMTP id i7mr9160202plk.104.1504714011637; Wed, 06 Sep 2017 09:06:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:08 -0700 Message-Id: <20170906160612.22769-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::231 Subject: [Qemu-devel] [PULL 28/32] target/arm: [tcg] Port to generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Llu=C3=ADs=20Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Tested-by: Emilio G. Cota Reviewed-by: Emilio G. Cota Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002631325.22386.10348327185029496649.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.h | 8 +--- target/arm/translate-a64.c | 107 ++++++++---------------------------------= --- target/arm/translate.c | 109 +++++++++--------------------------------= ---- 3 files changed, 41 insertions(+), 183 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index e8dcec51ac..55d691db40 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -150,21 +150,15 @@ static void disas_set_insn_syndrome(DisasContext *s, = uint32_t syn) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, - TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); +extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } =20 -static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUStat= e *cpu, - TranslationBlock *tb) -{ -} - static inline void gen_a64_set_pc_im(uint64_t val) { } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1973a36462..25c6622825 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11262,6 +11262,11 @@ static int aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, return max_insns; } =20 +static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ + tcg_clear_temp_count(); +} + static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -11325,6 +11330,7 @@ static void aarch64_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu) } =20 dc->base.pc_next =3D dc->pc; + translator_loop_temp_check(&dc->base); } =20 static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) @@ -11391,6 +11397,9 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) break; } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next =3D dc->pc; } =20 static void aarch64_tr_disas_log(const DisasContextBase *dcbase, @@ -11403,92 +11412,12 @@ static void aarch64_tr_disas_log(const DisasConte= xtBase *dcbase, 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); } =20 -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - int max_insns; - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - - max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - max_insns =3D aarch64_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - - do { - dc->base.num_insns++; - aarch64_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { - gen_io_start(); - } - - aarch64_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabl= ed || - singlestep || dc->base.num_insns >=3D max_insn= s)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several time= s. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. - */ - } while (!dc->base.is_jmp); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - - aarch64_tr_tb_stop(&dc->base, cs); - - gen_tb_end(tb, dc->base.num_insns); - - dc->base.tb->size =3D dc->pc - dc->base.pc_first; - dc->base.tb->icount =3D dc->base.num_insns; - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - aarch64_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif -} +const TranslatorOps aarch64_translator_ops =3D { + .init_disas_context =3D aarch64_tr_init_disas_context, + .tb_start =3D aarch64_tr_tb_start, + .insn_start =3D aarch64_tr_insn_start, + .breakpoint_check =3D aarch64_tr_breakpoint_check, + .translate_insn =3D aarch64_tr_translate_insn, + .tb_stop =3D aarch64_tr_tb_stop, + .disas_log =3D aarch64_tr_disas_log, +}; diff --git a/target/arm/translate.c b/target/arm/translate.c index 2dca196e17..dabd5eb89a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11936,6 +11936,7 @@ static void arm_tr_tb_start(DisasContextBase *dcbas= e, CPUState *cpu) tcg_gen_movi_i32(tmp, 0); store_cpu_field(tmp, condexec_bits); } + tcg_clear_temp_count(); } =20 static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) @@ -12055,6 +12056,7 @@ static void arm_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) } =20 dc->base.pc_next =3D dc->pc; + translator_loop_temp_check(&dc->base); } =20 static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) @@ -12169,6 +12171,9 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) gen_goto_tb(dc, 1, dc->pc); } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next =3D dc->pc; } =20 static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) @@ -12180,99 +12185,29 @@ static void arm_tr_disas_log(const DisasContextBa= se *dcbase, CPUState *cpu) dc->thumb | (dc->sctlr_b << 1)); } =20 +static const TranslatorOps arm_translator_ops =3D { + .init_disas_context =3D arm_tr_init_disas_context, + .tb_start =3D arm_tr_tb_start, + .insn_start =3D arm_tr_insn_start, + .breakpoint_check =3D arm_tr_breakpoint_check, + .translate_insn =3D arm_tr_translate_insn, + .tb_stop =3D arm_tr_tb_stop, + .disas_log =3D arm_tr_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - DisasContext dc1, *dc =3D &dc1; - int max_insns; - - /* generate intermediate code */ + DisasContext dc; + const TranslatorOps *ops =3D &arm_translator_ops; =20 - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ +#ifdef TARGET_AARCH64 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_tr_tb_start(&dc->base, cs); - - do { - dc->base.num_insns++; - arm_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { - gen_io_start(); - } - - arm_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >=3D max_insns)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - - arm_tr_tb_stop(&dc->base, cs); - - gen_tb_end(tb, dc->base.num_insns); - - tb->size =3D dc->pc - dc->base.pc_first; - tb->icount =3D dc->base.num_insns; - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - arm_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); + ops =3D &aarch64_translator_ops; } #endif + + translator_loop(ops, &dc.base, cpu, tb); } =20 static const char *cpu_mode_names[16] =3D { --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504715789256569.6825212548462; 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X-Received-From: 2607:f8b0:400e:c00::236 Subject: [Qemu-devel] [PULL 29/32] target/arm: [a64] Move page and ss checks to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Since AArch64 uses a fixed-width ISA, we can pre-compute the number of insns remaining on the page. Also, we can check for single-step once. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 25c6622825..9017e30510 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11206,6 +11206,7 @@ static int aarch64_tr_init_disas_context(DisasConte= xtBase *dcbase, DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; ARMCPU *arm_cpu =3D arm_env_get_cpu(env); + int bound; =20 dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; @@ -11254,8 +11255,14 @@ static int aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->is_ldex =3D false; dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 - dc->next_page_start =3D - (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + /* Bound the number of insns to execute to those left on the page. */ + bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + + /* If architectural single step active, limit to 1. */ + if (dc->ss_active) { + bound =3D 1; + } + max_insns =3D MIN(max_insns, bound); =20 init_tmp_a64_array(dc); =20 @@ -11323,12 +11330,6 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) disas_a64_insn(env, dc); } =20 - if (dc->base.is_jmp =3D=3D DISAS_NEXT) { - if (dc->ss_active || dc->pc >=3D dc->next_page_start) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } - dc->base.pc_next =3D dc->pc; translator_loop_temp_check(&dc->base); } --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504715947215913.9436129868382; Wed, 6 Sep 2017 09:39:07 -0700 (PDT) Received: from localhost ([::1]:37105 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpdM2-0001ft-35 for importer@patchew.org; Wed, 06 Sep 2017 12:39:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42041) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqy-0000bM-Oq for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:07:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqu-00037Y-02 for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:07:00 -0400 Received: from mail-pf0-x22a.google.com ([2607:f8b0:400e:c00::22a]:34785) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqt-00032z-Pc for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:55 -0400 Received: by mail-pf0-x22a.google.com with SMTP id m1so13486478pfk.1 for ; Wed, 06 Sep 2017 09:06:55 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FaKvXHHGiYR75jbxerCmzlpe42rCvutIo5e8u1b0PMw=; b=Kic5+E7N7vpQER4GVCBTf0GZvBmRq4YrkTVLov5upn1+R2IyNEMYA2Qyt0gGn/FYtz fkAxmJRyD4gs66YqfqIIyTz9wA2L7yeZ5OtxhjqThbUpxzLbt1etouzaBL1wMIMm7nxJ ehk8NJ3EW93uxweCixsp4BNSG0Dnt+jaidMdI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FaKvXHHGiYR75jbxerCmzlpe42rCvutIo5e8u1b0PMw=; b=qXjxI+EHWbDDwDjbxe9xWKPxj1NzTqyTia0spSEVxjNOsFB1ZNO/TB7x/S0x+Vx7/9 evKSmwFeDuw25A6zV78LhprsvZbj+jhRg0QRktAi3fYPKwrMPL/wfD4SFH6MDAcwFpHb 1K3YPMZUmvXAEzSc5hSuOcYBUY8DbFFQc0fhMbyZb/BdLGgotjLtybZtRPi201/nQ74U j7XERSH2unn4uV41C6pQUMbM5vBr0lH3DnDF+mI1PhWTp2YQ+2UaT8HWGtPYHnFelZKK lDjcmKsWBG3zMmZNVrr4EUsTq+4KbeRjefqFbffKfEC2xaLasItGwBpjSvZoHISeb90z /MKA== X-Gm-Message-State: AHPjjUhePp3Pr5CL4IRkqA9tuYbSVvNgAUs4pRQnuHY5loXC3+tQ2n4A muG9xLhsFjgxTjCa3RiFJw== X-Google-Smtp-Source: ADKCNb5Lorwg+INXciyLUKwAJQXs4kg+VoBPUlKNKso5xHoQ/Of9fIsDxEsBqtX0y+XKbr5Oc+hzPA== X-Received: by 10.84.210.45 with SMTP id z42mr8814641plh.178.1504714014598; Wed, 06 Sep 2017 09:06:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:10 -0700 Message-Id: <20170906160612.22769-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22a Subject: [Qemu-devel] [PULL 30/32] target/arm: Move ss check to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Richard Henderson We can check for single-step just once. Reviewed-by: Emilio G. Cota Reviewed-by: Llu=C3=ADs Vilanova Signed-off-by: Richard Henderson --- target/arm/translate.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index dabd5eb89a..0dd24aad90 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11883,6 +11883,11 @@ static int arm_tr_init_disas_context(DisasContextB= ase *dcbase, dc->next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; =20 + /* If architectural single step active, limit to 1. */ + if (is_singlestepping(dc)) { + max_insns =3D 1; + } + cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); cpu_F0d =3D tcg_temp_new_i64(); @@ -12037,11 +12042,9 @@ static void arm_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ =20 - if (is_singlestepping(dc)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } else if ((dc->pc >=3D dc->next_page_start) || - ((dc->pc >=3D dc->next_page_start - 3) && - insn_crosses_page(env, dc))) { + if (dc->pc >=3D dc->next_page_start || + (dc->pc >=3D dc->next_page_start - 3 && + insn_crosses_page(env, dc))) { /* We want to stop the TB if the next insn starts in a new pag= e, * or if it spans between this page and the next. This means t= hat * if we're looking at the last halfword in the page we need to --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504714937996521.7396549724384; Wed, 6 Sep 2017 09:22:17 -0700 (PDT) Received: from localhost ([::1]:37018 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpd5j-0004gV-Vm for importer@patchew.org; Wed, 06 Sep 2017 12:22:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42059) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcr5-0000mL-KJ for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:07:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqv-00038L-HJ for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:07:07 -0400 Received: from mail-pf0-x22d.google.com ([2607:f8b0:400e:c00::22d]:34785) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqv-00037z-8x for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:57 -0400 Received: by mail-pf0-x22d.google.com with SMTP id m1so13486557pfk.1 for ; Wed, 06 Sep 2017 09:06:57 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wHWrXUvCoyl4+HP2sLpsgj4++zHbUrdBKSZ1VeXF5H0=; b=SCVQNdcJQoF/1YSCk3mBFhe6jUTH9iTXprE7kt11wdnEpAWsIQfgHh0Ui2HZI7qlZ5 lElbolg7SM0GWIvQH6X6wTnJs8xiCLfewt0hEC24kL22DKr9Fj2xY7+JQ/Xa/cmjuRY3 qW40RzRgygpEzW9xhlLdZ1kTUBH6R4ARAS23k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wHWrXUvCoyl4+HP2sLpsgj4++zHbUrdBKSZ1VeXF5H0=; b=GYnC9p4MZ9DJgKMHkfizQYm+1PB43JL5DYNtH6YcXhpSCwxwGGgaj/XREj/2IWoBwH PcALJ4H2e55N8N2ly/N2rJBWIkCEiN9W7b11R8L8zHU3fWMFL9cNxBoGD8UU6cku/EIe EJ1/cBk5Nq88FAPBcryAoZVyOYG/QN+OcBQpEv000AQdrWhLvYIfFim9UWyNgA3t9Ncb UAIz3N/H0IM35esXSA09RpzlYWyu+nbkH5qD0dSQVZXdhwSAU8gTXQsZ6bEbCd6vJ5Jn bGHXcEoXd6dFAGJ5S20NFkeEgNI7uvravvCw9HxHuMg4jzx8GG6Jq6rbbq2JlNYMS6RZ KrIg== X-Gm-Message-State: AHPjjUglZREOhZVxHNxd6pUgQiHgjsRSrVkkPLzXIxNyE7CS+wm5Q5Mn Jihu2Z6f0cp+Vl/DlZ9hHg== X-Google-Smtp-Source: ADKCNb6FEjNUMgTTJy1+VTQksaUiFoKkx9f4vQixkgwuPJ0mj+rupkL8gQzA3qL+jWqbVaBk96aWVg== X-Received: by 10.99.104.6 with SMTP id d6mr8232156pgc.168.1504714015929; Wed, 06 Sep 2017 09:06:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:11 -0700 Message-Id: <20170906160612.22769-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22d Subject: [Qemu-devel] [PULL 31/32] target/arm: Split out thumb_tr_translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson We need not check for ARM vs Thumb state in order to dispatch disassembly of every instruction. Tested-by: Emilio G. Cota Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.c | 121 ++++++++++++++++++++++++++++++++-------------= ---- 1 file changed, 80 insertions(+), 41 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0dd24aad90..9e7bfbcf0c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11981,11 +11981,8 @@ static bool arm_tr_breakpoint_check(DisasContextBa= se *dcbase, CPUState *cpu, return true; } =20 -static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +static bool arm_pre_translate_insn(DisasContext *dc) { - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUARMState *env =3D cpu->env_ptr; - #ifdef CONFIG_USER_ONLY /* Intercept jump to the magic kernel page. */ if (dc->pc >=3D 0xffff0000) { @@ -11993,7 +11990,7 @@ static void arm_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) conditional execution block. */ gen_exception_internal(EXCP_KERNEL_TRAP); dc->base.is_jmp =3D DISAS_NORETURN; - return; + return true; } #endif =20 @@ -12012,56 +12009,85 @@ static void arm_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); dc->base.is_jmp =3D DISAS_NORETURN; - return; + return true; } =20 - if (dc->thumb) { - disas_thumb_insn(env, dc); - if (dc->condexec_mask) { - dc->condexec_cond =3D (dc->condexec_cond & 0xe) - | ((dc->condexec_mask >> 4) & 1); - dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; - if (dc->condexec_mask =3D=3D 0) { - dc->condexec_cond =3D 0; - } - } - } else { - unsigned int insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); - dc->pc +=3D 4; - disas_arm_insn(dc, insn); - } + return false; +} =20 +static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc) +{ if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp =3D 0; } =20 - if (dc->base.is_jmp =3D=3D DISAS_NEXT) { - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several time= s. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. */ - - if (dc->pc >=3D dc->next_page_start || - (dc->pc >=3D dc->next_page_start - 3 && - insn_crosses_page(env, dc))) { - /* We want to stop the TB if the next insn starts in a new pag= e, - * or if it spans between this page and the next. This means t= hat - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit= insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - dc->base.is_jmp =3D DISAS_TOO_MANY; - } + /* Translation stops when a conditional branch is encountered. + * Otherwise the subsequent code could get translated several times. + * Also stop translation when a page boundary is reached. This + * ensures prefetch aborts occur at the right place. + * + * We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + if (dc->base.is_jmp =3D=3D DISAS_NEXT + && (dc->pc >=3D dc->next_page_start + || (dc->pc >=3D dc->next_page_start - 3 + && insn_crosses_page(env, dc)))) { + dc->base.is_jmp =3D DISAS_TOO_MANY; } =20 dc->base.pc_next =3D dc->pc; translator_loop_temp_check(&dc->base); } =20 +static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + unsigned int insn; + + if (arm_pre_translate_insn(dc)) { + return; + } + + insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->pc +=3D 4; + disas_arm_insn(dc, insn); + + arm_post_translate_insn(env, dc); +} + +static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + + if (arm_pre_translate_insn(dc)) { + return; + } + + disas_thumb_insn(env, dc); + + /* Advance the Thumb condexec condition. */ + if (dc->condexec_mask) { + dc->condexec_cond =3D ((dc->condexec_cond & 0xe) | + ((dc->condexec_mask >> 4) & 1)); + dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; + if (dc->condexec_mask =3D=3D 0) { + dc->condexec_cond =3D 0; + } + } + + arm_post_translate_insn(env, dc); +} + static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -12198,12 +12224,25 @@ static const TranslatorOps arm_translator_ops =3D= { .disas_log =3D arm_tr_disas_log, }; =20 +static const TranslatorOps thumb_translator_ops =3D { + .init_disas_context =3D arm_tr_init_disas_context, + .tb_start =3D arm_tr_tb_start, + .insn_start =3D arm_tr_insn_start, + .breakpoint_check =3D arm_tr_breakpoint_check, + .translate_insn =3D thumb_tr_translate_insn, + .tb_stop =3D arm_tr_tb_stop, + .disas_log =3D arm_tr_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { DisasContext dc; const TranslatorOps *ops =3D &arm_translator_ops; =20 + if (ARM_TBFLAG_THUMB(tb->flags)) { + ops =3D &thumb_translator_ops; + } #ifdef TARGET_AARCH64 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { ops =3D &aarch64_translator_ops; --=20 2.13.5 From nobody Sat May 4 22:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504715124821156.4402450999977; Wed, 6 Sep 2017 09:25:24 -0700 (PDT) Received: from localhost ([::1]:37032 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpd8l-0007fO-N0 for importer@patchew.org; Wed, 06 Sep 2017 12:25:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42025) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqx-0000aP-Q8 for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:07:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqw-0003A3-JE for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:59 -0400 Received: from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:37876) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqw-00038p-Dg for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:58 -0400 Received: by mail-pg0-x22c.google.com with SMTP id d8so15976971pgt.4 for ; Wed, 06 Sep 2017 09:06:58 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FcT2poeH+q1L1w+cKeuwQSS5u5zh9VSMqgupWpqmAAU=; b=WEZRS3Zj3SvIUobu2mj0kXoOJdlc+XtUNXXRUocuCXCAZJqyVlCBxmwo1khSzT91B4 53Uv8i8fMyhrSlBKr8Ch0VNw97Q8igCw0HmWV45diW+iCNZ5Lm1kUSSith2UrcHnM94y vlW/3hmVWIZyD4UnqXfn/2bZMUgrfVsscsm7M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FcT2poeH+q1L1w+cKeuwQSS5u5zh9VSMqgupWpqmAAU=; b=VSEcTrF3ckPeawb8guAkvWkJo4DU1jJHke5/e9z/wAZ/otOGfN6ocjGMppf4zYVB1q zH7DsazXR8wwggGdxAJQ1Q8uG4d7FNT6CptsOKcH5XNFDdA8hKdPGQ3UG5RfsDh1RBrZ FMIBZ+bUzdclpKra3aT4PyQ9rAfcyAGCTuM+1lbxC3w+woytHuVUzsIxtxKUcL1qdT3B 2qJIYEps1Z48kA7GsfZxM41nlRflcPZBUhZ7L3C1yEXauRkSGWqrjvm7X6EYCZAU29Pd 4h026RIlD3lrHz6Qc5cnO6AexqqCEPR+6ffbVvHK7TIkjTuW182dOLPHkvBTP8e6zfRV gHsg== X-Gm-Message-State: AHPjjUjqVX05vtbDfUZthRAzVqGSRD0LOgT5HAtvM/fsM/gYTzVv8bmZ qnO6/9LxLiJgrtQushslgg== X-Google-Smtp-Source: ADKCNb4cF16fLGKFoJyLYeJ/KvF8lFeCYeDOiMsbgS7lHT6WwCvBxdDZ3LOltSC4GIVcaDAtlUfykg== X-Received: by 10.99.2.208 with SMTP id 199mr8129299pgc.441.1504714017250; Wed, 06 Sep 2017 09:06:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:12 -0700 Message-Id: <20170906160612.22769-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PULL 32/32] target/arm: Perform per-insn cross-page check only for Thumb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson ARM is a fixed-length ISA and we can compute the page crossing condition exactly once during init_disas_context. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.c | 58 ++++++++++++++++++++++++++++------------------= ---- 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9e7bfbcf0c..6946e56a3a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11888,6 +11888,13 @@ static int arm_tr_init_disas_context(DisasContextB= ase *dcbase, max_insns =3D 1; } =20 + /* ARM is a fixed-length ISA. Bound the number of insns to execute + to those left on the page. */ + if (!dc->thumb) { + int bound =3D (dc->next_page_start - dc->base.pc_first) / 4; + max_insns =3D MIN(max_insns, bound); + } + cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); cpu_F0d =3D tcg_temp_new_i64(); @@ -12015,34 +12022,12 @@ static bool arm_pre_translate_insn(DisasContext *= dc) return false; } =20 -static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc) +static void arm_post_translate_insn(DisasContext *dc) { if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp =3D 0; } - - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several times. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. - * - * We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - if (dc->base.is_jmp =3D=3D DISAS_NEXT - && (dc->pc >=3D dc->next_page_start - || (dc->pc >=3D dc->next_page_start - 3 - && insn_crosses_page(env, dc)))) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - dc->base.pc_next =3D dc->pc; translator_loop_temp_check(&dc->base); } @@ -12061,7 +12046,10 @@ static void arm_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) dc->pc +=3D 4; disas_arm_insn(dc, insn); =20 - arm_post_translate_insn(env, dc); + arm_post_translate_insn(dc); + + /* ARM is a fixed-length ISA. We performed the cross-page check + in init_disas_context by adjusting max_insns. */ } =20 static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) @@ -12085,7 +12073,27 @@ static void thumb_tr_translate_insn(DisasContextBa= se *dcbase, CPUState *cpu) } } =20 - arm_post_translate_insn(env, dc); + arm_post_translate_insn(dc); + + /* Thumb is a variable-length ISA. Stop translation when the next insn + * will touch a new page. This ensures that prefetch aborts occur at + * the right place. + * + * We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + if (dc->base.is_jmp =3D=3D DISAS_NEXT + && (dc->pc >=3D dc->next_page_start + || (dc->pc >=3D dc->next_page_start - 3 + && insn_crosses_page(env, dc)))) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } } =20 static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) --=20 2.13.5