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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id h1sm3467646pfg.153.2017.09.06.07.49.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 07:49:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RK/3SaYDnTtoPHuQstqpOcx+UbVMkRmtrESkuekKT5w=; b=atvvmcMz2LAhNeuCrDFxOB/ZrYcYojkaIDWDaYpybGoHm8wRwOPV4ralVAWaXtWe+5 gitlPDXLfQF7zE7D/eTPpAfvH+kX+FNhPDbfUHffSQB3wt6ubi9T7NxoxgVQcczph6/m 4fW9OhdjEwmuGHjaZiTDNobnhT9HEGftk6vVw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RK/3SaYDnTtoPHuQstqpOcx+UbVMkRmtrESkuekKT5w=; b=dpKrdpz4zoQ8CIpaDH6TOr97hcx6aiPYt1w1xS8U+Nv9dSY6POWXgj+zeT7vkxk7ie AA1Yw2R4DilVXGf/IxISJOiYGmOjWYah542xFjUNWJ1ucphXCdFgnvoxF/Ka11TQplIU XHWXC/IbcrAHi0JmdFrPKWnRTGDhIhaQC/J5GQCmCm8FCuxBR8/1ZfxO9A3C949tgff8 lxVfZAn8ZspTneZvob/vkLzkK1o70wsB2nTgDWcXDRGFWlkJZNg3wqbz+tVPtciWom16 RD/ihHaMchultB1zAlWTSCkoH2oQPc+FDFkXMCTtGp2cV5BnsiCg2xxprqVnWLOH+Vy8 c4Rg== X-Gm-Message-State: AHPjjUhAYGAYvomAmYNqMm53FK4fFIabpXTpy3p/bygyp3KoRh86kDPP X3hT/kJKNO4H4oSejY2nhg== X-Google-Smtp-Source: ADKCNb7Ng5tqETixcAYxa9yKG23vqhjlgyp5/cn1ior8iRCMr7dxPcImKiBSsFBudQxdL1NKhlLKxQ== X-Received: by 10.98.27.73 with SMTP id b70mr7390084pfb.21.1504709386982; Wed, 06 Sep 2017 07:49:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 07:49:29 -0700 Message-Id: <20170906144940.30880-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906144940.30880-1-richard.henderson@linaro.org> References: <20170906144940.30880-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22d Subject: [Qemu-devel] [PULL 03/14] tcg: Implement implicit ordering semantics X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Pranith Kumar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Pranith Kumar Currently, we cannot use mttcg for running strong memory model guests on weak memory model hosts due to missing ordering semantics. We implicitly generate fence instructions for stronger guests if an ordering mismatch is detected. We generate fences only for the orders for which fence instructions are necessary, for example a fence is not necessary between a store and a subsequent load on x86 since its absence in the guest binary tells that ordering need not be ensured. Also note that if we find multiple subsequent fence instructions in the generated IR, we combine them in the TCG optimization pass. This patch allows us to boot an x86 guest on ARM64 hosts using mttcg. Signed-off-by: Pranith Kumar Message-Id: <20170829063313.10237-4-bobby.prani@gmail.com> Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 87f673ef49..688d91755b 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -28,6 +28,7 @@ #include "exec/exec-all.h" #include "tcg.h" #include "tcg-op.h" +#include "tcg-mo.h" #include "trace-tcg.h" #include "trace/mem.h" =20 @@ -2662,8 +2663,20 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val= , TCGv addr, #endif } =20 +static void tcg_gen_req_mo(TCGBar type) +{ +#ifdef TCG_GUEST_DEFAULT_MO + type &=3D TCG_GUEST_DEFAULT_MO; +#endif + type &=3D ~TCG_TARGET_DEFAULT_MO; + if (type) { + tcg_gen_mb(type | TCG_BAR_SC); + } +} + void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 0, 0); trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, trace_mem_get_info(memop, 0)); @@ -2672,6 +2685,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) =20 void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); memop =3D tcg_canonicalize_memop(memop, 0, 1); trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env, addr, trace_mem_get_info(memop, 1)); @@ -2680,6 +2694,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) =20 void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); if (memop & MO_SIGN) { @@ -2698,6 +2713,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) =20 void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) { + tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop); return; --=20 2.13.5