From nobody Tue Nov 4 13:11:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150413369377720.383428485487002; Wed, 30 Aug 2017 15:54:53 -0700 (PDT) Received: from localhost ([::1]:53111 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnBsp-0004hF-L4 for importer@patchew.org; Wed, 30 Aug 2017 18:54:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34723) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dnBr0-0003VA-51 for qemu-devel@nongnu.org; Wed, 30 Aug 2017 18:52:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dnBqy-0002Gh-LE for qemu-devel@nongnu.org; Wed, 30 Aug 2017 18:52:58 -0400 Received: from mail-qt0-x241.google.com ([2607:f8b0:400d:c0d::241]:35788) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dnBqy-0002GW-Fc for qemu-devel@nongnu.org; Wed, 30 Aug 2017 18:52:56 -0400 Received: by mail-qt0-x241.google.com with SMTP id u11so6363254qtu.2 for ; Wed, 30 Aug 2017 15:52:56 -0700 (PDT) Received: from yoga.offpageads.com ([181.93.89.178]) by smtp.gmail.com with ESMTPSA id 54sm4449874qts.31.2017.08.30.15.52.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Aug 2017 15:52:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yi+pjInDxGAOIHNZmFO102gPGjOYyRgoxki9IDvo6Fc=; b=rHv0g5D5zN+jyNaJstgFnLVmGLTwgQIPc4eN0cwEtnKX8hoSDI5cppDD0b8qa2Dm+K fN4M9pjOYCsqf8kgO+DDYhYfynOG0ivbTHPowJ6Ugnr9gEEZDhVUUaHAv6iwv67MNOSQ 414YlSg0wZ75SYUL8hnpXfsmIayjMO/M4OaueZAsrmv8XqLaIzq9pn9hA2sy8GSNXVRw vCOFEisRWDdJOEyTa07TT4tLXqC4ZP780hdmMKWsLoQVq8i7loKQq8xGypCun+QFdtcN azdwsvhxVN4q3hv2wJXmTDe0oodemmyCN04HNSF0KwPbb5ltWdtC484230n1NJ5Xa/i6 pbzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yi+pjInDxGAOIHNZmFO102gPGjOYyRgoxki9IDvo6Fc=; b=ZP5E9UfNpEtKKKqTB4xmH2EMQuDYsvWgDiA2NQrQknjIc+oUQbTQwHpcYNSMHrkq7N mDrpP8jlfkm31ujl5aQR5Xj6VTIs0l8JnnRptPQ3W+tY/Kv3ryoNLu5lMvcJraK89GiK 8TaXv3aMd1uRkZfeUQcUKh1Mk4+NCkW31CseOB76vUcLc2wj3n2UovFAQqpXPKh5pfBu oLC74UN/aYo5Vuvl2x6AaVDn3bUJzlKi0YDDMVnQXFFZ9KPKCZabmD85xcqudIr2kQ6N CSLgG7LDc/M8EjHcjWPKf2eNlhYMCAyNV9PqW3NaCP+cwGCtAoiEFJohZ+K/ScpnbJ/E xe1w== X-Gm-Message-State: AHYfb5hcY/kL55MBgVrjiG80ibU14il+UNj29UYzsAsY8s3Udv37CKU4 1SkdRHvkDfdN9g== X-Received: by 10.200.44.106 with SMTP id e39mr4299646qta.140.1504133575855; Wed, 30 Aug 2017 15:52:55 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Igor Mammedov , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aurelien Jarno , Eduardo Habkost , Marcel Apfelbaum , James Hogan , Yongbok Kim Date: Wed, 30 Aug 2017 19:52:23 -0300 Message-Id: <20170830225225.27925-6-f4bug@amsat.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170830225225.27925-1-f4bug@amsat.org> References: <20170830225225.27925-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::241 Subject: [Qemu-devel] [PATCH v2 5/7] mips: MIPSCPU model subclasses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Igor Mammedov Register separate QOM types for each mips cpu model, so it would be possible to reuse generic CPU creation routines. Signed-off-by: Igor Mammedov Signed-off-by: Philippe Mathieu-Daud=C3=A9 [PMD: use internal.h, use void* to hold cpu_def in MIPSCPUClass, mark MIPSCPU abstract] Tested-by: James Hogan Reviewed-by: Eduardo Habkost --- target/mips/cpu-qom.h | 1 + target/mips/internal.h | 59 ++++++++++++++++++++++++++++++++++++++++= ++++ target/mips/cpu.c | 53 ++++++++++++++++++++++++++++++++++++++- target/mips/translate.c | 13 +++++----- target/mips/translate_init.c | 58 ++--------------------------------------= --- 5 files changed, 120 insertions(+), 64 deletions(-) diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 3f5bf23823..085711d8f9 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -49,6 +49,7 @@ typedef struct MIPSCPUClass { =20 DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); + const void *cpu_def; } MIPSCPUClass; =20 typedef struct MIPSCPU MIPSCPU; diff --git a/target/mips/internal.h b/target/mips/internal.h index cf4c9db427..45ded3484c 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -7,6 +7,65 @@ #ifndef MIPS_INTERNAL_H #define MIPS_INTERNAL_H =20 + +/* MMU types, the first four entries have the same layout as the + CP0C0_MT field. */ +enum mips_mmu_types { + MMU_TYPE_NONE, + MMU_TYPE_R4000, + MMU_TYPE_RESERVED, + MMU_TYPE_FMT, + MMU_TYPE_R3000, + MMU_TYPE_R6000, + MMU_TYPE_R8000 +}; + +struct mips_def_t { + const char *name; + int32_t CP0_PRid; + int32_t CP0_Config0; + int32_t CP0_Config1; + int32_t CP0_Config2; + int32_t CP0_Config3; + int32_t CP0_Config4; + int32_t CP0_Config4_rw_bitmask; + int32_t CP0_Config5; + int32_t CP0_Config5_rw_bitmask; + int32_t CP0_Config6; + int32_t CP0_Config7; + target_ulong CP0_LLAddr_rw_bitmask; + int CP0_LLAddr_shift; + int32_t SYNCI_Step; + int32_t CCRes; + int32_t CP0_Status_rw_bitmask; + int32_t CP0_TCStatus_rw_bitmask; + int32_t CP0_SRSCtl; + int32_t CP1_fcr0; + int32_t CP1_fcr31_rw_bitmask; + int32_t CP1_fcr31; + int32_t MSAIR; + int32_t SEGBITS; + int32_t PABITS; + int32_t CP0_SRSConf0_rw_bitmask; + int32_t CP0_SRSConf0; + int32_t CP0_SRSConf1_rw_bitmask; + int32_t CP0_SRSConf1; + int32_t CP0_SRSConf2_rw_bitmask; + int32_t CP0_SRSConf2; + int32_t CP0_SRSConf3_rw_bitmask; + int32_t CP0_SRSConf3; + int32_t CP0_SRSConf4_rw_bitmask; + int32_t CP0_SRSConf4; + int32_t CP0_PageGrain_rw_bitmask; + int32_t CP0_PageGrain; + target_ulong CP0_EBaseWG_rw_bitmask; + int insn_flags; + enum mips_mmu_types mmu_type; +}; + +extern const struct mips_def_t mips_defs[]; +extern const int mips_defs_number; + enum CPUMIPSMSADataFormat { DF_BYTE =3D 0, DF_HALF, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e3ef835599..84b6f8bf68 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -146,12 +146,37 @@ static void mips_cpu_initfn(Object *obj) CPUState *cs =3D CPU(obj); MIPSCPU *cpu =3D MIPS_CPU(obj); CPUMIPSState *env =3D &cpu->env; + MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(obj); =20 cs->env_ptr =3D env; =20 if (tcg_enabled()) { mips_tcg_init(); } + + if (mcc->cpu_def) { + env->cpu_model =3D mcc->cpu_def; + } +} + +static char *mips_cpu_type_name(const char *cpu_model) +{ + return g_strdup_printf("%s-" TYPE_MIPS_CPU, cpu_model); +} + +static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) +{ + ObjectClass *oc; + char *typename; + + if (cpu_model =3D=3D NULL) { + return NULL; + } + + typename =3D mips_cpu_type_name(cpu_model); + oc =3D object_class_by_name(typename); + g_free(typename); + return oc; } =20 static void mips_cpu_class_init(ObjectClass *c, void *data) @@ -166,6 +191,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) mcc->parent_reset =3D cc->reset; cc->reset =3D mips_cpu_reset; =20 + cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; cc->do_interrupt =3D mips_cpu_do_interrupt; cc->cpu_exec_interrupt =3D mips_cpu_exec_interrupt; @@ -193,14 +219,39 @@ static const TypeInfo mips_cpu_type_info =3D { .parent =3D TYPE_CPU, .instance_size =3D sizeof(MIPSCPU), .instance_init =3D mips_cpu_initfn, - .abstract =3D false, + .abstract =3D true, .class_size =3D sizeof(MIPSCPUClass), .class_init =3D mips_cpu_class_init, }; =20 +static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data) +{ + MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(oc); + mcc->cpu_def =3D data; +} + +static void mips_register_cpudef_type(const struct mips_def_t *def) +{ + char *typename =3D mips_cpu_type_name(def->name); + TypeInfo ti =3D { + .name =3D typename, + .parent =3D TYPE_MIPS_CPU, + .class_init =3D mips_cpu_cpudef_class_init, + .class_data =3D (void *)def, + }; + + type_register(&ti); + g_free(typename); +} + static void mips_cpu_register_types(void) { + int i; + type_register_static(&mips_cpu_type_info); + for (i =3D 0; i < mips_defs_number; i++) { + mips_register_cpudef_type(&mips_defs[i]); + } } =20 type_init(mips_cpu_register_types) diff --git a/target/mips/translate.c b/target/mips/translate.c index 94c38e8755..f7128bc91d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20525,16 +20525,15 @@ void cpu_mips_realize_env(CPUMIPSState *env) =20 MIPSCPU *cpu_mips_init(const char *cpu_model) { + ObjectClass *oc; MIPSCPU *cpu; - CPUMIPSState *env; - const mips_def_t *def; =20 - def =3D cpu_mips_find_by_name(cpu_model); - if (!def) + oc =3D cpu_class_by_name(TYPE_MIPS_CPU, cpu_model); + if (oc =3D=3D NULL) { return NULL; - cpu =3D MIPS_CPU(object_new(TYPE_MIPS_CPU)); - env =3D &cpu->env; - env->cpu_model =3D def; + } + + cpu =3D MIPS_CPU(object_new(object_class_get_name(oc))); =20 object_property_set_bool(OBJECT(cpu), true, "realized", NULL); =20 diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c index 255d25bacd..8bbded46c4 100644 --- a/target/mips/translate_init.c +++ b/target/mips/translate_init.c @@ -51,64 +51,9 @@ #define MIPS_CONFIG5 \ ((0 << CP0C5_M)) =20 -/* MMU types, the first four entries have the same layout as the - CP0C0_MT field. */ -enum mips_mmu_types { - MMU_TYPE_NONE, - MMU_TYPE_R4000, - MMU_TYPE_RESERVED, - MMU_TYPE_FMT, - MMU_TYPE_R3000, - MMU_TYPE_R6000, - MMU_TYPE_R8000 -}; - -struct mips_def_t { - const char *name; - int32_t CP0_PRid; - int32_t CP0_Config0; - int32_t CP0_Config1; - int32_t CP0_Config2; - int32_t CP0_Config3; - int32_t CP0_Config4; - int32_t CP0_Config4_rw_bitmask; - int32_t CP0_Config5; - int32_t CP0_Config5_rw_bitmask; - int32_t CP0_Config6; - int32_t CP0_Config7; - target_ulong CP0_LLAddr_rw_bitmask; - int CP0_LLAddr_shift; - int32_t SYNCI_Step; - int32_t CCRes; - int32_t CP0_Status_rw_bitmask; - int32_t CP0_TCStatus_rw_bitmask; - int32_t CP0_SRSCtl; - int32_t CP1_fcr0; - int32_t CP1_fcr31_rw_bitmask; - int32_t CP1_fcr31; - int32_t MSAIR; - int32_t SEGBITS; - int32_t PABITS; - int32_t CP0_SRSConf0_rw_bitmask; - int32_t CP0_SRSConf0; - int32_t CP0_SRSConf1_rw_bitmask; - int32_t CP0_SRSConf1; - int32_t CP0_SRSConf2_rw_bitmask; - int32_t CP0_SRSConf2; - int32_t CP0_SRSConf3_rw_bitmask; - int32_t CP0_SRSConf3; - int32_t CP0_SRSConf4_rw_bitmask; - int32_t CP0_SRSConf4; - int32_t CP0_PageGrain_rw_bitmask; - int32_t CP0_PageGrain; - target_ulong CP0_EBaseWG_rw_bitmask; - int insn_flags; - enum mips_mmu_types mmu_type; -}; - /*************************************************************************= ****/ /* MIPS CPU definitions */ -static const mips_def_t mips_defs[] =3D +const mips_def_t mips_defs[] =3D { { .name =3D "4Kc", @@ -808,6 +753,7 @@ static const mips_def_t mips_defs[] =3D =20 #endif }; +const int mips_defs_number =3D ARRAY_SIZE(mips_defs); =20 static const mips_def_t *cpu_mips_find_by_name (const char *name) { --=20 2.14.1