From nobody Wed Nov 5 08:43:49 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504111232610904.6710989341291; Wed, 30 Aug 2017 09:40:32 -0700 (PDT) Received: from localhost ([::1]:51554 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dn62Y-0001sc-Da for importer@patchew.org; Wed, 30 Aug 2017 12:40:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50233) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dn5yp-0007K5-C8 for qemu-devel@nongnu.org; Wed, 30 Aug 2017 12:36:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dn5ym-0006Ma-LU for qemu-devel@nongnu.org; Wed, 30 Aug 2017 12:36:39 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:55705 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dn5ym-0006LM-FM for qemu-devel@nongnu.org; Wed, 30 Aug 2017 12:36:36 -0400 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v7UGTHjX091217 for ; Wed, 30 Aug 2017 12:36:35 -0400 Received: from e06smtp12.uk.ibm.com (e06smtp12.uk.ibm.com [195.75.94.108]) by mx0b-001b2d01.pphosted.com with ESMTP id 2cp0gja0mv-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 30 Aug 2017 12:36:35 -0400 Received: from localhost by e06smtp12.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 30 Aug 2017 17:36:31 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v7UGaVTZ21037070; Wed, 30 Aug 2017 16:36:31 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A3D0A52041; Wed, 30 Aug 2017 16:31:57 +0100 (BST) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTPS id 75F095203F; Wed, 30 Aug 2017 16:31:57 +0100 (BST) From: Halil Pasic To: Cornelia Huck Date: Wed, 30 Aug 2017 18:36:09 +0200 X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170830163609.50260-1-pasic@linux.vnet.ibm.com> References: <20170830163609.50260-1-pasic@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 17083016-0008-0000-0000-000004917049 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17083016-0009-0000-0000-00001E21C2DA Message-Id: <20170830163609.50260-10-pasic@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-08-30_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1708300251 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH 9/9] s390x: factor out common ioinst handler logic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dong Jia Shi , Halil Pasic , Pierre Morel , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some of ioinst the handlers look very much the same: they basically delegate the work to the appropriate css function (doing some always the same stuff before and after the call to the appropriate css function). Let us create a template and get rid of some code. Signed-off-by: Halil Pasic Suggested-by: Marc Hartmayer Reviewed-by: Pierre Morel --- The handlers for MSCH and SSCH look very similar to our template too. It's just that there is one more parameter to the corresponding css function. Maybe one could do something to unify that too (e.g. some crazy macro) but I don't think it's worth the effort. Another idea was to make the two corresponding functions single argument too (by Dong Jia). --- target/s390x/ioinst.c | 77 ++++++++++-------------------------------------= ---- 1 file changed, 14 insertions(+), 63 deletions(-) diff --git a/target/s390x/ioinst.c b/target/s390x/ioinst.c index a286495219..6583e5216d 100644 --- a/target/s390x/ioinst.c +++ b/target/s390x/ioinst.c @@ -37,7 +37,10 @@ int ioinst_disassemble_sch_ident(uint32_t value, int *m,= int *cssid, int *ssid, return 0; } =20 -void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1) +/* many ionst handlers look the same: they just delegate to a some css fun= c */ +static void ioinst_handler_template_sch(S390CPU *cpu, uint64_t reg1, + const char *iname, + void (*handler_css)(SubchDev *)) { int cssid, ssid, schid, m; SubchDev *sch; @@ -46,14 +49,14 @@ void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1) program_interrupt(&cpu->env, PGM_OPERAND, 4); return; } - trace_ioinst_sch_id("xsch", cssid, ssid, schid); + trace_ioinst_sch_id(iname, cssid, ssid, schid); sch =3D css_find_subch(m, cssid, ssid, schid); if (!sch || !css_subch_visible(sch)) { setcc(cpu, 3); return; } css_subch_clear_iret(sch); - css_do_xsch(sch); + handler_css(sch); if (sch->iret.pgm_chk) { program_interrupt(&cpu->env, sch->iret.irq_code, 4); return; @@ -61,52 +64,19 @@ void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1) setcc(cpu, sch->iret.cc); } =20 -void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1) +void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1) { - int cssid, ssid, schid, m; - SubchDev *sch; + ioinst_handler_template_sch(cpu, reg1, "xsch", css_do_xsch); +} =20 - if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) { - program_interrupt(&cpu->env, PGM_OPERAND, 4); - return; - } - trace_ioinst_sch_id("csch", cssid, ssid, schid); - sch =3D css_find_subch(m, cssid, ssid, schid); - if (!sch || !css_subch_visible(sch)) { - setcc(cpu, 3); - return; - } - css_subch_clear_iret(sch); - css_do_csch(sch); - if (sch->iret.pgm_chk) { - program_interrupt(&cpu->env, sch->iret.irq_code, 4); - return; - } - setcc(cpu, sch->iret.cc); +void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1) +{ + ioinst_handler_template_sch(cpu, reg1, "csch", css_do_csch); } =20 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1) { - int cssid, ssid, schid, m; - SubchDev *sch; - - if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) { - program_interrupt(&cpu->env, PGM_OPERAND, 4); - return; - } - trace_ioinst_sch_id("hsch", cssid, ssid, schid); - sch =3D css_find_subch(m, cssid, ssid, schid); - if (!sch || !css_subch_visible(sch)) { - setcc(cpu, 3); - return; - } - css_subch_clear_iret(sch); - css_do_hsch(sch); - if (sch->iret.pgm_chk) { - program_interrupt(&cpu->env, sch->iret.irq_code, 4); - return; - } - setcc(cpu, sch->iret.cc); + ioinst_handler_template_sch(cpu, reg1, "hsch", css_do_hsch); } =20 static int ioinst_schib_valid(SCHIB *schib) @@ -720,26 +690,7 @@ void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, u= int64_t reg2, =20 void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1) { - int cssid, ssid, schid, m; - SubchDev *sch; - - if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) { - program_interrupt(&cpu->env, PGM_OPERAND, 4); - return; - } - trace_ioinst_sch_id("rsch", cssid, ssid, schid); - sch =3D css_find_subch(m, cssid, ssid, schid); - if (!sch || !css_subch_visible(sch)) { - setcc(cpu, 3); - return; - } - css_subch_clear_iret(sch); - css_do_rsch(sch); - if (sch->iret.pgm_chk) { - program_interrupt(&cpu->env, sch->iret.irq_code, 4); - return; - } - setcc(cpu, sch->iret.cc); + ioinst_handler_template_sch(cpu, reg1, "rsch", css_do_rsch); } =20 #define RCHP_REG1_RES(_reg) (_reg & 0x00000000ff00ff00) --=20 2.13.5