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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g8yP4qkSZz+fxQ+4zsqNUcLQi6JaL8uvacalBHt62FU=; b=YfBHJhA+0hZdSNFEXbzltGqxC4ZtRjAM8SRblzowFlMsMi0tivhAQjCG0hWfgohfFk tE+8UWzsaiDg6YKGIzc2aoRACngKaZ/Aji6/53JuIOKKR8CYpidXP2NLlo2iPTBUhpUU 1DtOVujDwPaofXrsG0uoYrXiGR12On3ypPZHw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g8yP4qkSZz+fxQ+4zsqNUcLQi6JaL8uvacalBHt62FU=; b=k8YFRxYVjA0D/Nckl8Ii09Q9AZRjx9JpgV2+n5J76lZNNL8/khQVocw5besoKyB7y7 6VT2Yuzu6uX4eaYpc293Zx2/kFEm1F1aTkD3NRGY5dYyUMoUEFWqJMVPGEP4Gr3dRg39 +5DZ2cHqtx3vqweUzCibKqgsrfS8UoMlZfROA13+D7PtslUo6c/9qgWowQR98EovBrZ2 UlT5d8hQ6wOoxpLMn5lu+/iR1WfBSNLdnMOQLcm0hR7R2JajvnqrMN71s6d/9eMLIuD0 1pSXH1uWzVNGkqp1k+9FFwtb07w4hPK3oKIgWAGotXwDoMKgHRh9WnKSBSVbIjKkYWfM X4bw== X-Gm-Message-State: AHYfb5hyZ+mCnfBOD9epVlAqU9aYUQO9TBc9uRq47Se1fLx1E2434/is J7V5Qb2kDc3x+XeBsZY2Pg== X-Received: by 10.84.193.131 with SMTP id f3mr2002790pld.62.1504039691525; Tue, 29 Aug 2017 13:48:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:57 -0700 Message-Id: <20170829204759.6853-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PATCH 6/8] tcg/s390: Use distinct-operands facility X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This allows using a 3-operand insn form for some arithmetic, logicals and shifts. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.inc.c | 118 +++++++++++++++++++++++++++++++++++-------= ---- 2 files changed, 91 insertions(+), 28 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 957f0c0afe..1b5eb22c26 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -58,6 +58,7 @@ typedef enum TCGReg { #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34)) #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND +#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND =20 extern uint64_t s390_facilities; =20 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 5414c9d879..a80b07db65 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -159,6 +159,16 @@ typedef enum S390Opcode { =20 RRF_LOCR =3D 0xb9f2, RRF_LOCGR =3D 0xb9e2, + RRF_NRK =3D 0xb9f4, + RRF_NGRK =3D 0xb9e4, + RRF_ORK =3D 0xb9f6, + RRF_OGRK =3D 0xb9e6, + RRF_SRK =3D 0xb9f9, + RRF_SGRK =3D 0xb9e9, + RRF_SLRK =3D 0xb9fb, + RRF_SLGRK =3D 0xb9eb, + RRF_XRK =3D 0xb9f7, + RRF_XGRK =3D 0xb9e7, =20 RR_AR =3D 0x1a, RR_ALR =3D 0x1e, @@ -179,8 +189,11 @@ typedef enum S390Opcode { RSY_RLL =3D 0xeb1d, RSY_RLLG =3D 0xeb1c, RSY_SLLG =3D 0xeb0d, + RSY_SLLK =3D 0xebdf, RSY_SRAG =3D 0xeb0a, + RSY_SRAK =3D 0xebdc, RSY_SRLG =3D 0xeb0c, + RSY_SRLK =3D 0xebde, =20 RS_SLL =3D 0x89, RS_SRA =3D 0x8a, @@ -1065,23 +1078,29 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, case TCG_COND_GEU: do_geu: /* We need "real" carry semantics, so use SUBTRACT LOGICAL - instead of COMPARE LOGICAL. This needs an extra move. */ - tcg_out_mov(s, type, TCG_TMP0, c1); + instead of COMPARE LOGICAL. This may need an extra move. */ if (c2const) { - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_mov(s, type, TCG_TMP0, c1); if (type =3D=3D TCG_TYPE_I32) { tcg_out_insn(s, RIL, SLFI, TCG_TMP0, c2); } else { tcg_out_insn(s, RIL, SLGFI, TCG_TMP0, c2); } + } else if (s390_facilities & FACILITY_DISTINCT_OPS) { + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_insn(s, RRF, SLRK, TCG_TMP0, c1, c2); + } else { + tcg_out_insn(s, RRF, SLGRK, TCG_TMP0, c1, c2); + } } else { + tcg_out_mov(s, type, TCG_TMP0, c1); if (type =3D=3D TCG_TYPE_I32) { tcg_out_insn(s, RR, SLR, TCG_TMP0, c2); } else { tcg_out_insn(s, RRE, SLGR, TCG_TMP0, c2); } - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); } + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); tcg_out_insn(s, RRE, ALCGR, dest, dest); return; =20 @@ -1648,7 +1667,7 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - S390Opcode op; + S390Opcode op, op2; TCGArg a0, a1, a2; =20 switch (opc) { @@ -1753,29 +1772,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, if (const_args[2]) { a2 =3D -a2; goto do_addi_32; + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RR, SR, a0, a2); + } else { + tcg_out_insn(s, RRF, SRK, a0, a1, a2); } - tcg_out_insn(s, RR, SR, args[0], args[2]); break; =20 case INDEX_op_and_i32: + a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; if (const_args[2]) { - tgen_andi(s, TCG_TYPE_I32, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen_andi(s, TCG_TYPE_I32, a0, a2); + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RR, NR, a0, a2); } else { - tcg_out_insn(s, RR, NR, args[0], args[2]); + tcg_out_insn(s, RRF, NRK, a0, a1, a2); } break; case INDEX_op_or_i32: + a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; if (const_args[2]) { - tgen64_ori(s, args[0], args[2] & 0xffffffff); + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen64_ori(s, a0, a2); + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RR, OR, a0, a2); } else { - tcg_out_insn(s, RR, OR, args[0], args[2]); + tcg_out_insn(s, RRF, ORK, a0, a1, a2); } break; case INDEX_op_xor_i32: + a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; if (const_args[2]) { - tgen64_xori(s, args[0], args[2] & 0xffffffff); - } else { + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen64_xori(s, a0, a2); + } else if (a0 =3D=3D a1) { tcg_out_insn(s, RR, XR, args[0], args[2]); + } else { + tcg_out_insn(s, RRF, XRK, a0, a1, a2); } break; =20 @@ -1804,18 +1838,31 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, =20 case INDEX_op_shl_i32: op =3D RS_SLL; + op2 =3D RSY_SLLK; do_shift32: - if (const_args[2]) { - tcg_out_sh32(s, op, args[0], TCG_REG_NONE, args[2]); + a0 =3D args[0], a1 =3D args[1], a2 =3D (int32_t)args[2]; + if (a0 =3D=3D a1) { + if (const_args[2]) { + tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); + } else { + tcg_out_sh32(s, op, a0, a2, 0); + } } else { - tcg_out_sh32(s, op, args[0], args[2], 0); + /* Using tcg_out_sh64 here for the format; it is a 32-bit shif= t. */ + if (const_args[2]) { + tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); + } else { + tcg_out_sh64(s, op2, a0, a1, a2, 0); + } } break; case INDEX_op_shr_i32: op =3D RS_SRL; + op2 =3D RSY_SRLK; goto do_shift32; case INDEX_op_sar_i32: op =3D RS_SRA; + op2 =3D RSY_SRAK; goto do_shift32; =20 case INDEX_op_rotl_i32: @@ -1957,30 +2004,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, if (const_args[2]) { a2 =3D -a2; goto do_addi_64; + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RRE, SGR, a0, a2); } else { - tcg_out_insn(s, RRE, SGR, args[0], args[2]); + tcg_out_insn(s, RRF, SGRK, a0, a1, a2); } break; =20 case INDEX_op_and_i64: + a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); - } else { + } else if (a0 =3D=3D a1) { tcg_out_insn(s, RRE, NGR, args[0], args[2]); + } else { + tcg_out_insn(s, RRF, NGRK, a0, a1, a2); } break; case INDEX_op_or_i64: + a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { - tgen64_ori(s, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen64_ori(s, a0, a2); + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RRE, OGR, a0, a2); } else { - tcg_out_insn(s, RRE, OGR, args[0], args[2]); + tcg_out_insn(s, RRF, OGRK, a0, a1, a2); } break; case INDEX_op_xor_i64: + a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { - tgen64_xori(s, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen64_xori(s, a0, a2); + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RRE, XGR, a0, a2); } else { - tcg_out_insn(s, RRE, XGR, args[0], args[2]); + tcg_out_insn(s, RRF, XGRK, a0, a1, a2); } break; =20 @@ -2168,6 +2229,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef r_rC =3D { .args_ct_str =3D { "r", "rC" } = }; static const TCGTargetOpDef r_rZ =3D { .args_ct_str =3D { "r", "rZ" } = }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; + static const TCGTargetOpDef r_r_rM =3D { .args_ct_str =3D { "r", "r", = "rM" } }; static const TCGTargetOpDef r_0_r =3D { .args_ct_str =3D { "r", "0", "= r" } }; static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; @@ -2211,7 +2273,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &r_r_ri; case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_0_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); =20 case INDEX_op_mul_i32: /* If we have the general-instruction-extensions, then we have @@ -2227,32 +2289,32 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) OI[LH][LH] instructions. By rejecting certain negative ranges, the immediate load plus the reg-reg OR is smaller. */ return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_ri + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_= 0_ri) : &r_0_rN); case INDEX_op_or_i64: return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_rM + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_= 0_rM) : &r_0_rN); =20 case INDEX_op_xor_i32: /* Without EXT_IMM, no immediates are supported. Otherwise, rejecting certain negative ranges leads to smaller code. */ return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_ri + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_= 0_ri) : &r_0_r); case INDEX_op_xor_i64: return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_rM + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_= 0_rM) : &r_0_r); =20 case INDEX_op_and_i32: case INDEX_op_and_i64: - return &r_0_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); =20 case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return &r_0_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); =20 case INDEX_op_shl_i64: case INDEX_op_shr_i64: --=20 2.13.5