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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0RJY26L+wluBLiCwy06P1bcCFRjSUiVl+17C88pqpyA=; b=a/x906QphU6HJBjjrSVfTSlMgTMyWNm9VBxZptmPwjJe/51dtMdkjD8xhkGAsGkME6 JLGpM5EhR5nHIrMJbCfXnecq73WPLskqYCb6Yn0xWcE32gECqJRwmA9Wu3SCNTI/FBTj FYShmTgrNwffSx9Dr+WW3OJ57FKPNjdf/zdPw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0RJY26L+wluBLiCwy06P1bcCFRjSUiVl+17C88pqpyA=; b=EEV9i6bsVdZPrP9jeHVPHbFCi82ERdyDqkLWehs4ku0NPvDmMG2NfuR97xRaN/5FaM JpktTW7o3P3f7kZuAKMorGrbTZVGgApJ/wra2NJIGmPj87KgrO41MFvwERqxlzM4lRwm AEhNy5Fo1X6lE/dwlw8mia5jHcwFH8MkUEnu+JHtYoc3UVOuJf5MXy5Gu71CjxbG7ygq 48dL/D+nv16/13aqQBpuGKAiG74vsmP9JRP410nZrpoMXjs0uuLxPZFLTevPi7R9IX14 AvjrdiVyxoEvc6M5NmZwOKubkHenlg4smnm4fCB2jmWV/Jgcwg3N0BHovHqrrWAHhj9o zzCg== X-Gm-Message-State: AHYfb5gdc8yLt7LTtpLDLKu5t7Xr0A0aavDszr2uVL1tTB7BG2IoWx09 gA9zlNRQpCsrVt9VK+tioQ== X-Received: by 10.98.59.194 with SMTP id w63mr1665905pfj.44.1504039687194; Tue, 29 Aug 2017 13:48:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:54 -0700 Message-Id: <20170829204759.6853-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::231 Subject: [Qemu-devel] [PATCH 3/8] tcg/s390: Merge muli facilities check to tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 45 +++++++++++++++++++++++++------------------= -- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index e075b4844a..ff3f644f8e 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -38,12 +38,13 @@ a 32-bit displacement here Just In Case. */ #define USE_LONG_BRANCHES 0 =20 -#define TCG_CT_CONST_MULI 0x100 -#define TCG_CT_CONST_ORI 0x200 -#define TCG_CT_CONST_XORI 0x400 -#define TCG_CT_CONST_U31 0x800 -#define TCG_CT_CONST_ADLI 0x1000 -#define TCG_CT_CONST_ZERO 0x2000 +#define TCG_CT_CONST_S16 0x100 +#define TCG_CT_CONST_S32 0x200 +#define TCG_CT_CONST_ORI 0x400 +#define TCG_CT_CONST_XORI 0x800 +#define TCG_CT_CONST_U31 0x1000 +#define TCG_CT_CONST_ADLI 0x2000 +#define TCG_CT_CONST_ZERO 0x4000 =20 /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ @@ -388,8 +389,11 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, case 'A': ct->ct |=3D TCG_CT_CONST_ADLI; break; - case 'K': - ct->ct |=3D TCG_CT_CONST_MULI; + case 'I': + ct->ct |=3D TCG_CT_CONST_S16; + break; + case 'J': + ct->ct |=3D TCG_CT_CONST_S32; break; case 'O': ct->ct |=3D TCG_CT_CONST_ORI; @@ -503,16 +507,10 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, } =20 /* The following are mutually exclusive. */ - if (ct & TCG_CT_CONST_MULI) { - /* Immediates that may be used with multiply. If we have the - general-instruction-extensions, then we have MULTIPLY SINGLE - IMMEDIATE with a signed 32-bit, otherwise we have only - MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - if (s390_facilities & FACILITY_GEN_INST_EXT) { - return val =3D=3D (int32_t)val; - } else { - return val =3D=3D (int16_t)val; - } + if (ct & TCG_CT_CONST_S16) { + return val =3D=3D (int16_t)val; + } else if (ct & TCG_CT_CONST_S32) { + return val =3D=3D (int32_t)val; } else if (ct & TCG_CT_CONST_ADLI) { return tcg_match_add2i(type, val); } else if (ct & TCG_CT_CONST_ORI) { @@ -2239,7 +2237,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef r_rZ =3D { .args_ct_str =3D { "r", "rZ" } = }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; - static const TCGTargetOpDef r_0_rK =3D { .args_ct_str =3D { "r", "0", = "rK" } }; + static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; + static const TCGTargetOpDef r_0_rJ =3D { .args_ct_str =3D { "r", "0", = "rJ" } }; static const TCGTargetOpDef r_0_rO =3D { .args_ct_str =3D { "r", "0", = "rO" } }; static const TCGTargetOpDef r_0_rX =3D { .args_ct_str =3D { "r", "0", = "rX" } }; =20 @@ -2274,9 +2273,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_sub_i32: case INDEX_op_sub_i64: return &r_0_ri; + case INDEX_op_mul_i32: + /* If we have the general-instruction-extensions, then we have + MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we + have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ + return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_r= I); case INDEX_op_mul_i64: - return &r_0_rK; + return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_r= I); + case INDEX_op_or_i32: case INDEX_op_or_i64: return &r_0_rO; --=20 2.13.5