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X-Received-From: 2607:f8b0:400e:c05::233 Subject: [Qemu-devel] [PATCH 1/8] tcg/s390: Fully convert tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use a switch instead of searching a table. Signed-off-by: Richard Henderson Acked-by: Cornelia Huck Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/s390/tcg-target.inc.c | 278 +++++++++++++++++++++++++-----------------= ---- 1 file changed, 154 insertions(+), 124 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 5d7083e90c..d34649eb13 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -2246,134 +2246,164 @@ static inline void tcg_out_op(TCGContext *s, TCGO= pcode opc, } } =20 -static const TCGTargetOpDef s390_op_defs[] =3D { - { INDEX_op_exit_tb, { } }, - { INDEX_op_goto_tb, { } }, - { INDEX_op_br, { } }, - { INDEX_op_goto_ptr, { "r" } }, - - { INDEX_op_ld8u_i32, { "r", "r" } }, - { INDEX_op_ld8s_i32, { "r", "r" } }, - { INDEX_op_ld16u_i32, { "r", "r" } }, - { INDEX_op_ld16s_i32, { "r", "r" } }, - { INDEX_op_ld_i32, { "r", "r" } }, - { INDEX_op_st8_i32, { "r", "r" } }, - { INDEX_op_st16_i32, { "r", "r" } }, - { INDEX_op_st_i32, { "r", "r" } }, - - { INDEX_op_add_i32, { "r", "r", "ri" } }, - { INDEX_op_sub_i32, { "r", "0", "ri" } }, - { INDEX_op_mul_i32, { "r", "0", "rK" } }, - - { INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } }, - { INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } }, - - { INDEX_op_and_i32, { "r", "0", "ri" } }, - { INDEX_op_or_i32, { "r", "0", "rO" } }, - { INDEX_op_xor_i32, { "r", "0", "rX" } }, - - { INDEX_op_neg_i32, { "r", "r" } }, - - { INDEX_op_shl_i32, { "r", "0", "ri" } }, - { INDEX_op_shr_i32, { "r", "0", "ri" } }, - { INDEX_op_sar_i32, { "r", "0", "ri" } }, - - { INDEX_op_rotl_i32, { "r", "r", "ri" } }, - { INDEX_op_rotr_i32, { "r", "r", "ri" } }, - - { INDEX_op_ext8s_i32, { "r", "r" } }, - { INDEX_op_ext8u_i32, { "r", "r" } }, - { INDEX_op_ext16s_i32, { "r", "r" } }, - { INDEX_op_ext16u_i32, { "r", "r" } }, - - { INDEX_op_bswap16_i32, { "r", "r" } }, - { INDEX_op_bswap32_i32, { "r", "r" } }, - - { INDEX_op_add2_i32, { "r", "r", "0", "1", "rA", "r" } }, - { INDEX_op_sub2_i32, { "r", "r", "0", "1", "rA", "r" } }, - - { INDEX_op_brcond_i32, { "r", "rC" } }, - { INDEX_op_setcond_i32, { "r", "r", "rC" } }, - { INDEX_op_movcond_i32, { "r", "r", "rC", "r", "0" } }, - { INDEX_op_deposit_i32, { "r", "rZ", "r" } }, - { INDEX_op_extract_i32, { "r", "r" } }, - - { INDEX_op_qemu_ld_i32, { "r", "L" } }, - { INDEX_op_qemu_ld_i64, { "r", "L" } }, - { INDEX_op_qemu_st_i32, { "L", "L" } }, - { INDEX_op_qemu_st_i64, { "L", "L" } }, - - { INDEX_op_ld8u_i64, { "r", "r" } }, - { INDEX_op_ld8s_i64, { "r", "r" } }, - { INDEX_op_ld16u_i64, { "r", "r" } }, - { INDEX_op_ld16s_i64, { "r", "r" } }, - { INDEX_op_ld32u_i64, { "r", "r" } }, - { INDEX_op_ld32s_i64, { "r", "r" } }, - { INDEX_op_ld_i64, { "r", "r" } }, - - { INDEX_op_st8_i64, { "r", "r" } }, - { INDEX_op_st16_i64, { "r", "r" } }, - { INDEX_op_st32_i64, { "r", "r" } }, - { INDEX_op_st_i64, { "r", "r" } }, - - { INDEX_op_add_i64, { "r", "r", "ri" } }, - { INDEX_op_sub_i64, { "r", "0", "ri" } }, - { INDEX_op_mul_i64, { "r", "0", "rK" } }, - - { INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } }, - { INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } }, - { INDEX_op_mulu2_i64, { "b", "a", "0", "r" } }, - - { INDEX_op_and_i64, { "r", "0", "ri" } }, - { INDEX_op_or_i64, { "r", "0", "rO" } }, - { INDEX_op_xor_i64, { "r", "0", "rX" } }, - - { INDEX_op_neg_i64, { "r", "r" } }, - - { INDEX_op_shl_i64, { "r", "r", "ri" } }, - { INDEX_op_shr_i64, { "r", "r", "ri" } }, - { INDEX_op_sar_i64, { "r", "r", "ri" } }, - - { INDEX_op_rotl_i64, { "r", "r", "ri" } }, - { INDEX_op_rotr_i64, { "r", "r", "ri" } }, - - { INDEX_op_ext8s_i64, { "r", "r" } }, - { INDEX_op_ext8u_i64, { "r", "r" } }, - { INDEX_op_ext16s_i64, { "r", "r" } }, - { INDEX_op_ext16u_i64, { "r", "r" } }, - { INDEX_op_ext32s_i64, { "r", "r" } }, - { INDEX_op_ext32u_i64, { "r", "r" } }, - - { INDEX_op_ext_i32_i64, { "r", "r" } }, - { INDEX_op_extu_i32_i64, { "r", "r" } }, - - { INDEX_op_bswap16_i64, { "r", "r" } }, - { INDEX_op_bswap32_i64, { "r", "r" } }, - { INDEX_op_bswap64_i64, { "r", "r" } }, - - { INDEX_op_clz_i64, { "r", "r", "ri" } }, - - { INDEX_op_add2_i64, { "r", "r", "0", "1", "rA", "r" } }, - { INDEX_op_sub2_i64, { "r", "r", "0", "1", "rA", "r" } }, - - { INDEX_op_brcond_i64, { "r", "rC" } }, - { INDEX_op_setcond_i64, { "r", "r", "rC" } }, - { INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } }, - { INDEX_op_deposit_i64, { "r", "0", "r" } }, - { INDEX_op_extract_i64, { "r", "r" } }, - - { INDEX_op_mb, { } }, - { -1 }, -}; - static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - int i, n =3D ARRAY_SIZE(s390_op_defs); + static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; + static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; + static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; + static const TCGTargetOpDef L_L =3D { .args_ct_str =3D { "L", "L" } }; + static const TCGTargetOpDef r_rC =3D { .args_ct_str =3D { "r", "rC" } = }; + static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; + static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; + static const TCGTargetOpDef r_0_rK =3D { .args_ct_str =3D { "r", "0", = "rK" } }; + static const TCGTargetOpDef r_0_rO =3D { .args_ct_str =3D { "r", "0", = "rO" } }; + static const TCGTargetOpDef r_0_rX =3D { .args_ct_str =3D { "r", "0", = "rX" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return &r_r; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + return &r_r_ri; + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + return &r_0_ri; + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + return &r_0_rK; + case INDEX_op_or_i32: + case INDEX_op_or_i64: + return &r_0_rO; + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + return &r_0_rX; + case INDEX_op_and_i32: + case INDEX_op_and_i64: + return &r_0_ri; + + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + return &r_0_ri; + + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + return &r_r_ri; + + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + return &r_r_ri; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return &r_rC; + + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + return &r_r; + + case INDEX_op_clz_i64: + return &r_r_ri; + + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_i64: + return &r_L; + case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_i32: + return &L_L; =20 - for (i =3D 0; i < n; ++i) { - if (s390_op_defs[i].op =3D=3D op) { - return &s390_op_defs[i]; + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + { + static const TCGTargetOpDef dep + =3D { .args_ct_str =3D { "r", "rZ", "r" } }; + return &dep; } + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + { + static const TCGTargetOpDef setc + =3D { .args_ct_str =3D { "r", "r", "rC" } }; + return &setc; + } + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: + { + static const TCGTargetOpDef movc + =3D { .args_ct_str =3D { "r", "r", "rC", "r", "0" } }; + return &movc; + } + case INDEX_op_div2_i32: + case INDEX_op_div2_i64: + case INDEX_op_divu2_i32: + case INDEX_op_divu2_i64: + { + static const TCGTargetOpDef div2 + =3D { .args_ct_str =3D { "b", "a", "0", "1", "r" } }; + return &div2; + } + case INDEX_op_mulu2_i64: + { + static const TCGTargetOpDef mul2 + =3D { .args_ct_str =3D { "b", "a", "0", "r" } }; + return &mul2; + } + case INDEX_op_add2_i32: + case INDEX_op_add2_i64: + case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: + { + static const TCGTargetOpDef arith2 + =3D { .args_ct_str =3D { "r", "r", "0", "1", "rA", "r" } }; + return &arith2; + } + + default: + break; } return NULL; } --=20 2.13.5 From nobody Tue Nov 4 11:49:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15040397907156.176512952240273; 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X-Received-From: 2607:f8b0:400e:c05::22e Subject: [Qemu-devel] [PATCH 2/8] tcg/s390: Merge cmpi facilities check to tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Acked-by: Cornelia Huck --- tcg/s390/tcg-target.inc.c | 68 +++++++++++++++++++++----------------------= ---- 1 file changed, 30 insertions(+), 38 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index d34649eb13..e075b4844a 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -41,7 +41,7 @@ #define TCG_CT_CONST_MULI 0x100 #define TCG_CT_CONST_ORI 0x200 #define TCG_CT_CONST_XORI 0x400 -#define TCG_CT_CONST_CMPI 0x800 +#define TCG_CT_CONST_U31 0x800 #define TCG_CT_CONST_ADLI 0x1000 #define TCG_CT_CONST_ZERO 0x2000 =20 @@ -398,7 +398,18 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, ct->ct |=3D TCG_CT_CONST_XORI; break; case 'C': - ct->ct |=3D TCG_CT_CONST_CMPI; + /* ??? We have no insight here into whether the comparison is + signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit + signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses + a 32-bit unsigned immediate. If we were to use the (semi) + obvious "val =3D=3D (int32_t)val" we would be enabling unsigned + comparisons vs very large numbers. The only solution is to + take the intersection of the ranges. */ + /* ??? Another possible solution is to simply lie and allow all + constants here and force the out-of-range values into a temp + register in tgen_cmp when we have knowledge of the actual + comparison code in use. */ + ct->ct |=3D TCG_CT_CONST_U31; break; case 'Z': ct->ct |=3D TCG_CT_CONST_ZERO; @@ -463,35 +474,6 @@ static int tcg_match_xori(TCGType type, tcg_target_lon= g val) return 1; } =20 -/* Imediates to be used with comparisons. */ - -static int tcg_match_cmpi(TCGType type, tcg_target_long val) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - /* The COMPARE IMMEDIATE instruction is available. */ - if (type =3D=3D TCG_TYPE_I32) { - /* We have a 32-bit immediate and can compare against anything= . */ - return 1; - } else { - /* ??? We have no insight here into whether the comparison is - signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-b= it - signed immediate, and the COMPARE LOGICAL IMMEDIATE insn us= es - a 32-bit unsigned immediate. If we were to use the (semi) - obvious "val =3D=3D (int32_t)val" we would be enabling unsi= gned - comparisons vs very large numbers. The only solution is to - take the intersection of the ranges. */ - /* ??? Another possible solution is to simply lie and allow all - constants here and force the out-of-range values into a temp - register in tgen_cmp when we have knowledge of the actual - comparison code in use. */ - return val >=3D 0 && val <=3D 0x7fffffff; - } - } else { - /* Only the LOAD AND TEST instruction is available. */ - return val =3D=3D 0; - } -} - /* Immediates to be used with add2/sub2. */ =20 static int tcg_match_add2i(TCGType type, tcg_target_long val) @@ -537,8 +519,8 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, return tcg_match_ori(type, val); } else if (ct & TCG_CT_CONST_XORI) { return tcg_match_xori(type, val); - } else if (ct & TCG_CT_CONST_CMPI) { - return tcg_match_cmpi(type, val); + } else if (ct & TCG_CT_CONST_U31) { + return val >=3D 0 && val <=3D 0x7fffffff; } else if (ct & TCG_CT_CONST_ZERO) { return val =3D=3D 0; } @@ -2252,7 +2234,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; static const TCGTargetOpDef L_L =3D { .args_ct_str =3D { "L", "L" } }; + static const TCGTargetOpDef r_ri =3D { .args_ct_str =3D { "r", "ri" } = }; static const TCGTargetOpDef r_rC =3D { .args_ct_str =3D { "r", "rC" } = }; + static const TCGTargetOpDef r_rZ =3D { .args_ct_str =3D { "r", "rZ" } = }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; static const TCGTargetOpDef r_0_rK =3D { .args_ct_str =3D { "r", "0", = "rK" } }; @@ -2320,8 +2304,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) return &r_r_ri; =20 case INDEX_op_brcond_i32: + /* Without EXT_IMM, only the LOAD AND TEST insn is available. */ + return (s390_facilities & FACILITY_EXT_IMM ? &r_ri : &r_rZ); case INDEX_op_brcond_i64: - return &r_rC; + return (s390_facilities & FACILITY_EXT_IMM ? &r_rC : &r_rZ); =20 case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -2366,16 +2352,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: { - static const TCGTargetOpDef setc + /* Without EXT_IMM, only the LOAD AND TEST insn is available. = */ + static const TCGTargetOpDef setc_z + =3D { .args_ct_str =3D { "r", "r", "rZ" } }; + static const TCGTargetOpDef setc_c =3D { .args_ct_str =3D { "r", "r", "rC" } }; - return &setc; + return (s390_facilities & FACILITY_EXT_IMM ? &setc_c : &setc_z= ); } case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: { - static const TCGTargetOpDef movc + /* Without EXT_IMM, only the LOAD AND TEST insn is available. = */ + static const TCGTargetOpDef movc_z + =3D { .args_ct_str =3D { "r", "r", "rZ", "r", "0" } }; + static const TCGTargetOpDef movc_c =3D { .args_ct_str =3D { "r", "r", "rC", "r", "0" } }; - return &movc; + return (s390_facilities & FACILITY_EXT_IMM ? &movc_c : &movc_z= ); } case INDEX_op_div2_i32: case INDEX_op_div2_i64: --=20 2.13.5 From nobody Tue Nov 4 11:49:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504039956728393.5599924109961; Tue, 29 Aug 2017 13:52:36 -0700 (PDT) Received: from localhost ([::1]:46909 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmnUw-0005x2-HO for importer@patchew.org; Tue, 29 Aug 2017 16:52:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmnQf-0002Qq-K8 for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmnQe-0001UN-NQ for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:09 -0400 Received: from mail-pf0-x231.google.com ([2607:f8b0:400e:c00::231]:36810) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmnQe-0001U3-HS for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:08 -0400 Received: by mail-pf0-x231.google.com with SMTP id z87so13387420pfi.3 for ; Tue, 29 Aug 2017 13:48:08 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0RJY26L+wluBLiCwy06P1bcCFRjSUiVl+17C88pqpyA=; b=a/x906QphU6HJBjjrSVfTSlMgTMyWNm9VBxZptmPwjJe/51dtMdkjD8xhkGAsGkME6 JLGpM5EhR5nHIrMJbCfXnecq73WPLskqYCb6Yn0xWcE32gECqJRwmA9Wu3SCNTI/FBTj FYShmTgrNwffSx9Dr+WW3OJ57FKPNjdf/zdPw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0RJY26L+wluBLiCwy06P1bcCFRjSUiVl+17C88pqpyA=; b=EEV9i6bsVdZPrP9jeHVPHbFCi82ERdyDqkLWehs4ku0NPvDmMG2NfuR97xRaN/5FaM JpktTW7o3P3f7kZuAKMorGrbTZVGgApJ/wra2NJIGmPj87KgrO41MFvwERqxlzM4lRwm AEhNy5Fo1X6lE/dwlw8mia5jHcwFH8MkUEnu+JHtYoc3UVOuJf5MXy5Gu71CjxbG7ygq 48dL/D+nv16/13aqQBpuGKAiG74vsmP9JRP410nZrpoMXjs0uuLxPZFLTevPi7R9IX14 AvjrdiVyxoEvc6M5NmZwOKubkHenlg4smnm4fCB2jmWV/Jgcwg3N0BHovHqrrWAHhj9o zzCg== X-Gm-Message-State: AHYfb5gdc8yLt7LTtpLDLKu5t7Xr0A0aavDszr2uVL1tTB7BG2IoWx09 gA9zlNRQpCsrVt9VK+tioQ== X-Received: by 10.98.59.194 with SMTP id w63mr1665905pfj.44.1504039687194; Tue, 29 Aug 2017 13:48:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:54 -0700 Message-Id: <20170829204759.6853-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::231 Subject: [Qemu-devel] [PATCH 3/8] tcg/s390: Merge muli facilities check to tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Acked-by: Cornelia Huck --- tcg/s390/tcg-target.inc.c | 45 +++++++++++++++++++++++++------------------= -- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index e075b4844a..ff3f644f8e 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -38,12 +38,13 @@ a 32-bit displacement here Just In Case. */ #define USE_LONG_BRANCHES 0 =20 -#define TCG_CT_CONST_MULI 0x100 -#define TCG_CT_CONST_ORI 0x200 -#define TCG_CT_CONST_XORI 0x400 -#define TCG_CT_CONST_U31 0x800 -#define TCG_CT_CONST_ADLI 0x1000 -#define TCG_CT_CONST_ZERO 0x2000 +#define TCG_CT_CONST_S16 0x100 +#define TCG_CT_CONST_S32 0x200 +#define TCG_CT_CONST_ORI 0x400 +#define TCG_CT_CONST_XORI 0x800 +#define TCG_CT_CONST_U31 0x1000 +#define TCG_CT_CONST_ADLI 0x2000 +#define TCG_CT_CONST_ZERO 0x4000 =20 /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ @@ -388,8 +389,11 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, case 'A': ct->ct |=3D TCG_CT_CONST_ADLI; break; - case 'K': - ct->ct |=3D TCG_CT_CONST_MULI; + case 'I': + ct->ct |=3D TCG_CT_CONST_S16; + break; + case 'J': + ct->ct |=3D TCG_CT_CONST_S32; break; case 'O': ct->ct |=3D TCG_CT_CONST_ORI; @@ -503,16 +507,10 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, } =20 /* The following are mutually exclusive. */ - if (ct & TCG_CT_CONST_MULI) { - /* Immediates that may be used with multiply. If we have the - general-instruction-extensions, then we have MULTIPLY SINGLE - IMMEDIATE with a signed 32-bit, otherwise we have only - MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - if (s390_facilities & FACILITY_GEN_INST_EXT) { - return val =3D=3D (int32_t)val; - } else { - return val =3D=3D (int16_t)val; - } + if (ct & TCG_CT_CONST_S16) { + return val =3D=3D (int16_t)val; + } else if (ct & TCG_CT_CONST_S32) { + return val =3D=3D (int32_t)val; } else if (ct & TCG_CT_CONST_ADLI) { return tcg_match_add2i(type, val); } else if (ct & TCG_CT_CONST_ORI) { @@ -2239,7 +2237,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef r_rZ =3D { .args_ct_str =3D { "r", "rZ" } = }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; - static const TCGTargetOpDef r_0_rK =3D { .args_ct_str =3D { "r", "0", = "rK" } }; + static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; + static const TCGTargetOpDef r_0_rJ =3D { .args_ct_str =3D { "r", "0", = "rJ" } }; static const TCGTargetOpDef r_0_rO =3D { .args_ct_str =3D { "r", "0", = "rO" } }; static const TCGTargetOpDef r_0_rX =3D { .args_ct_str =3D { "r", "0", = "rX" } }; =20 @@ -2274,9 +2273,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_sub_i32: case INDEX_op_sub_i64: return &r_0_ri; + case INDEX_op_mul_i32: + /* If we have the general-instruction-extensions, then we have + MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we + have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ + return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_r= I); case INDEX_op_mul_i64: - return &r_0_rK; + return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_r= I); + case INDEX_op_or_i32: case INDEX_op_or_i64: return &r_0_rO; --=20 2.13.5 From nobody Tue Nov 4 11:49:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504040109175115.92313899499368; Tue, 29 Aug 2017 13:55:09 -0700 (PDT) Received: from localhost ([::1]:46920 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmnXO-00084f-JX for importer@patchew.org; Tue, 29 Aug 2017 16:55:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49495) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmnQg-0002RB-R6 for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmnQg-0001Uq-06 for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:10 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:35703) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmnQf-0001Ua-QW for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:09 -0400 Received: by mail-pg0-x22a.google.com with SMTP id 63so13983044pgc.2 for ; Tue, 29 Aug 2017 13:48:09 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+xk74aQne64nnvSHJDOsLuL5qJmlj3IuSazRcsfg9Ns=; b=UXB8wM105do+MTLcKRSMaS3kwSuzvQZQfu7XR5vIr/poJjkCS7IkHQ0MHbj2sL/iuN smTBMVKQoTrlw7xFtaM/I3f1Hbh+LlIErZPz3kymwpac3BnVwA2EmFI70TDChNRspSYi YwDoUYZ1jEW7AASm3bdnrsMkDTrJWcFyb/THE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+xk74aQne64nnvSHJDOsLuL5qJmlj3IuSazRcsfg9Ns=; b=gCB3rXnU2v+dR9Vw7oh49GjbgHh2PkqZvOFiNlYOsAQeyOC3hU784w5ELKILKYcI/u FNYtRPpTXl7bm2d7PIyUNVvPpNona+DBUowd/WJEvhZKI11erqUiJrk9iPcGK/xs6Hm+ 20Y0wQ8G5moRzIY8VAC+yEVbL/168HI47NJ88GyPZdPAV0rfRXGbsBhCySZ6kY3ZruRt Z/OKgXVA5Jx5P4r90iR7dt2Cjr+m5tPTGTXGsQhVX/EnmDbLLei3HV4ub2jcn/9Ubsnu wNmJgBqMBR71ollkSHCBlsGfpHjXRsiL0mRs1vpYMDUF3Y6hpHwkHkbSbpAOi6H/1lFK lBkg== X-Gm-Message-State: AHYfb5gs0RIT+yUhvn9A6Fe6WFLNguFMA3tx3SlcjOrCmQy3DpLHV2EL WViHnDLh3nMSao4W/1t7lg== X-Received: by 10.98.58.73 with SMTP id h70mr1601951pfa.27.1504039688487; Tue, 29 Aug 2017 13:48:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:55 -0700 Message-Id: <20170829204759.6853-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH 4/8] tcg/s390: Merge add2i facilities check to tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Acked-by: Cornelia Huck --- tcg/s390/tcg-target.inc.c | 38 ++++++++++++++------------------------ 1 file changed, 14 insertions(+), 24 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index ff3f644f8e..6b08ccea6d 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -43,7 +43,7 @@ #define TCG_CT_CONST_ORI 0x400 #define TCG_CT_CONST_XORI 0x800 #define TCG_CT_CONST_U31 0x1000 -#define TCG_CT_CONST_ADLI 0x2000 +#define TCG_CT_CONST_S33 0x2000 #define TCG_CT_CONST_ZERO 0x4000 =20 /* Several places within the instruction set 0 means "no register" @@ -387,7 +387,7 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, tcg_regset_set_reg(ct->u.regs, TCG_REG_R3); break; case 'A': - ct->ct |=3D TCG_CT_CONST_ADLI; + ct->ct |=3D TCG_CT_CONST_S33; break; case 'I': ct->ct |=3D TCG_CT_CONST_S16; @@ -478,20 +478,6 @@ static int tcg_match_xori(TCGType type, tcg_target_lon= g val) return 1; } =20 -/* Immediates to be used with add2/sub2. */ - -static int tcg_match_add2i(TCGType type, tcg_target_long val) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - if (type =3D=3D TCG_TYPE_I32) { - return 1; - } else if (val >=3D -0xffffffffll && val <=3D 0xffffffffll) { - return 1; - } - } - return 0; -} - /* Test if a constant matches the constraint. */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) @@ -511,8 +497,8 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, return val =3D=3D (int16_t)val; } else if (ct & TCG_CT_CONST_S32) { return val =3D=3D (int32_t)val; - } else if (ct & TCG_CT_CONST_ADLI) { - return tcg_match_add2i(type, val); + } else if (ct & TCG_CT_CONST_S33) { + return val >=3D -0xffffffffll && val <=3D 0xffffffffll; } else if (ct & TCG_CT_CONST_ORI) { return tcg_match_ori(type, val); } else if (ct & TCG_CT_CONST_XORI) { @@ -2241,6 +2227,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) static const TCGTargetOpDef r_0_rJ =3D { .args_ct_str =3D { "r", "0", = "rJ" } }; static const TCGTargetOpDef r_0_rO =3D { .args_ct_str =3D { "r", "0", = "rO" } }; static const TCGTargetOpDef r_0_rX =3D { .args_ct_str =3D { "r", "0", = "rX" } }; + static const TCGTargetOpDef a2_r + =3D { .args_ct_str =3D { "r", "r", "0", "1", "r", "r" } }; + static const TCGTargetOpDef a2_ri + =3D { .args_ct_str =3D { "r", "r", "0", "1", "ri", "r" } }; + static const TCGTargetOpDef a2_rA + =3D { .args_ct_str =3D { "r", "r", "0", "1", "rA", "r" } }; =20 switch (op) { case INDEX_op_goto_ptr: @@ -2389,15 +2381,13 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) =3D { .args_ct_str =3D { "b", "a", "0", "r" } }; return &mul2; } + case INDEX_op_add2_i32: - case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r); + case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - { - static const TCGTargetOpDef arith2 - =3D { .args_ct_str =3D { "r", "r", "0", "1", "rA", "r" } }; - return &arith2; - } + return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r); =20 default: break; --=20 2.13.5 From nobody Tue Nov 4 11:49:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504039962137184.1338332787832; Tue, 29 Aug 2017 13:52:42 -0700 (PDT) Received: from localhost ([::1]:46910 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmnUx-0005xA-Ri for importer@patchew.org; Tue, 29 Aug 2017 16:52:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49514) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmnQj-0002TK-7x for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmnQh-0001VY-Po for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:13 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:33569) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmnQh-0001VD-H9 for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:11 -0400 Received: by mail-pg0-x22a.google.com with SMTP id t3so14084237pgt.0 for ; Tue, 29 Aug 2017 13:48:11 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=z1QnsbS9MFumUozer0g7J9ZIxQh46hRZoXAWdZEeU2g=; b=BYS8IDyGqL9lFbuMXw/72Hkdt/wOItGzn8WhJo4y9vNsHZMf0jDNVNoLaOjH8ilV8g EpMOLztN8HkxAWFqZ+wvc6rBSKVz4fvZYmbmyVuo83RzzvJov2lkTghl1E1w40e/ihNC PCyq75faA7KCODU0fpYUqUcr1P4Qp9mhYgDFA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=z1QnsbS9MFumUozer0g7J9ZIxQh46hRZoXAWdZEeU2g=; b=U6h1rGGrlhHnW+tpRFnIIbjQJEt6zqv17VdsUURo4/SlukmKGc6y+f3zb4FRi3wog4 pOW2QdyIw1xbOcXs47HMahiL1uwSB8B5OPynCrerHZY0qIENE0AxG98/GWdb7Q7VxXjP w/FlyEPnJ05z0OIKDJQm5XGld93+X9N88b3CCbcybYwSqSBRqCTyb4QTgyYag+7K2OV2 PlFRrjD/OEasAW0kDoQRKfvQZGBxqLxI7Aciv8NhaqGyeQRf4xp23yQR7+97IdLuvHnQ aywx+SPuZS47UIuPpn2GWOhXgdhD0qrxQEuToapz1lNJflnTavHsW7AyPHZq4Lz/8etE lkWQ== X-Gm-Message-State: AHYfb5gCFDr0pBvldLQug2pVQfkJHTbaEEOLIRg3xR806QAs+UKTeMVS AH6x6NpppHbvnCNnpU5GGw== X-Received: by 10.98.14.194 with SMTP id 63mr1619222pfo.80.1504039690175; Tue, 29 Aug 2017 13:48:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:56 -0700 Message-Id: <20170829204759.6853-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PATCH 5/8] tcg/s390: Merge ori+xori facilities check to tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Acked-by: Cornelia Huck --- tcg/s390/tcg-target.inc.c | 101 +++++++++++++++---------------------------= ---- 1 file changed, 33 insertions(+), 68 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 6b08ccea6d..5414c9d879 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -40,8 +40,8 @@ =20 #define TCG_CT_CONST_S16 0x100 #define TCG_CT_CONST_S32 0x200 -#define TCG_CT_CONST_ORI 0x400 -#define TCG_CT_CONST_XORI 0x800 +#define TCG_CT_CONST_NN16 0x400 +#define TCG_CT_CONST_NN32 0x800 #define TCG_CT_CONST_U31 0x1000 #define TCG_CT_CONST_S33 0x2000 #define TCG_CT_CONST_ZERO 0x4000 @@ -395,11 +395,11 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, case 'J': ct->ct |=3D TCG_CT_CONST_S32; break; - case 'O': - ct->ct |=3D TCG_CT_CONST_ORI; + case 'N': + ct->ct |=3D TCG_CT_CONST_NN16; break; - case 'X': - ct->ct |=3D TCG_CT_CONST_XORI; + case 'M': + ct->ct |=3D TCG_CT_CONST_NN32; break; case 'C': /* ??? We have no insight here into whether the comparison is @@ -424,60 +424,6 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, return ct_str; } =20 -/* Immediates to be used with logical OR. This is an optimization only, - since a full 64-bit immediate OR can always be performed with 4 sequent= ial - OI[LH][LH] instructions. What we're looking for is immediates that we - can load efficiently, and the immediate load plus the reg-reg OR is - smaller than the sequential OI's. */ - -static int tcg_match_ori(TCGType type, tcg_target_long val) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - if (type =3D=3D TCG_TYPE_I32) { - /* All 32-bit ORs can be performed with 1 48-bit insn. */ - return 1; - } - } - - /* Look for negative values. These are best to load with LGHI. */ - if (val < 0) { - if (val =3D=3D (int16_t)val) { - return 0; - } - if (s390_facilities & FACILITY_EXT_IMM) { - if (val =3D=3D (int32_t)val) { - return 0; - } - } - } - - return 1; -} - -/* Immediates to be used with logical XOR. This is almost, but not quite, - only an optimization. XOR with immediate is only supported with the - extended-immediate facility. That said, there are a few patterns for - which it is better to load the value into a register first. */ - -static int tcg_match_xori(TCGType type, tcg_target_long val) -{ - if ((s390_facilities & FACILITY_EXT_IMM) =3D=3D 0) { - return 0; - } - - if (type =3D=3D TCG_TYPE_I32) { - /* All 32-bit XORs can be performed with 1 48-bit insn. */ - return 1; - } - - /* Look for negative values. These are best to load with LGHI. */ - if (val < 0 && val =3D=3D (int32_t)val) { - return 0; - } - - return 1; -} - /* Test if a constant matches the constraint. */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) @@ -499,10 +445,10 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, return val =3D=3D (int32_t)val; } else if (ct & TCG_CT_CONST_S33) { return val >=3D -0xffffffffll && val <=3D 0xffffffffll; - } else if (ct & TCG_CT_CONST_ORI) { - return tcg_match_ori(type, val); - } else if (ct & TCG_CT_CONST_XORI) { - return tcg_match_xori(type, val); + } else if (ct & TCG_CT_CONST_NN16) { + return !(val < 0 && val =3D=3D (int16_t)val); + } else if (ct & TCG_CT_CONST_NN32) { + return !(val < 0 && val =3D=3D (int32_t)val); } else if (ct & TCG_CT_CONST_U31) { return val >=3D 0 && val <=3D 0x7fffffff; } else if (ct & TCG_CT_CONST_ZERO) { @@ -2222,11 +2168,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) static const TCGTargetOpDef r_rC =3D { .args_ct_str =3D { "r", "rC" } = }; static const TCGTargetOpDef r_rZ =3D { .args_ct_str =3D { "r", "rZ" } = }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; + static const TCGTargetOpDef r_0_r =3D { .args_ct_str =3D { "r", "0", "= r" } }; static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; static const TCGTargetOpDef r_0_rJ =3D { .args_ct_str =3D { "r", "0", = "rJ" } }; - static const TCGTargetOpDef r_0_rO =3D { .args_ct_str =3D { "r", "0", = "rO" } }; - static const TCGTargetOpDef r_0_rX =3D { .args_ct_str =3D { "r", "0", = "rX" } }; + static const TCGTargetOpDef r_0_rN =3D { .args_ct_str =3D { "r", "0", = "rN" } }; + static const TCGTargetOpDef r_0_rM =3D { .args_ct_str =3D { "r", "0", = "rM" } }; static const TCGTargetOpDef a2_r =3D { .args_ct_str =3D { "r", "r", "0", "1", "r", "r" } }; static const TCGTargetOpDef a2_ri @@ -2275,11 +2222,29 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_r= I); =20 case INDEX_op_or_i32: + /* The use of [iNM] constraints are optimization only, since a full + 64-bit immediate OR can always be performed with 4 sequential + OI[LH][LH] instructions. By rejecting certain negative ranges, + the immediate load plus the reg-reg OR is smaller. */ + return (s390_facilities & FACILITY_EXT_IMM + ? &r_0_ri + : &r_0_rN); case INDEX_op_or_i64: - return &r_0_rO; + return (s390_facilities & FACILITY_EXT_IMM + ? &r_0_rM + : &r_0_rN); + case INDEX_op_xor_i32: + /* Without EXT_IMM, no immediates are supported. Otherwise, + rejecting certain negative ranges leads to smaller code. */ + return (s390_facilities & FACILITY_EXT_IMM + ? &r_0_ri + : &r_0_r); case INDEX_op_xor_i64: - return &r_0_rX; + return (s390_facilities & FACILITY_EXT_IMM + ? &r_0_rM + : &r_0_r); + case INDEX_op_and_i32: case INDEX_op_and_i64: return &r_0_ri; --=20 2.13.5 From nobody Tue Nov 4 11:49:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504040262464238.51082260881708; Tue, 29 Aug 2017 13:57:42 -0700 (PDT) Received: from localhost ([::1]:46933 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmnZs-0002Jn-7L for importer@patchew.org; Tue, 29 Aug 2017 16:57:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49529) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmnQk-0002V3-Qm for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmnQj-0001Vn-5L for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:14 -0400 Received: from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:36623) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmnQi-0001Vd-Sy for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:13 -0400 Received: by mail-pg0-x22c.google.com with SMTP id r133so13991517pgr.3 for ; Tue, 29 Aug 2017 13:48:12 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g8yP4qkSZz+fxQ+4zsqNUcLQi6JaL8uvacalBHt62FU=; b=YfBHJhA+0hZdSNFEXbzltGqxC4ZtRjAM8SRblzowFlMsMi0tivhAQjCG0hWfgohfFk tE+8UWzsaiDg6YKGIzc2aoRACngKaZ/Aji6/53JuIOKKR8CYpidXP2NLlo2iPTBUhpUU 1DtOVujDwPaofXrsG0uoYrXiGR12On3ypPZHw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g8yP4qkSZz+fxQ+4zsqNUcLQi6JaL8uvacalBHt62FU=; b=k8YFRxYVjA0D/Nckl8Ii09Q9AZRjx9JpgV2+n5J76lZNNL8/khQVocw5besoKyB7y7 6VT2Yuzu6uX4eaYpc293Zx2/kFEm1F1aTkD3NRGY5dYyUMoUEFWqJMVPGEP4Gr3dRg39 +5DZ2cHqtx3vqweUzCibKqgsrfS8UoMlZfROA13+D7PtslUo6c/9qgWowQR98EovBrZ2 UlT5d8hQ6wOoxpLMn5lu+/iR1WfBSNLdnMOQLcm0hR7R2JajvnqrMN71s6d/9eMLIuD0 1pSXH1uWzVNGkqp1k+9FFwtb07w4hPK3oKIgWAGotXwDoMKgHRh9WnKSBSVbIjKkYWfM X4bw== X-Gm-Message-State: AHYfb5hyZ+mCnfBOD9epVlAqU9aYUQO9TBc9uRq47Se1fLx1E2434/is J7V5Qb2kDc3x+XeBsZY2Pg== X-Received: by 10.84.193.131 with SMTP id f3mr2002790pld.62.1504039691525; Tue, 29 Aug 2017 13:48:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:57 -0700 Message-Id: <20170829204759.6853-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PATCH 6/8] tcg/s390: Use distinct-operands facility X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This allows using a 3-operand insn form for some arithmetic, logicals and shifts. Signed-off-by: Richard Henderson Acked-by: Cornelia Huck --- tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.inc.c | 118 +++++++++++++++++++++++++++++++++++-------= ---- 2 files changed, 91 insertions(+), 28 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 957f0c0afe..1b5eb22c26 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -58,6 +58,7 @@ typedef enum TCGReg { #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34)) #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND +#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND =20 extern uint64_t s390_facilities; =20 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 5414c9d879..a80b07db65 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -159,6 +159,16 @@ typedef enum S390Opcode { =20 RRF_LOCR =3D 0xb9f2, RRF_LOCGR =3D 0xb9e2, + RRF_NRK =3D 0xb9f4, + RRF_NGRK =3D 0xb9e4, + RRF_ORK =3D 0xb9f6, + RRF_OGRK =3D 0xb9e6, + RRF_SRK =3D 0xb9f9, + RRF_SGRK =3D 0xb9e9, + RRF_SLRK =3D 0xb9fb, + RRF_SLGRK =3D 0xb9eb, + RRF_XRK =3D 0xb9f7, + RRF_XGRK =3D 0xb9e7, =20 RR_AR =3D 0x1a, RR_ALR =3D 0x1e, @@ -179,8 +189,11 @@ typedef enum S390Opcode { RSY_RLL =3D 0xeb1d, RSY_RLLG =3D 0xeb1c, RSY_SLLG =3D 0xeb0d, + RSY_SLLK =3D 0xebdf, RSY_SRAG =3D 0xeb0a, + RSY_SRAK =3D 0xebdc, RSY_SRLG =3D 0xeb0c, + RSY_SRLK =3D 0xebde, =20 RS_SLL =3D 0x89, RS_SRA =3D 0x8a, @@ -1065,23 +1078,29 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, case TCG_COND_GEU: do_geu: /* We need "real" carry semantics, so use SUBTRACT LOGICAL - instead of COMPARE LOGICAL. This needs an extra move. */ - tcg_out_mov(s, type, TCG_TMP0, c1); + instead of COMPARE LOGICAL. This may need an extra move. */ if (c2const) { - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_mov(s, type, TCG_TMP0, c1); if (type =3D=3D TCG_TYPE_I32) { tcg_out_insn(s, RIL, SLFI, TCG_TMP0, c2); } else { tcg_out_insn(s, RIL, SLGFI, TCG_TMP0, c2); } + } else if (s390_facilities & FACILITY_DISTINCT_OPS) { + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_insn(s, RRF, SLRK, TCG_TMP0, c1, c2); + } else { + tcg_out_insn(s, RRF, SLGRK, TCG_TMP0, c1, c2); + } } else { + tcg_out_mov(s, type, TCG_TMP0, c1); if (type =3D=3D TCG_TYPE_I32) { tcg_out_insn(s, RR, SLR, TCG_TMP0, c2); } else { tcg_out_insn(s, RRE, SLGR, TCG_TMP0, c2); } - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); } + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); tcg_out_insn(s, RRE, ALCGR, dest, dest); return; =20 @@ -1648,7 +1667,7 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - S390Opcode op; + S390Opcode op, op2; TCGArg a0, a1, a2; =20 switch (opc) { @@ -1753,29 +1772,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, if (const_args[2]) { a2 =3D -a2; goto do_addi_32; + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RR, SR, a0, a2); + } else { + tcg_out_insn(s, RRF, SRK, a0, a1, a2); } - tcg_out_insn(s, RR, SR, args[0], args[2]); break; =20 case INDEX_op_and_i32: + a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; if (const_args[2]) { - tgen_andi(s, TCG_TYPE_I32, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen_andi(s, TCG_TYPE_I32, a0, a2); + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RR, NR, a0, a2); } else { - tcg_out_insn(s, RR, NR, args[0], args[2]); + tcg_out_insn(s, RRF, NRK, a0, a1, a2); } break; case INDEX_op_or_i32: + a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; if (const_args[2]) { - tgen64_ori(s, args[0], args[2] & 0xffffffff); + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen64_ori(s, a0, a2); + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RR, OR, a0, a2); } else { - tcg_out_insn(s, RR, OR, args[0], args[2]); + tcg_out_insn(s, RRF, ORK, a0, a1, a2); } break; case INDEX_op_xor_i32: + a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; if (const_args[2]) { - tgen64_xori(s, args[0], args[2] & 0xffffffff); - } else { + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen64_xori(s, a0, a2); + } else if (a0 =3D=3D a1) { tcg_out_insn(s, RR, XR, args[0], args[2]); + } else { + tcg_out_insn(s, RRF, XRK, a0, a1, a2); } break; =20 @@ -1804,18 +1838,31 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, =20 case INDEX_op_shl_i32: op =3D RS_SLL; + op2 =3D RSY_SLLK; do_shift32: - if (const_args[2]) { - tcg_out_sh32(s, op, args[0], TCG_REG_NONE, args[2]); + a0 =3D args[0], a1 =3D args[1], a2 =3D (int32_t)args[2]; + if (a0 =3D=3D a1) { + if (const_args[2]) { + tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); + } else { + tcg_out_sh32(s, op, a0, a2, 0); + } } else { - tcg_out_sh32(s, op, args[0], args[2], 0); + /* Using tcg_out_sh64 here for the format; it is a 32-bit shif= t. */ + if (const_args[2]) { + tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); + } else { + tcg_out_sh64(s, op2, a0, a1, a2, 0); + } } break; case INDEX_op_shr_i32: op =3D RS_SRL; + op2 =3D RSY_SRLK; goto do_shift32; case INDEX_op_sar_i32: op =3D RS_SRA; + op2 =3D RSY_SRAK; goto do_shift32; =20 case INDEX_op_rotl_i32: @@ -1957,30 +2004,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, if (const_args[2]) { a2 =3D -a2; goto do_addi_64; + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RRE, SGR, a0, a2); } else { - tcg_out_insn(s, RRE, SGR, args[0], args[2]); + tcg_out_insn(s, RRF, SGRK, a0, a1, a2); } break; =20 case INDEX_op_and_i64: + a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); - } else { + } else if (a0 =3D=3D a1) { tcg_out_insn(s, RRE, NGR, args[0], args[2]); + } else { + tcg_out_insn(s, RRF, NGRK, a0, a1, a2); } break; case INDEX_op_or_i64: + a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { - tgen64_ori(s, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen64_ori(s, a0, a2); + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RRE, OGR, a0, a2); } else { - tcg_out_insn(s, RRE, OGR, args[0], args[2]); + tcg_out_insn(s, RRF, OGRK, a0, a1, a2); } break; case INDEX_op_xor_i64: + a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { - tgen64_xori(s, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen64_xori(s, a0, a2); + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RRE, XGR, a0, a2); } else { - tcg_out_insn(s, RRE, XGR, args[0], args[2]); + tcg_out_insn(s, RRF, XGRK, a0, a1, a2); } break; =20 @@ -2168,6 +2229,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef r_rC =3D { .args_ct_str =3D { "r", "rC" } = }; static const TCGTargetOpDef r_rZ =3D { .args_ct_str =3D { "r", "rZ" } = }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; + static const TCGTargetOpDef r_r_rM =3D { .args_ct_str =3D { "r", "r", = "rM" } }; static const TCGTargetOpDef r_0_r =3D { .args_ct_str =3D { "r", "0", "= r" } }; static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; @@ -2211,7 +2273,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &r_r_ri; case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_0_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); =20 case INDEX_op_mul_i32: /* If we have the general-instruction-extensions, then we have @@ -2227,32 +2289,32 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) OI[LH][LH] instructions. By rejecting certain negative ranges, the immediate load plus the reg-reg OR is smaller. */ return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_ri + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_= 0_ri) : &r_0_rN); case INDEX_op_or_i64: return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_rM + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_= 0_rM) : &r_0_rN); =20 case INDEX_op_xor_i32: /* Without EXT_IMM, no immediates are supported. Otherwise, rejecting certain negative ranges leads to smaller code. */ return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_ri + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_= 0_ri) : &r_0_r); case INDEX_op_xor_i64: return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_rM + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_= 0_rM) : &r_0_r); =20 case INDEX_op_and_i32: case INDEX_op_and_i64: - return &r_0_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); =20 case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return &r_0_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); =20 case INDEX_op_shl_i64: case INDEX_op_shr_i64: --=20 2.13.5 From nobody Tue Nov 4 11:49:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504040402929578.1487016452983; Tue, 29 Aug 2017 14:00:02 -0700 (PDT) Received: from localhost ([::1]:46948 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmnc8-0004L9-Q8 for importer@patchew.org; Tue, 29 Aug 2017 17:00:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49547) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmnQn-0002Xg-UW for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmnQk-0001WE-Sk for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:18 -0400 Received: from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:35710) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmnQk-0001W3-K2 for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:14 -0400 Received: by mail-pg0-x235.google.com with SMTP id 63so13983565pgc.2 for ; Tue, 29 Aug 2017 13:48:14 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kDmH5DemrkbAsivBHhbt4U1wgoxR7gHo6X6o0mKr35Y=; b=hECew1pgXDIyJF5AHC3RS8bJYqymq5Xtc2Fm53p3a2MFnOuOEv/UMNdMS9xXN40eq5 +/tPYfcKxL/otNj+razhKZcHza+dLa4FHNNS+UI5fuz78MLz5/A+6nTVfQs8ZvpYcZfU KF93wsR2tgcVpw8GBROjjEk3yu40+L8lc7vtE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kDmH5DemrkbAsivBHhbt4U1wgoxR7gHo6X6o0mKr35Y=; b=s8s8ji2QtBMoxwHaO2W6haFO8bFt6gchdUti9uuTkbcJcwolLRzsiGTRCmRBrIAkCu 00Q3Sp0002/nNKfyTr8Bh+lilYNoEf+64Yf77lUctm8toT8/HCRbiDMcVioKu8vbJRBc EGVU78Q2p9KC0YTpP0kUTzHwOEkG4MzU6gFRAAvreIfNp91qvMDsKQJWhnJWjdMLGZGu UmxPOAt4DbWelSK/n/WrFUdJQMOcZMeTgd0GbmRcU/jmcd27bZ6R6VO8LFT470CGvsz9 ERyJrCVhSZHGp0drtIJo2yjqr3bOW+blV2hMFv1tvVgjcdXAePMG5NPSwy5vxOPQsJTu VoKA== X-Gm-Message-State: AHYfb5hqfDCjYwQalhDxOexwgCTukK7FP9t4jF3CKNOK/kMsJRo5geIY EfKgapTCbcwaRdfihknBQw== X-Received: by 10.84.218.14 with SMTP id q14mr1950239pli.286.1504039693220; Tue, 29 Aug 2017 13:48:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:58 -0700 Message-Id: <20170829204759.6853-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PATCH 7/8] tcg/s390: Use load-on-condition-2 facility X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This allows LOAD HALFWORD IMMEDIATE ON CONDITION, eliminating one insn in some common cases. Signed-off-by: Richard Henderson Acked-by: Cornelia Huck --- tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.inc.c | 79 +++++++++++++++++++++++++++++++++++++------= ---- 2 files changed, 63 insertions(+), 17 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 1b5eb22c26..81fc179459 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -59,6 +59,7 @@ typedef enum TCGReg { #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND +#define FACILITY_LOAD_ON_COND2 (1ULL << (63 - 53)) =20 extern uint64_t s390_facilities; =20 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index a80b07db65..0de968fde2 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -122,6 +122,7 @@ typedef enum S390Opcode { RIE_CLGIJ =3D 0xec7d, RIE_CLRJ =3D 0xec77, RIE_CRJ =3D 0xec76, + RIE_LOCGHI =3D 0xec46, RIE_RISBG =3D 0xec55, =20 RRE_AGR =3D 0xb908, @@ -495,6 +496,13 @@ static void tcg_out_insn_RI(TCGContext *s, S390Opcode = op, TCGReg r1, int i2) tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); } =20 +static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1, + int i2, int m3) +{ + tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); + tcg_out32(s, (i2 << 16) | (op & 0xff)); +} + static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int = i2) { tcg_out16(s, op | (r1 << 4)); @@ -1063,7 +1071,20 @@ static void tgen_setcond(TCGContext *s, TCGType type= , TCGCond cond, TCGReg dest, TCGReg c1, TCGArg c2, int c2const) { int cc; + bool have_loc; =20 + /* With LOC2, we can always emit the minimum 3 insns. */ + if (s390_facilities & FACILITY_LOAD_ON_COND2) { + /* Emit: d =3D 0, d =3D (cc ? 1 : d). */ + cc =3D tgen_cmp(s, type, cond, c1, c2, c2const, false); + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc); + return; + } + + have_loc =3D (s390_facilities & FACILITY_LOAD_ON_COND) !=3D 0; + + /* For HAVE_LOC, only the path through do_greater is smaller. */ switch (cond) { case TCG_COND_GTU: case TCG_COND_GT: @@ -1076,6 +1097,9 @@ static void tgen_setcond(TCGContext *s, TCGType type,= TCGCond cond, return; =20 case TCG_COND_GEU: + if (have_loc) { + goto do_loc; + } do_geu: /* We need "real" carry semantics, so use SUBTRACT LOGICAL instead of COMPARE LOGICAL. This may need an extra move. */ @@ -1105,10 +1129,17 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, return; =20 case TCG_COND_LEU: + if (have_loc) { + goto do_loc; + } + /* fallthru */ case TCG_COND_LTU: case TCG_COND_LT: /* Swap operands so that we can use GEU/GTU/GT. */ if (c2const) { + if (have_loc) { + goto do_loc; + } tcg_out_movi(s, type, TCG_TMP0, c2); c2 =3D c1; c2const =3D 0; @@ -1133,6 +1164,9 @@ static void tgen_setcond(TCGContext *s, TCGType type,= TCGCond cond, break; =20 case TCG_COND_EQ: + if (have_loc) { + goto do_loc; + } /* X =3D=3D 0 is X <=3D 0 is 0 >=3D X. */ if (c2const && c2 =3D=3D 0) { tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0); @@ -1148,33 +1182,39 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, } =20 cc =3D tgen_cmp(s, type, cond, c1, c2, c2const, false); - if (s390_facilities & FACILITY_LOAD_ON_COND) { - /* Emit: d =3D 0, t =3D 1, d =3D (cc ? t : d). */ - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); - tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); - } else { - /* Emit: d =3D 1; if (cc) goto over; d =3D 0; over: */ - tcg_out_movi(s, type, dest, 1); - tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); - tcg_out_movi(s, type, dest, 0); - } + /* Emit: d =3D 1; if (cc) goto over; d =3D 0; over: */ + tcg_out_movi(s, type, dest, 1); + tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); + tcg_out_movi(s, type, dest, 0); + return; + + do_loc: + cc =3D tgen_cmp(s, type, cond, c1, c2, c2const, false); + /* Emit: d =3D 0, t =3D 1, d =3D (cc ? t : d). */ + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); + tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); } =20 static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg de= st, - TCGReg c1, TCGArg c2, int c2const, TCGReg r3) + TCGReg c1, TCGArg c2, int c2const, + TCGArg v3, int v3const) { int cc; if (s390_facilities & FACILITY_LOAD_ON_COND) { cc =3D tgen_cmp(s, type, c, c1, c2, c2const, false); - tcg_out_insn(s, RRF, LOCGR, dest, r3, cc); + if (v3const) { + tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc); + } else { + tcg_out_insn(s, RRF, LOCGR, dest, v3, cc); + } } else { c =3D tcg_invert_cond(c); cc =3D tgen_cmp(s, type, c, c1, c2, c2const, false); =20 /* Emit: if (cc) goto over; dest =3D r3; over: */ tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); - tcg_out_insn(s, RRE, LGR, dest, r3); + tcg_out_insn(s, RRE, LGR, dest, v3); } } =20 @@ -1937,7 +1977,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, break; case INDEX_op_movcond_i32: tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], - args[2], const_args[2], args[3]); + args[2], const_args[2], args[3], const_args[3]); break; =20 case INDEX_op_qemu_ld_i32: @@ -2170,7 +2210,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, break; case INDEX_op_movcond_i64: tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], - args[2], const_args[2], args[3]); + args[2], const_args[2], args[3], const_args[3]); break; =20 OP_32_64(deposit): @@ -2391,7 +2431,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) =3D { .args_ct_str =3D { "r", "r", "rZ", "r", "0" } }; static const TCGTargetOpDef movc_c =3D { .args_ct_str =3D { "r", "r", "rC", "r", "0" } }; - return (s390_facilities & FACILITY_EXT_IMM ? &movc_c : &movc_z= ); + static const TCGTargetOpDef movc_l + =3D { .args_ct_str =3D { "r", "r", "rC", "rI", "0" } }; + return (s390_facilities & FACILITY_EXT_IMM + ? (s390_facilities & FACILITY_LOAD_ON_COND2 + ? &movc_l : &movc_c) + : &movc_z); } case INDEX_op_div2_i32: case INDEX_op_div2_i64: --=20 2.13.5 From nobody Tue Nov 4 11:49:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504039955159686.6247173883395; Tue, 29 Aug 2017 13:52:35 -0700 (PDT) Received: from localhost ([::1]:46907 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmnUu-0005vV-V9 for importer@patchew.org; Tue, 29 Aug 2017 16:52:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49546) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmnQn-0002Xf-UW for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmnQm-0001Wc-Bx for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:18 -0400 Received: from mail-pf0-x22b.google.com ([2607:f8b0:400e:c00::22b]:33713) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmnQm-0001WS-3R for qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:48:16 -0400 Received: by mail-pf0-x22b.google.com with SMTP id r62so13445484pfj.0 for ; Tue, 29 Aug 2017 13:48:15 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id i84sm6633646pfj.139.2017.08.29.13.48.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2017 13:48:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7EKO1ayOrpPVDOid0Oz0SpWK65aO/ZVIVhQGxN0Ans4=; b=QS2vjLqTSDVAWQ/zvYxiWo6s6J1Y3MudsfEvSlTIln7j/lmrkOMtJWqUiUmqCdpASJ KkyHyLz7nnwzBdRnzI0oUMbdnBPqRHJ+sC7ANQp0AATfrm4fUrGDyYK5VhX9jGAQIfHO OJny5XMRbE4aYlUE24N0U0k1FS8IO5sqVbQ94= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7EKO1ayOrpPVDOid0Oz0SpWK65aO/ZVIVhQGxN0Ans4=; b=drSqcRoJ9ighCYiiaPNvg4nohJ2MJkQ82+ssIBUug1/dwXFxi+qA9VkKJ3pcieLxEI rECDzWR+T65z5F4OF8hIsUPaRo2sNtxcZugIhNNoScd1gm/06oumYKtCbnun5TK53vNJ v7dX4vY+B7ffuDfE199nD1XNhrDz9lshfU16aQ3hthBu1z068/ACBAiPb+ABBRfcKRjW kKyke/qVUnxAIdg0GFwm6H92o5k4cYhq3XeCamyYcY2ZX4kAmY7DzhUIXNokJImuM+OH aq4WsoCdr6M+v8XmS2Ksb2is22Zwursb5T/1tqoBasvUSzyzKo4O1Tw4Mm9ofw+HM7w+ HAuQ== X-Gm-Message-State: AHYfb5jY7Yx+uSdo3HIbtIqdu4kSHceR0GJ3YWRKGjB6SXiJOwesb3gQ rslXz3+NC0L8XZvfytbW8g== X-Received: by 10.84.175.195 with SMTP id t61mr1970034plb.240.1504039694769; Tue, 29 Aug 2017 13:48:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 29 Aug 2017 13:47:59 -0700 Message-Id: <20170829204759.6853-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170829204759.6853-1-richard.henderson@linaro.org> References: <20170829204759.6853-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22b Subject: [Qemu-devel] [PATCH 8/8] tcg/s390: Use slbgr for setcond le and leu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Acked-by: Cornelia Huck --- tcg/s390/tcg-target.inc.c | 119 +++++++++++++++++-------------------------= ---- 1 file changed, 43 insertions(+), 76 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 0de968fde2..38b9e791ee 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1084,11 +1084,20 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, =20 have_loc =3D (s390_facilities & FACILITY_LOAD_ON_COND) !=3D 0; =20 - /* For HAVE_LOC, only the path through do_greater is smaller. */ + /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */ + restart: switch (cond) { + case TCG_COND_NE: + /* X !=3D 0 is X > 0. */ + if (c2const && c2 =3D=3D 0) { + cond =3D TCG_COND_GTU; + } else { + break; + } + /* fallthru */ + case TCG_COND_GTU: case TCG_COND_GT: - do_greater: /* The result of a compare has CC=3D2 for GT and CC=3D3 unused. ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */ tgen_cmp(s, type, cond, c1, c2, c2const, true); @@ -1096,49 +1105,33 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, tcg_out_insn(s, RRE, ALCGR, dest, dest); return; =20 - case TCG_COND_GEU: - if (have_loc) { - goto do_loc; - } - do_geu: - /* We need "real" carry semantics, so use SUBTRACT LOGICAL - instead of COMPARE LOGICAL. This may need an extra move. */ - if (c2const) { - tcg_out_mov(s, type, TCG_TMP0, c1); - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RIL, SLFI, TCG_TMP0, c2); - } else { - tcg_out_insn(s, RIL, SLGFI, TCG_TMP0, c2); - } - } else if (s390_facilities & FACILITY_DISTINCT_OPS) { - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RRF, SLRK, TCG_TMP0, c1, c2); - } else { - tcg_out_insn(s, RRF, SLGRK, TCG_TMP0, c1, c2); - } + case TCG_COND_EQ: + /* X =3D=3D 0 is X <=3D 0. */ + if (c2const && c2 =3D=3D 0) { + cond =3D TCG_COND_LEU; } else { - tcg_out_mov(s, type, TCG_TMP0, c1); - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RR, SLR, TCG_TMP0, c2); - } else { - tcg_out_insn(s, RRE, SLGR, TCG_TMP0, c2); - } + break; } - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_insn(s, RRE, ALCGR, dest, dest); - return; + /* fallthru */ =20 case TCG_COND_LEU: - if (have_loc) { - goto do_loc; - } - /* fallthru */ + case TCG_COND_LE: + /* As above, but we're looking for borrow, or !carry. + The second insn computes d - d - borrow, or -1 for true + and 0 for false. So we must mask to 1 bit afterward. */ + tgen_cmp(s, type, cond, c1, c2, c2const, true); + tcg_out_insn(s, RRE, SLBGR, dest, dest); + tgen_andi(s, type, dest, 1); + return; + + case TCG_COND_GEU: case TCG_COND_LTU: case TCG_COND_LT: - /* Swap operands so that we can use GEU/GTU/GT. */ + case TCG_COND_GE: + /* Swap operands so that we can use LEU/GTU/GT/LE. */ if (c2const) { if (have_loc) { - goto do_loc; + break; } tcg_out_movi(s, type, TCG_TMP0, c2); c2 =3D c1; @@ -1149,51 +1142,25 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, c1 =3D c2; c2 =3D t; } - if (cond =3D=3D TCG_COND_LEU) { - goto do_geu; - } cond =3D tcg_swap_cond(cond); - goto do_greater; - - case TCG_COND_NE: - /* X !=3D 0 is X > 0. */ - if (c2const && c2 =3D=3D 0) { - cond =3D TCG_COND_GTU; - goto do_greater; - } - break; - - case TCG_COND_EQ: - if (have_loc) { - goto do_loc; - } - /* X =3D=3D 0 is X <=3D 0 is 0 >=3D X. */ - if (c2const && c2 =3D=3D 0) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0); - c2 =3D c1; - c2const =3D 0; - c1 =3D TCG_TMP0; - goto do_geu; - } - break; + goto restart; =20 default: - break; + g_assert_not_reached(); } =20 cc =3D tgen_cmp(s, type, cond, c1, c2, c2const, false); - /* Emit: d =3D 1; if (cc) goto over; d =3D 0; over: */ - tcg_out_movi(s, type, dest, 1); - tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); - tcg_out_movi(s, type, dest, 0); - return; - - do_loc: - cc =3D tgen_cmp(s, type, cond, c1, c2, c2const, false); - /* Emit: d =3D 0, t =3D 1, d =3D (cc ? t : d). */ - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); - tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); + if (have_loc) { + /* Emit: d =3D 0, t =3D 1, d =3D (cc ? t : d). */ + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); + tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); + } else { + /* Emit: d =3D 1; if (cc) goto over; d =3D 0; over: */ + tcg_out_movi(s, type, dest, 1); + tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); + tcg_out_movi(s, type, dest, 0); + } } =20 static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg de= st, --=20 2.13.5