From nobody Fri May 3 11:17:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503570022252741.5577380330226; Thu, 24 Aug 2017 03:20:22 -0700 (PDT) Received: from localhost ([::1]:47580 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkpFM-0001bM-Rh for importer@patchew.org; Thu, 24 Aug 2017 06:20:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56353) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkpDd-0000hi-6H for qemu-devel@nongnu.org; Thu, 24 Aug 2017 06:18:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkpDa-0006fE-1J for qemu-devel@nongnu.org; Thu, 24 Aug 2017 06:18:33 -0400 Received: from smtp02.citrix.com ([66.165.176.63]:1520) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1dkpDZ-0006es-RM for qemu-devel@nongnu.org; Thu, 24 Aug 2017 06:18:29 -0400 X-IronPort-AV: E=Sophos;i="5.41,420,1498521600"; d="scan'208";a="444959945" From: Roger Pau Monne To: , Date: Thu, 24 Aug 2017 10:47:53 +0100 Message-ID: <20170824094753.77795-3-roger.pau@citrix.com> X-Mailer: git-send-email 2.11.0 (Apple Git-81) In-Reply-To: <20170824094753.77795-1-roger.pau@citrix.com> References: <20170824094753.77795-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 66.165.176.63 Subject: [Qemu-devel] [PATCH QEMU] xen/pt: allow QEMU to request MSI unmasking at bind time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anthony Perard , Stefano Stabellini , qemu-devel@nongnu.org, Jan Beulich , Roger Pau Monne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 When a MSIX interrupt is bound to a guest using xc_domain_update_msi_irq (XEN_DOMCTL_bind_pt_irq) the interrupt is left masked by default. This causes problems with guests that first configure interrupts and clean the per-entry MSIX table mask bit and afterwards enable MSIX globally. In such scenario the Xen internal msixtbl handlers would not detect the unmasking of MSIX entries because vectors are not yet registered since MSIX is not enabled, and vectors would be left masked. Introduce a new flag in the gflags field to signal Xen whether a MSIX interrupt should be unmasked after being bound. Signed-off-by: Roger Pau Monn=C3=A9 Reported-by: Andreas Kinzler --- Cc: Stefano Stabellini Cc: Anthony Perard Cc: Jan Beulich Cc: qemu-devel@nongnu.org --- hw/xen/xen_pt_msi.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c index ff9a79f5d2..c00ac2fd7d 100644 --- a/hw/xen/xen_pt_msi.c +++ b/hw/xen/xen_pt_msi.c @@ -24,6 +24,7 @@ #define XEN_PT_GFLAGS_SHIFT_DM 9 #define XEN_PT_GFLAGSSHIFT_DELIV_MODE 12 #define XEN_PT_GFLAGSSHIFT_TRG_MODE 15 +#define XEN_PT_GFLAGSSHIFT_UNMASKED 16 =20 #define latch(fld) latch[PCI_MSIX_ENTRY_##fld / sizeof(uint32_t)] =20 @@ -155,7 +156,8 @@ static int msi_msix_update(XenPCIPassthroughState *s, int pirq, bool is_msix, int msix_entry, - int *old_pirq) + int *old_pirq, + bool masked) { PCIDevice *d =3D &s->dev; uint8_t gvec =3D msi_vector(data); @@ -171,6 +173,8 @@ static int msi_msix_update(XenPCIPassthroughState *s, table_addr =3D s->msix->mmio_base_addr; } =20 + gflags |=3D masked ? 0 : (1u << XEN_PT_GFLAGSSHIFT_UNMASKED); + rc =3D xc_domain_update_msi_irq(xen_xc, xen_domid, gvec, pirq, gflags, table_addr); =20 @@ -274,7 +278,7 @@ int xen_pt_msi_update(XenPCIPassthroughState *s) { XenPTMSI *msi =3D s->msi; return msi_msix_update(s, msi_addr64(msi), msi->data, msi->pirq, - false, 0, &msi->pirq); + false, 0, &msi->pirq, false); } =20 void xen_pt_msi_disable(XenPCIPassthroughState *s) @@ -355,7 +359,8 @@ static int xen_pt_msix_update_one(XenPCIPassthroughStat= e *s, int entry_nr, } =20 rc =3D msi_msix_update(s, entry->addr, entry->data, pirq, true, - entry_nr, &entry->pirq); + entry_nr, &entry->pirq, + vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT); =20 if (!rc) { entry->updated =3D false; --=20 2.11.0 (Apple Git-81)