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Violators will be prosecuted; Mon, 21 Aug 2017 16:00:51 -0400 Received: from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com [9.57.199.110]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v7LK0oMY29491392; Mon, 21 Aug 2017 20:00:50 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 79D20AE056; Mon, 21 Aug 2017 16:01:11 -0400 (EDT) Received: from morokweng.ibm.com (unknown [9.80.206.105]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP id 85AF5AE034; Mon, 21 Aug 2017 16:01:09 -0400 (EDT) From: Thiago Jung Bauermann To: qemu-ppc@nongnu.org Date: Mon, 21 Aug 2017 17:00:36 -0300 X-Mailer: git-send-email 2.14.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 17082120-0052-0000-0000-00000253118E X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007586; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000223; SDB=6.00905676; UDB=6.00453859; IPR=6.00685879; BA=6.00005545; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016797; XFM=3.00000015; UTC=2017-08-21 20:00:53 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17082120-0053-0000-0000-000051BEA0BA Message-Id: <20170821200036.15036-1-bauerman@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-08-21_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1708210312 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id v7LJx5Xb057388 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH] spapr: Add ibm, processor-storage-keys property to CPU DT node X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Ellerman , Ram Pai , Alexander Graf , qemu-devel@nongnu.org, Paul Mackerras , Thiago Jung Bauermann , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" LoPAPR says: =E2=80=9Cibm,processor-storage-keys=E2=80=9D property name indicating the number of virtual storage keys supported by the processor described by this node. prop-encoded-array: Consists of two cells encoded as with encode-int. The first cell represents the number of virtual storage keys supported for data accesses while the second cell represents the number of virtual storage keys supported for instruction accesses. The cell value of zero indicates that no storage keys are supported for the access type. pHyp provides the property above but there's a bug in P8 firmware where the second cell is zero even though POWER8 supports instruction access keys. This bug will be fixed for P9. Tested with KVM on POWER8 Firenze machine and with TCG on x86_64 machine. Signed-off-by: Thiago Jung Bauermann --- The sysfs files are provided by this patch for Linux: https://lists.ozlabs.org/pipermail/linuxppc-dev/2017-August/162005.html I realize that this patch can't be committed before the Linux one goes in, but I'd appreciate feedback so that it will be ready by the time the kernel side is accepted. hw/ppc/spapr.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/ppc/spapr.h | 6 ++++ 2 files changed, 82 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f7a19720dcdf..a665e4d830f7 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -605,6 +605,80 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *= fdt, int offset, pcc->radix_page_info->count * sizeof(radix_AP_encodings[0])))); } + + if (spapr->storage_keys) { + uint32_t val[2]; + + val[0] =3D cpu_to_be32(spapr->storage_keys); + val[1] =3D spapr->insn_keys ? val[0] : 0; + + _FDT(fdt_setprop(fdt, offset, "ibm,processor-storage-keys", + val, sizeof(val))); + } +} + +#define SYSFS_PROT_KEYS_PATH "/sys/kernel/mm/protection_keys/" +#define SYSFS_USABLE_STORAGE_KEYS SYSFS_PROT_KEYS_PATH "usable_keys" +#define SYSFS_DISABLE_EXEC_KEYS SYSFS_PROT_KEYS_PATH "disable_execute_supp= orted" + +static void setup_storage_keys(CPUPPCState *env, sPAPRMachineState *spapr) +{ + if (!(env->mmu_model & POWERPC_MMU_AMR)) + return; + + if (kvm_enabled()) { + char buf[sizeof("false\n")]; + uint32_t keys; + FILE *fd; + + /* + * With KVM, we allow the guest to use the keys which the kernel t= ells + * us are available. + */ + + fd =3D fopen(SYSFS_USABLE_STORAGE_KEYS, "r"); + if (!fd) { + error_report("%s: open %s failed", __func__, + SYSFS_USABLE_STORAGE_KEYS); + return; + } + + if (fscanf(fd, "%u", &keys) !=3D 1) { + error_report("%s: error reading %s", __func__, + SYSFS_USABLE_STORAGE_KEYS); + fclose(fd); + return; + } + + fclose(fd); + + /* Now find out whether the keys can be used for instruction acces= s. */ + + fd =3D fopen(SYSFS_DISABLE_EXEC_KEYS, "r"); + if (!fd) { + error_report("%s: open %s failed", __func__, + SYSFS_USABLE_STORAGE_KEYS); + return; + } + + if (!fread(buf, 1, sizeof(buf), fd)) { + error_report("%s: error reading %s", __func__, + SYSFS_DISABLE_EXEC_KEYS); + fclose(fd); + return; + } + + fclose(fd); + + spapr->storage_keys =3D keys; + spapr->insn_keys =3D !strncmp(buf, "true\n", sizeof(buf)); + } else { + /* Without KVM, all keys provided by the architecture are availabl= e. */ + spapr->storage_keys =3D 32; + + /* POWER7 doesn't support instruction access keys. */ + spapr->insn_keys =3D POWERPC_MMU_VER(env->mmu_model) !=3D POWERPC_= MMU_VER_2_06; + } } =20 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spap= r) @@ -619,6 +693,8 @@ static void spapr_populate_cpus_dt_node(void *fdt, sPAP= RMachineState *spapr) _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); =20 + setup_storage_keys(&POWERPC_CPU(first_cpu)->env, spapr); + /* * We walk the CPUs in reverse order to ensure that CPU DT nodes * created by fdt_add_subnode() end up in the right order in FDT diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 2a303a705c17..15af12010779 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -122,6 +122,12 @@ struct sPAPRMachineState { * occurs during the unplug process. */ QTAILQ_HEAD(, sPAPRDIMMState) pending_dimm_unplugs; =20 + /* Number of processor storage keys available to the guest. */ + uint32_t storage_keys; + + /* Whether storage keys can control instruction access. */ + bool insn_keys; + /*< public >*/ char *kvm_type; MemoryHotplugState hotplug_memory;