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X-Received-From: 2a00:1450:400c:c0c::235 Subject: [Qemu-devel] [RFC PATCH 2/9] tcg: introduce the concepts of a TCGv_vec register type X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently it only makes sense for globals - i.e. registers directly mapped to CPUEnv. --- tcg/README | 1 + tcg/tcg.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/tcg/README b/tcg/README index f116b7b694..e0868d95b4 100644 --- a/tcg/README +++ b/tcg/README @@ -57,6 +57,7 @@ typed. A number of types are supported: =20 TCGv_i32 - 32 bit integer TCGv_i64 - 64 bit integer + TCGv_vec - an arbitrary sized vector register TCGv - target pointer (aliased to 32 or 64 bit integer) TCGv_ptr - host pointer (used for direct access to host structures) =20 diff --git a/tcg/tcg.h b/tcg/tcg.h index 17b7750ee6..d75636b6ab 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -256,6 +256,7 @@ typedef struct TCGPool { typedef enum TCGType { TCG_TYPE_I32, TCG_TYPE_I64, + TCG_TYPE_VECTOR, TCG_TYPE_COUNT, /* number of different types */ =20 /* An alias for the size of the host register. */ @@ -431,6 +432,7 @@ typedef tcg_target_ulong TCGArg; typedef struct TCGv_i32_d *TCGv_i32; typedef struct TCGv_i64_d *TCGv_i64; typedef struct TCGv_ptr_d *TCGv_ptr; +typedef struct TCGv_vec_d *TCGv_vec; typedef TCGv_ptr TCGv_env; #if TARGET_LONG_BITS =3D=3D 32 #define TCGv TCGv_i32 @@ -450,6 +452,11 @@ static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(i= ntptr_t i) return (TCGv_i64)i; } =20 +static inline TCGv_vec QEMU_ARTIFICIAL MAKE_TCGV_VEC(intptr_t i) +{ + return (TCGv_vec)i; +} + static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i) { return (TCGv_ptr)i; @@ -465,6 +472,11 @@ static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TC= Gv_i64 t) return (intptr_t)t; } =20 +static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_VEC(TCGv_vec t) +{ + return (intptr_t)t; +} + static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t) { return (intptr_t)t; @@ -788,6 +800,7 @@ int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intp= tr_t, const char *); =20 TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name); TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name); +TCGv_vec tcg_global_reg_new_vec(TCGReg reg, const char *name); =20 TCGv_i32 tcg_temp_new_internal_i32(int temp_local); TCGv_i64 tcg_temp_new_internal_i64(int temp_local); @@ -829,6 +842,13 @@ static inline TCGv_i64 tcg_temp_local_new_i64(void) return tcg_temp_new_internal_i64(1); } =20 +static inline TCGv_vec tcg_global_mem_new_vec(TCGv_ptr reg, intptr_t offse= t, + const char *name) +{ + int idx =3D tcg_global_mem_new_internal(TCG_TYPE_VECTOR, reg, offset, = name); + return MAKE_TCGV_VEC(idx); +} + #if defined(CONFIG_DEBUG_TCG) /* If you call tcg_clear_temp_count() at the start of a section of * code which is not supposed to leak any TCG temporaries, then --=20 2.13.0