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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id n11sm20626318pfg.15.2017.08.15.07.57.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 Aug 2017 07:57:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SgAaEYM18OE+mUpjVkYzlZyVnbr8ndjZmIY5W1zNvyI=; b=ZoFcqDuet/QGi2nRgJNNHLha7S3eqMac5sj5ziUv5J3cp6pdhpxQPweKEV5STN4jV5 OEQf8PD4f/mfeUG/3ceWg7a9L7DhNzIa7t10rp+gmUPR6NW0q9fC6b9fGx9xu2J7bWKs 4W1OPJMDNKW/IRXczKvGirPC7gTpCwoDWZP0I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SgAaEYM18OE+mUpjVkYzlZyVnbr8ndjZmIY5W1zNvyI=; b=fbh4fcQ0jY9MvZ+H0QoghBPSl3PIryIi+jJfdhgSULHSlkBp7JsgmWnQvEEUGcTSrd y1C06xp9Dvka6NGaOzDbfttY8MX8a/Ds0BoA6UsYRgRIbHb0tnB2S20a2LdWpBJzPl+L cNJBcJFWL68bBzQ8zEM8IqBEf3o6DOSP9Ebna5t6KlTxcImszxmsGzIzFj4TUa5H90YF n+PF5w0YzNT1s2ubV6P41nb6IXkoBlyEq070FrOc/SnbeByxXXyr2QYc1vMD64S+98PJ Es5vlqlKhpLkRTRCAtWHRx+l1vD3GnPwnPLb3rrMGTl2lJjR1YmcmREJ4boMtP4Uy7ok 3RRw== X-Gm-Message-State: AHYfb5hc9DSjNJwDRyzFyxG13LOE9bsKvgY47XGSwHoJdum0RU3Y6D1/ F+ZZ4hnRCX+XtGi+iDJFlw== X-Received: by 10.84.167.230 with SMTP id i35mr31743455plg.181.1502809041202; Tue, 15 Aug 2017 07:57:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 15 Aug 2017 07:57:14 -0700 Message-Id: <20170815145714.17635-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.4 In-Reply-To: <20170815145714.17635-1-richard.henderson@linaro.org> References: <20170815145714.17635-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::236 Subject: [Qemu-devel] [PATCH v2 for-2.10 3/3] target/arm: Require alignment for load exclusive X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Acording to the ARM ARM exclusive loads require the same allignment as exclusive stores. Let's update the memops used for the load to match that of the store. This adds the alignment requirement to the memops. Reviewed-by: Edgar E. Iglesias Signed-off-by: Alistair Francis [rth: Require 16-byte alignment for 64-bit LDXP.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index eac545e4f2..2200e25be0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1861,7 +1861,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, g_assert(size >=3D 2); if (size =3D=3D 2) { /* The pair must be single-copy atomic for the doubleword. */ - memop |=3D MO_64; + memop |=3D MO_64 | MO_ALIGN; tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); if (s->be_data =3D=3D MO_LE) { tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, = 32); @@ -1871,10 +1871,11 @@ static void gen_load_exclusive(DisasContext *s, int= rt, int rt2, tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0,= 32); } } else { - /* The pair must be single-copy atomic for *each* doubleword, - but not the entire quadword. */ + /* The pair must be single-copy atomic for *each* doubleword, = not + the entire quadword, however it must be quadword aligned. = */ memop |=3D MO_64; - tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); + tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, + memop | MO_ALIGN_16); =20 TCGv_i64 addr2 =3D tcg_temp_new_i64(); tcg_gen_addi_i64(addr2, addr, 8); @@ -1885,7 +1886,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); } } else { - memop |=3D size; + memop |=3D size | MO_ALIGN; tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop); tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); } --=20 2.13.4