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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id q199sm1335819pfq.135.2017.08.03.23.23.22 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 23:23:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=h7V8nRljnln2mzYsOMBJaZTFKJXHGLQipaVpf2qy0jI=; b=qoS/t7ICx39mALzzx1I9Vj+Mpv3bBAl596KAvOLjqfBEqpmAsXWRy4fR22M/ns4eHP QJmOd6tL5ZLT7uKgtP8qZLH/TSOvjqMaAIaXiKR4/j0I0k06UcQyTAes04iT2LD2elvV 7SJNvX2WxNuQwFvAtp0061E2IOcrQEllNWku40KCatgdF0wkypP4C4qKMhFKX3p8XKZK FTBXVZFl9SFepqFTLA60nXL5rIHg+dkXxRZQQdNxskdII7SvNBEsC3/zjZ9zeQkivUOr PcMhDUlyZqypV7bJnkUrDR5LjDp4iSMWYcMVBYjtGY2RzyT9XI6jEK4ZYMLgg7Qk6KVr LHPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=h7V8nRljnln2mzYsOMBJaZTFKJXHGLQipaVpf2qy0jI=; b=piO0+dfjuhl3huB8eyAEow/ju6ARepfY9MGCZWTwqL2jzK68cZ5MgZPkUqWo5q6pOo ar9wwT7xjvuD7xaj1P4D1qJ6IP9OSZwyJthzyE/jZd4dDfPPLDN8wCOYpY/HzbAN3BrI MSJnIpQbuOuIaF3CTU6FpQNIZNTx9O1sObelj747h9OQXdaxDkWAE0V6JMrWEUlDDyay 7jee8Xqh1m7lXmHsUCmNgNkIKZLJaza9Bd+/lMv2wdGel1P/tWf0AgOWd/t3Szjf9lxR yUR/zlmRa8fc8pZ6vZUcIoYX95Et+tJ9Pb+qCVzKJoEIGvofVRVizlWr5RFV48OzWzru nqyA== X-Gm-Message-State: AIVw1122YSZbGuLfJ0kO6jD5Bs7klXxGF9cz1BW6+1qPHiDTpMX2Dz6x epLkJqfC6Eyx841wQ5Q= X-Received: by 10.99.95.76 with SMTP id t73mr1251773pgb.349.1501827803828; Thu, 03 Aug 2017 23:23:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 23:23:14 -0700 Message-Id: <20170804062314.12594-7-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804062314.12594-1-rth@twiddle.net> References: <20170804062314.12594-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH for-2.11 6/6] tcg/i386: Use pdep for deposit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 4 ++- tcg/i386/tcg-target.inc.c | 82 ++++++++++++++++++++++++++++++++++++++-----= ---- 2 files changed, 70 insertions(+), 16 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 85b0ccd98c..e512648c95 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -148,7 +148,9 @@ extern bool have_popcnt; #endif =20 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ - (((ofs) =3D=3D 0 && (len) =3D=3D 8) || ((ofs) =3D=3D 8 && (len) =3D=3D= 8) || \ + (have_bmi2 || \ + ((ofs) =3D=3D 0 && (len) =3D=3D 8) || \ + ((ofs) =3D=3D 8 && (len) =3D=3D 8) || \ ((ofs) =3D=3D 0 && (len) =3D=3D 16)) #define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid =20 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 69587c82de..aeefb72aa0 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -329,6 +329,7 @@ static inline int tcg_target_const_match(tcg_target_lon= g val, TCGType type, #define OPC_MOVSLQ (0x63 | P_REXW) #define OPC_MOVZBL (0xb6 | P_EXT) #define OPC_MOVZWL (0xb7 | P_EXT) +#define OPC_PDEP (0xf5 | P_EXT38 | P_SIMDF2) #define OPC_PEXT (0xf5 | P_EXT38 | P_SIMDF3) #define OPC_POP_r32 (0x58) #define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) @@ -554,14 +555,12 @@ static void tcg_out_sfx_pool_imm(TCGContext *s, int r= , tcg_target_ulong data) tcg_out32(s, 0); } =20 -#if 0 static void tcg_out_opc_pool_imm(TCGContext *s, int opc, int r, tcg_target_ulong data) { tcg_out_opc(s, opc, r, 0, 0); tcg_out_sfx_pool_imm(s, r, data); } -#endif =20 static void tcg_out_vex_pool_imm(TCGContext *s, int opc, int r, int v, tcg_target_ulong data) @@ -1902,7 +1901,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - TCGArg a0, a1, a2, a3; + TCGArg a0, a1, a2, a3, a4; int c, const_a2, vexop, rexw =3D 0; =20 #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -2262,17 +2261,68 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, #endif =20 OP_32_64(deposit): - if (args[3] =3D=3D 0 && args[4] =3D=3D 8) { - /* load bits 0..7 */ - tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0); - } else if (args[3] =3D=3D 8 && args[4] =3D=3D 8) { - /* load bits 8..15 */ - tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); - } else if (args[3] =3D=3D 0 && args[4] =3D=3D 16) { - /* load bits 0..15 */ - tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); - } else { - tcg_abort(); + a3 =3D args[3]; + a4 =3D args[4]; + { + tcg_target_ulong mask =3D deposit64(0, a3, a4, -1); + + if (const_args[1]) { + tcg_debug_assert(have_bmi2); + if (a3 =3D=3D 0 && a0 =3D=3D a2) { + if (a4 <=3D 32) { + tgen_arithi(s, ARITH_AND, a0, mask, 0); + } else { + tcg_out_opc_pool_imm(s, OPC_ARITH_GvEv + P_REXW + + ARITH_AND * 8, a0, mask); + } + } else { + tcg_out_vex_pool_imm(s, OPC_PDEP + + (a3 + a4 > 32) * P_REXW, + a0, a2, mask); + } + a1 &=3D ~mask; + if (a1 !=3D 0) { + if (!rexw || a1 =3D=3D (int)a1) { + tgen_arithi(s, ARITH_OR + rexw, a0, a1, 0); + } else { + tcg_out_opc_pool_imm(s, OPC_ARITH_GvEv + P_REXW + + ARITH_OR * 8, a0, a1); + } + } + } else if (a0 =3D=3D a1 && a3 =3D=3D 0 && a4 =3D=3D 8) { + /* load bits 0..7 */ + tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2,= a0); + } else if (a0 =3D=3D a1 && a3 =3D=3D 8 && a4 =3D=3D 8 && a0 < = 4 && a2 < 8) { + /* load bits 8..15 */ + tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); + } else if (a0 =3D=3D a1 && a3 =3D=3D 0 && a4 =3D=3D 16) { + /* load bits 0..15 */ + tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); + } else { + TCGType type =3D rexw ? TCG_TYPE_I64 : TCG_TYPE_I32; + TCGReg t1 =3D tcg_reg_alloc_new(s, type); + TCGReg t2 =3D t1; + + tcg_debug_assert(have_bmi2); + tcg_out_movi(s, type, t1, mask); + if (a0 =3D=3D a2) { + t2 =3D tcg_reg_alloc_new(s, type); + tcg_out_vex_modrm(s, OPC_ANDN + rexw, t2, t1, a1); + if (a3 =3D=3D 0) { + tgen_arithr(s, ARITH_AND + rexw, a0, t1); + } else { + tcg_out_vex_modrm(s, OPC_PDEP + rexw, a0, a2, t1); + } + } else { + tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, t1, a1); + if (a3 =3D=3D 0) { + tgen_arithr(s, ARITH_AND + rexw, t1, a2); + } else { + tcg_out_vex_modrm(s, OPC_PDEP + rexw, t1, a2, t1); + } + } + tgen_arithr(s, ARITH_OR + rexw, a0, t2); + } } break; =20 @@ -2480,7 +2530,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) { static const TCGTargetOpDef dep =3D { .args_ct_str =3D { "Q", "0", "Q" } }; - return &dep; + static const TCGTargetOpDef pdep + =3D { .args_ct_str =3D { "r", "ri", "r" } }; + return have_bmi2 ? &pdep : &dep; } case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: --=20 2.13.3