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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id q199sm1335819pfq.135.2017.08.03.23.23.16 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 23:23:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=paorHe3sqTqEIdLPxMp8BCggiDO+kJcJ6vXqbOfRtig=; b=kiqBtk3vz29wzbCA5Id1KuOxJaMHKxYCzULbOMbN2O3V2DW/rTJRh50DPGJUH+tC6l 4RcPNAPYAEmSSUNUZ90/o7kBrBppmaY2CaVLJky7DxFP2L5NuDPnSDq0G4fcSDwvElRB UfjNXuvtYkn7UpFQVRlgsPb/aCoMkG5eELjXzmdXnp+KxutOVuCLRrOttp684RVwkxvu /VbAbHBHF+Pm3uQ8ntAzZ+J1LPAkdSUNjHTh/Y/pYTBWb5bkS3KN9QklvVGAf13IlXSA BGGcTMGKe/FRj/QCISxooqHnZEsoP6bCFt8M5ZPdPi09v5Cz1EocJKsT0xkAroy/8F7e RPtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=paorHe3sqTqEIdLPxMp8BCggiDO+kJcJ6vXqbOfRtig=; b=KOb2EJeR+TjsyvqNOZeuw5MG25PwXuMDGJAx30I1nsWGyNfuBRjf2Pt0jJlc6h/PEs eZV+tuFaR8eHAoKfiWd+7GjoEwBXahbH4hphkU+nWPuYgkwaSUpRf0oTEJ7A/SVXKkwT JdwHr8IAUVeCu8+8qViu57yCZL/ch/QRuHw8fomMrBHN6+0H3F3qhl77MBTkvJgghOfS GW0vYPPpBUvDp8JmLiXngKPT5VOczodcXyboxmsZ6SmmPZZgsz7PiT/1VSp1mvfbQ45P aH00WU5/qRmp/Ck9rsW8nshARvsCIJ7cwx0ThmMLGLrAKxZIp6kjtN8b8u4/Ocu1asFf FO2w== X-Gm-Message-State: AIVw110oQxJiTdZ1m9eFfHhHvHPVjiWHaRFQe0uTZvw57zVizXnliMHn tqMqBLQFs2bJPtDqEn4= X-Received: by 10.101.69.196 with SMTP id m4mr1216503pgr.105.1501827798075; Thu, 03 Aug 2017 23:23:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 23:23:09 -0700 Message-Id: <20170804062314.12594-2-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804062314.12594-1-rth@twiddle.net> References: <20170804062314.12594-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH for-2.11 1/6] tcg: Add tcg_reg_alloc_new X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows the backend to allocate an otherwise unused register. This can allow the backend to avoid having to reserve a full-time temporary register. Signed-off-by: Richard Henderson --- tcg/tcg.h | 1 + tcg/tcg.c | 58 +++++++++++++++++++++++++++++++++++++++++++++------------- 2 files changed, 46 insertions(+), 13 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index ac94133870..dd97095af5 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -655,6 +655,7 @@ struct TCGContext { uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */ uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */ =20 + TCGRegSet regs_in_use; TCGRegSet reserved_regs; intptr_t current_frame_offset; intptr_t frame_start; diff --git a/tcg/tcg.c b/tcg/tcg.c index fd8a3dfe93..787c8ba0f7 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -112,6 +112,8 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TC= GArg val, static void tcg_out_call(TCGContext *s, tcg_insn_unit *target); static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct); +static TCGReg tcg_reg_alloc_new(TCGContext *s, TCGType t) + __attribute__((unused)); #ifdef TCG_TARGET_NEED_LDST_LABELS static bool tcg_out_ldst_finalize(TCGContext *s); #endif @@ -1947,16 +1949,19 @@ static void temp_sync(TCGContext *s, TCGTemp *ts, /* If we're going to free the temp immediately, then we won't require it later in a register, so attempt to store the constant to memory directly. */ - if (free_or_dead - && tcg_out_sti(s, ts->type, ts->val, - ts->mem_base->reg, ts->mem_offset)) { - break; + if (free_or_dead) { + s->regs_in_use =3D -1; + if (tcg_out_sti(s, ts->type, ts->val, + ts->mem_base->reg, ts->mem_offset)) { + break; + } } temp_load(s, ts, tcg_target_available_regs[ts->type], allocated_regs); /* fallthrough */ =20 case TEMP_VAL_REG: + s->regs_in_use =3D -1; tcg_out_st(s, ts->type, ts->reg, ts->mem_base->reg, ts->mem_offset); break; @@ -2015,6 +2020,14 @@ static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet= desired_regs, tcg_abort(); } =20 +static TCGReg tcg_reg_alloc_new(TCGContext *s, TCGType t) +{ + TCGReg r; + r =3D tcg_reg_alloc(s, tcg_target_available_regs[t], s->regs_in_use, 0= ); + tcg_regset_set_reg(s->regs_in_use, r); + return r; +} + /* Make sure the temporary is in a register. If needed, allocate the regi= ster from DESIRED while avoiding ALLOCATED. */ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, @@ -2027,11 +2040,13 @@ static void temp_load(TCGContext *s, TCGTemp *ts, T= CGRegSet desired_regs, return; case TEMP_VAL_CONST: reg =3D tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirec= t_base); + s->regs_in_use =3D allocated_regs; tcg_out_movi(s, ts->type, reg, ts->val); ts->mem_coherent =3D 0; break; case TEMP_VAL_MEM: reg =3D tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirec= t_base); + s->regs_in_use =3D -1; tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); ts->mem_coherent =3D 1; break; @@ -2105,6 +2120,7 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGT= emp *ots, { if (ots->fixed_reg) { /* For fixed registers, we do not do any constant propagation. */ + s->regs_in_use =3D s->reserved_regs; tcg_out_movi(s, ots->type, ots->reg, val); return; } @@ -2129,17 +2145,16 @@ static void tcg_reg_alloc_movi(TCGContext *s, const= TCGArg *args, TCGTemp *ots =3D &s->temps[args[0]]; tcg_target_ulong val =3D args[1]; =20 + s->regs_in_use =3D s->reserved_regs; tcg_reg_alloc_do_movi(s, ots, val, arg_life); } =20 static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def, const TCGArg *args, TCGLifeData arg_life) { - TCGRegSet allocated_regs; TCGTemp *ts, *ots; TCGType otype, itype; =20 - tcg_regset_set(allocated_regs, s->reserved_regs); ots =3D &s->temps[args[0]]; ts =3D &s->temps[args[1]]; =20 @@ -2153,6 +2168,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOpDef *def, if (IS_DEAD_ARG(1)) { temp_dead(s, ts); } + s->regs_in_use =3D s->reserved_regs; tcg_reg_alloc_do_movi(s, ots, val, arg_life); return; } @@ -2162,7 +2178,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TC= GOpDef *def, the SOURCE value into its own register first, that way we don't have to reload SOURCE the next time it is used. */ if (ts->val_type =3D=3D TEMP_VAL_MEM) { - temp_load(s, ts, tcg_target_available_regs[itype], allocated_regs); + temp_load(s, ts, tcg_target_available_regs[itype], s->reserved_reg= s); } =20 tcg_debug_assert(ts->val_type =3D=3D TEMP_VAL_REG); @@ -2173,12 +2189,14 @@ static void tcg_reg_alloc_mov(TCGContext *s, const = TCGOpDef *def, if (!ots->mem_allocated) { temp_allocate_frame(s, args[0]); } + s->regs_in_use =3D -1; tcg_out_st(s, otype, ts->reg, ots->mem_base->reg, ots->mem_offset); if (IS_DEAD_ARG(1)) { temp_dead(s, ts); } temp_dead(s, ots); } else { + TCGRegSet allocated_regs; if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) { /* the mov can be suppressed */ if (ots->val_type =3D=3D TEMP_VAL_REG) { @@ -2188,19 +2206,21 @@ static void tcg_reg_alloc_mov(TCGContext *s, const = TCGOpDef *def, temp_dead(s, ts); } else { if (ots->val_type !=3D TEMP_VAL_REG) { - /* When allocating a new register, make sure to not spill = the - input one. */ + /* When allocating a new register, make sure to not + spill the input one. */ + allocated_regs =3D s->reserved_regs; tcg_regset_set_reg(allocated_regs, ts->reg); ots->reg =3D tcg_reg_alloc(s, tcg_target_available_regs[ot= ype], allocated_regs, ots->indirect_bas= e); } + s->regs_in_use =3D -1; tcg_out_mov(s, otype, ots->reg, ts->reg); } ots->val_type =3D TEMP_VAL_REG; ots->mem_coherent =3D 0; s->reg_to_temp[ots->reg] =3D ots; if (NEED_SYNC_ARG(0)) { - temp_sync(s, ots, allocated_regs, 0); + temp_sync(s, ots, s->reserved_regs, 0); } } } @@ -2281,6 +2301,7 @@ static void tcg_reg_alloc_op(TCGContext *s, and move the temporary register into it */ reg =3D tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, ts->indirect_base); + s->regs_in_use =3D -1; tcg_out_mov(s, ts->type, reg, ts->reg); } new_args[i] =3D reg; @@ -2355,6 +2376,7 @@ static void tcg_reg_alloc_op(TCGContext *s, } =20 /* emit instruction */ + s->regs_in_use =3D i_allocated_regs | o_allocated_regs; tcg_out_op(s, opc, new_args, const_args); =20 /* move the outputs in the correct register if needed */ @@ -2362,6 +2384,7 @@ static void tcg_reg_alloc_op(TCGContext *s, ts =3D &s->temps[args[i]]; reg =3D new_args[i]; if (ts->fixed_reg && ts->reg !=3D reg) { + s->regs_in_use =3D -1; tcg_out_mov(s, ts->type, ts->reg, reg); } if (NEED_SYNC_ARG(i)) { @@ -2420,6 +2443,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, ts =3D &s->temps[arg]; temp_load(s, ts, tcg_target_available_regs[ts->type], s->reserved_regs); + s->regs_in_use =3D -1; tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_off= set); } #ifndef TCG_TARGET_STACK_GROWSUP @@ -2428,7 +2452,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, } =20 /* assign input registers */ - tcg_regset_set(allocated_regs, s->reserved_regs); + allocated_regs =3D s->reserved_regs; for(i =3D 0; i < nb_regs; i++) { arg =3D args[nb_oargs + i]; if (arg !=3D TCG_CALL_DUMMY_ARG) { @@ -2438,6 +2462,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, =20 if (ts->val_type =3D=3D TEMP_VAL_REG) { if (ts->reg !=3D reg) { + s->regs_in_use =3D -1; tcg_out_mov(s, ts->type, reg, ts->reg); } } else { @@ -2458,7 +2483,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, temp_dead(s, &s->temps[args[i]]); } } - =20 + /* clobber call registers */ for (i =3D 0; i < TCG_TARGET_NB_REGS; i++) { if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { @@ -2476,10 +2501,16 @@ static void tcg_reg_alloc_call(TCGContext *s, int n= b_oargs, int nb_iargs, save_globals(s, allocated_regs); } =20 + s->regs_in_use =3D allocated_regs; tcg_out_call(s, func_addr); =20 /* assign output registers and emit moves if needed */ - for(i =3D 0; i < nb_oargs; i++) { + allocated_regs =3D s->reserved_regs; + for (i =3D 0; i < nb_oargs; i++) { + reg =3D tcg_target_call_oarg_regs[i]; + tcg_regset_set_reg(allocated_regs, reg); + } + for (i =3D 0; i < nb_oargs; i++) { arg =3D args[i]; ts =3D &s->temps[arg]; reg =3D tcg_target_call_oarg_regs[i]; @@ -2487,6 +2518,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_= oargs, int nb_iargs, =20 if (ts->fixed_reg) { if (ts->reg !=3D reg) { + s->regs_in_use =3D -1; tcg_out_mov(s, ts->type, ts->reg, reg); } } else { --=20 2.13.3 From nobody Mon May 6 07:58:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id q199sm1335819pfq.135.2017.08.03.23.23.18 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 23:23:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=DBnfsR/Yvxo7vwrjcPDGY/LZWZ5bxnbCcScFvAst9d8=; b=RUK68BqPLm6fkWL1f8dU6TWYMl5ZZuyvN8Rc+AMzp18wbttbOW8hg/EeEABXBl+Za6 EeCBm2K0sqTmE4sV/sVZ8mBC1Rr/S1XyQ672rbrPO45CCGpKjZSrZdjJz9cMXExjEpQV 2D4cCXCWe1nUb0hkMzZtA8f0m8Wyg0aWEP9RJO2AbxIKnvGX4xLaXeYFWjxl53OwtlUK pAiCoW3fG/DQrhJDbvIfHdX2wWF1nWmRgjECuXI19Ed6okmpUEVr7T243Njs7bH3QMcS eFBYrL1Bp6Uwhp4y5/ul7Ta6BKz0SH9Gjbti1O+TjII9m373HwW0/KfcwBBRHOekY/g6 PHJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=DBnfsR/Yvxo7vwrjcPDGY/LZWZ5bxnbCcScFvAst9d8=; b=Je45d9vmHrTcGK1XeSOdPHlOPNfgyIlu6Ne45euP38bk4KLBEyh9lRUvj0dP8oW6ji jFWljFfwD6DAxWPCsw39U0/SulstY6QprNT0pM397JbN/SUUh4hofT7Bk7qpuiKNp3JN tTLSP62uPoft4OdgNzgtHw66aNEhBmtSYXnV388gTNilrxv8mE6OO+N7qVnAaK11biQi LG0L6aWbUixqe/UWVMq4gliwj4UvVwtRxhV/qYqFBsY6HV2T3Niq/AK0JwZyNX9Qpvk+ nlaPiTmSnMpp7wmw5t7deR6uzLvLnSEoo7s4S76tyhYYpAT5Mx0eCbMfaXg9Kfv7TpBf i3Qg== X-Gm-Message-State: AIVw110nIGMNf9prBv+to7xN9We8/G+EodKe4GEurQHzFye3k8KcreiR 3ei3XjSR+XImaXWzNrs= X-Received: by 10.98.70.27 with SMTP id t27mr1291983pfa.103.1501827799074; Thu, 03 Aug 2017 23:23:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 23:23:10 -0700 Message-Id: <20170804062314.12594-3-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804062314.12594-1-rth@twiddle.net> References: <20170804062314.12594-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH for-2.11 2/6] disas/i386: Fix disassembly of two-byte vex prefixes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- disas/i386.c | 1 + 1 file changed, 1 insertion(+) diff --git a/disas/i386.c b/disas/i386.c index f1e376ca4a..7a238b203b 100644 --- a/disas/i386.c +++ b/disas/i386.c @@ -3559,6 +3559,7 @@ ckvexprefix (void) } else { /* Two byte VEX prefix. */ newrex |=3D (vex2 & 0x80 ? 0 : REX_R); + newpfx |=3D PREFIX_VEX_0F; codep +=3D 2; } =20 --=20 2.13.3 From nobody Mon May 6 07:58:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501828236943700.8937438006744; Thu, 3 Aug 2017 23:30:36 -0700 (PDT) Received: from localhost ([::1]:38614 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddW82-0001QM-Uz for importer@patchew.org; Fri, 04 Aug 2017 02:30:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51526) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddW14-0003Wz-Iy for qemu-devel@nongnu.org; Fri, 04 Aug 2017 02:23:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddW13-0005RD-JX for qemu-devel@nongnu.org; Fri, 04 Aug 2017 02:23:22 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:38703) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddW13-0005QP-Ct for qemu-devel@nongnu.org; Fri, 04 Aug 2017 02:23:21 -0400 Received: by mail-pg0-x241.google.com with SMTP id 123so894305pga.5 for ; Thu, 03 Aug 2017 23:23:21 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id q199sm1335819pfq.135.2017.08.03.23.23.19 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 23:23:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=KJPypG4nUZebT4tKMcdJjuOyrLByu7LUhZZIqXihfsw=; b=H4QlG3gD80wE+6moSxjdWz8BHW+FUj0GSp6buMg3Cf5S1rr/aPLcsvwcrWkBqCsXp+ JUKf6sRpDQhhlqR7wQoAZOoud8wgScfS+KVpufkdUN7Fe9feTDcUkQP5XHY3dO5eDPWE wfrhgsZY/xj7AOECUYEBdVishYgB76lY3H4txTfW3cRLZhD/DEjOad9O4ZM3/NKoZRuj 8U2cVEP6K5Xfre1ERb3qT1hSLlErXbJYaF3uFpnjpLmsKeGrVblGfWeX63+dH72dw+Ow e7w8phfx8OzDwIdX0AWeZEFvaYqndg9Qd3dcY39l8xceBdJI67spNSFu1IRZrW6/Oh/9 gnug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=KJPypG4nUZebT4tKMcdJjuOyrLByu7LUhZZIqXihfsw=; b=MPcmNjmUvwuVZMLA8AFtCOFSdbVCfnaEL+N2dQvr0I4I3otXss15EspvOF3Fhy9egO 5efpEN6qPf24yo0a/Tn3zu6vatf/lNTbM8RBUgAqSM7Y03ZsUYIFexz7NsX3rJYL5KfT VHM7tN+ywdel9NpOCnhBk73LiB2wC5tjBYQIPACgONqPpHcCmH0T5wu72yoM6mydGG9h J3qsRaAy0ENaokmkOCujsyqw9KOcwnPB/D+Vy+4vz9DcrZMa061ZiTDaq0BBwpoaYQ0t 0S8YYOLGOF4C4CIOVg0WxURMnR5Mv79EC4/Ob18hPzcSpZLSFZFonXrq+me1wmrMyzFR 0Kdg== X-Gm-Message-State: AIVw112BxL9T1foS4pJIlJ9QLnqhRDCoI3kYh5t65CaCRhsz9d1/2tzz +U+7itk4rFVMCmn7dkU= X-Received: by 10.99.119.76 with SMTP id s73mr1233876pgc.374.1501827800317; Thu, 03 Aug 2017 23:23:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 23:23:11 -0700 Message-Id: <20170804062314.12594-4-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804062314.12594-1-rth@twiddle.net> References: <20170804062314.12594-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH for-2.11 3/6] disas/i386: Add disassembly of vex.0f38.f5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Which includes pext, pdep and bzhi. Signed-off-by: Richard Henderson --- disas/i386.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/disas/i386.c b/disas/i386.c index 7a238b203b..7eaa378a10 100644 --- a/disas/i386.c +++ b/disas/i386.c @@ -683,6 +683,7 @@ fetch_data(struct disassemble_info *info, bfd_byte *add= r) #define PREGRP105 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 105 } } #define PREGRP106 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 106 } } #define PREGRP107 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 107 } } +#define PREGRP108 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 108 } } =20 #define X86_64_0 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 0 } } #define X86_64_1 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 1 } } @@ -1484,7 +1485,7 @@ static const unsigned char threebyte_0x38_uses_REPNZ_= prefix[256] =3D { /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */ /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */ - /* f0 */ 1,1,0,0,0,0,0,1,0,0,0,0,0,0,0,0, /* ff */ + /* f0 */ 1,1,0,0,0,1,0,1,0,0,0,0,0,0,0,0, /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -1508,7 +1509,7 @@ static const unsigned char threebyte_0x38_uses_REPZ_p= refix[256] =3D { /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */ /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */ - /* f0 */ 0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0, /* ff */ + /* f0 */ 0,0,0,0,0,1,0,1,0,0,0,0,0,0,0,0, /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -2808,6 +2809,14 @@ static const struct dis386 prefix_user_table[][4] = =3D { { "bsfS", { Gv, Ev } }, { "(bad)", { XX } }, }, + + /* PREGRP108 */ + { + { "bzhi", { Gv, Ev, Bv } }, + { "pext", { Gv, Bv, Ev } }, + { "(bad)", { XX } }, + { "pdep", { Gv, Bv, Ev } }, + }, }; =20 static const struct dis386 x86_64_table[][2] =3D { @@ -3108,7 +3117,7 @@ static const struct dis386 three_byte_table[][256] = =3D { { PREGRP105 }, { "(bad)", { XX } }, { "(bad)", { XX } }, - { "(bad)", { XX } }, + { PREGRP108 }, { "(bad)", { XX } }, { PREGRP106 }, /* f8 */ --=20 2.13.3 From nobody Mon May 6 07:58:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501828370982309.2455075947455; Thu, 3 Aug 2017 23:32:50 -0700 (PDT) Received: from localhost ([::1]:38753 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddWAD-0003QL-IC for importer@patchew.org; Fri, 04 Aug 2017 02:32:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51556) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddW15-0003XB-Gm for qemu-devel@nongnu.org; Fri, 04 Aug 2017 02:23:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddW14-0005SN-KV for qemu-devel@nongnu.org; Fri, 04 Aug 2017 02:23:23 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:35999) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddW14-0005Rd-F5 for qemu-devel@nongnu.org; Fri, 04 Aug 2017 02:23:22 -0400 Received: by mail-pg0-x243.google.com with SMTP id y129so905929pgy.3 for ; Thu, 03 Aug 2017 23:23:22 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id q199sm1335819pfq.135.2017.08.03.23.23.20 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 23:23:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=krKCIW/aKy0qznI+lx5y0kTUm89otc0Hfj0/Yauj0MM=; b=AR1XTWySpDYli5+44Yn/YeS6QnRTxOF6fLH+GnGcHGrYtEHdvp3na8oaw6cvvVTAIx ppJKpFBXSDtLgfkW31X53ueQGfWWcas/WYfJDGzYaMeB2fWdbrbdVzYhdyGF4zuHGtJf xVgo3uHF3oqCdOW9G8xXxIpzIt+yX9crbdhgeft5lUarFKxka1yuNttAgCT5xfK4ZPf0 KPxyMTzfr1NjPtvv4pnvr8iE6NPZ8nT+bjkbmxDz9dKh9nP4CGqeXdtMxxwPt3E/Vxrw iM+Qdha5wBt1V9Q0wUPunC5lktTlFJBzz1ydZEcvFkeQuG2Jg9H/H9qY0p+rXAuuIeCO k3kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=krKCIW/aKy0qznI+lx5y0kTUm89otc0Hfj0/Yauj0MM=; b=iEOPTPwEbVZzwa00k+cQ7aaLNh7tiVnDaR7C8I7NK+57pD5sdWZ4wLFqLoxeYCGCD+ mIo57OchjzUGSCYDIn78MBmmGdD0mAk6Kb67Dm6/sdg88Nd92x2ln0LhBBldfSxXSik4 N2V3kl+1Dl1ZK9MAi5j8kHRL42UzxFCIkNWmvl+AWeSWwesLjCBY+/jK/tyMdhZQMm2f IoXnm3aK1MbWs9sy2Q6pSpmv4dk30QboCmxgN12/8NiYxGdvDhjJlZC3vDZztmcDBsdg aU7HS114ouaXqUDGQSVwLs7IbOCdNLKmg6XmDX+cQ2q+0TYj/VvEWYbZURjhO672JZP1 XFvQ== X-Gm-Message-State: AHYfb5jL/g/eDW33g78/LDHZCGc4qSAmqlaPaxI4xIvJNSq+D/gYFd8/ 5NSKgK6TI0BQ7Fsbzys= X-Received: by 10.98.70.200 with SMTP id o69mr1293545pfi.325.1501827801445; Thu, 03 Aug 2017 23:23:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 23:23:12 -0700 Message-Id: <20170804062314.12594-5-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804062314.12594-1-rth@twiddle.net> References: <20170804062314.12594-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH for-2.11 4/6] disas/i386: Add disassembly of rorx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- disas/i386.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/disas/i386.c b/disas/i386.c index 7eaa378a10..a557e678ec 100644 --- a/disas/i386.c +++ b/disas/i386.c @@ -684,6 +684,7 @@ fetch_data(struct disassemble_info *info, bfd_byte *add= r) #define PREGRP106 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 106 } } #define PREGRP107 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 107 } } #define PREGRP108 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 108 } } +#define PREGRP109 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 109 } } =20 #define X86_64_0 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 0 } } #define X86_64_1 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 1 } } @@ -1557,7 +1558,7 @@ static const unsigned char threebyte_0x3a_uses_REPNZ_= prefix[256] =3D { /* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */ /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */ - /* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */ + /* f0 */ 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -2817,6 +2818,14 @@ static const struct dis386 prefix_user_table[][4] = =3D { { "(bad)", { XX } }, { "pdep", { Gv, Bv, Ev } }, }, + + /* PREGRP109 */ + { + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "(bad)", { XX } }, + { "rorx", { Gv, Ev, Ib } }, + }, }; =20 static const struct dis386 x86_64_table[][2] =3D { @@ -3403,7 +3412,7 @@ static const struct dis386 three_byte_table[][256] = =3D { { "(bad)", { XX } }, { "(bad)", { XX } }, /* f0 */ - { "(bad)", { XX } }, + { PREGRP109 }, { "(bad)", { XX } }, { "(bad)", { XX } }, { "(bad)", { XX } }, --=20 2.13.3 From nobody Mon May 6 07:58:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501827934218504.742900267987; Thu, 3 Aug 2017 23:25:34 -0700 (PDT) Received: from localhost ([::1]:38463 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddW3A-0005OM-Qc for importer@patchew.org; Fri, 04 Aug 2017 02:25:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51595) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddW17-0003Yl-LG for qemu-devel@nongnu.org; Fri, 04 Aug 2017 02:23:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddW15-0005Tk-RS for qemu-devel@nongnu.org; Fri, 04 Aug 2017 02:23:25 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:33118) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddW15-0005St-Jl for qemu-devel@nongnu.org; Fri, 04 Aug 2017 02:23:23 -0400 Received: by mail-pf0-x244.google.com with SMTP id c65so958053pfl.0 for ; Thu, 03 Aug 2017 23:23:23 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id q199sm1335819pfq.135.2017.08.03.23.23.21 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 23:23:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=m+XNZcfPh2ezzBjtpZc8TIZpPNtdBU/s2DK/CpgGjW0=; b=oyWG3NGqIuO/WrOaPDMosu9OAi6t4DRwTFc8Jj4QWVdxKl95YXmpsRvNiKhuV0hVSK ni6E+RwcPywZ76d+8bn3pDnX6ii+JDD+CujGHIdjqcV5FQYqdFlp3oCjySd6037OAQCA MTr4i4WXutuBTDgPLLIOkLLt81c0jMofSPWzZHLpWQCAAW5C4qxfNoKFNl/U4k5DykFE K9Uxfl7lX3XjEgt7IaqqUt9BQ4H7wY3sgTh6v8nFE2jFvQrkBBkRDB/o+tswsi+PAn0t yGYRw1r2oJy4Aq1dnTR/As7WHiKODK2DA7UOygw80uiP1czdnKsiNJB9R989SRtz0p4N 8aYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=m+XNZcfPh2ezzBjtpZc8TIZpPNtdBU/s2DK/CpgGjW0=; b=Ulf/nUC8Nzc4v70L+8v9s0m3zHXvnkZ7ISlSNTyI/cwjBfthpLKc8kDgnuE84pJxr6 oNgUDDAcqOTZDNkm6yqJaB90ggeo8+F31kOyr3Dy4XShh9anvWc4T+ose8YtpZzHMnKC CzdoKjm4md3qJkrmzTRshoRlWZ0t6J6empgiZr9ano+i8pOaUM9whprvtveApARrEqRX 9M5ht631s4tcnR6FvPF6OVabFt3evDq0LZcxWKJQFikDcNJk+yi6rolQLE1XBXfPQm7o PosoGHvsod744Js5Y9UXrtSpsqvESf2tckGKkizIjzIEdYVQOfbYElKe8H5e2t2DNWrB /b0Q== X-Gm-Message-State: AIVw110p+wI0RqIRk7z+JRBNkBiCdHgdnS8jDSUhejsOP/fZ3P9VyUcF ihI3Zqw7kBQS0A7CNEU= X-Received: by 10.99.104.129 with SMTP id d123mr1217846pgc.236.1501827802348; Thu, 03 Aug 2017 23:23:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 23:23:13 -0700 Message-Id: <20170804062314.12594-6-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804062314.12594-1-rth@twiddle.net> References: <20170804062314.12594-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH for-2.11 5/6] tcg/i386: Use pext for extract X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 6 +- tcg/i386/tcg-target.inc.c | 147 +++++++++++++++++++++++++++++++++---------= ---- 2 files changed, 109 insertions(+), 44 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b89dababf4..85b0ccd98c 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -76,6 +76,7 @@ typedef enum { #endif =20 extern bool have_bmi1; +extern bool have_bmi2; extern bool have_popcnt; =20 /* optional instructions */ @@ -153,9 +154,10 @@ extern bool have_popcnt; =20 /* Check for the possibility of high-byte extraction and, for 64-bit, zero-extending 32-bit right-shift. */ -#define TCG_TARGET_extract_i32_valid(ofs, len) ((ofs) =3D=3D 8 && (len) = =3D=3D 8) +#define TCG_TARGET_extract_i32_valid(ofs, len) \ + (have_bmi2 || ((ofs) =3D=3D 8 && (len) =3D=3D 8)) #define TCG_TARGET_extract_i64_valid(ofs, len) \ - (((ofs) =3D=3D 8 && (len) =3D=3D 8) || ((ofs) + (len)) =3D=3D 32) + (have_bmi2 || ((ofs) =3D=3D 8 && (len) =3D=3D 8) || ((ofs) + (len)) = =3D=3D 32) =20 #if TCG_TARGET_REG_BITS =3D=3D 64 # define TCG_AREG0 TCG_REG_R14 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 5231056fd3..69587c82de 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -124,11 +124,11 @@ static bool have_cmov; /* We need these symbols in tcg-target.h, and we can't properly conditiona= lize it there. Therefore we always define the variable. */ bool have_bmi1; +bool have_bmi2; bool have_popcnt; =20 #ifdef CONFIG_CPUID_H static bool have_movbe; -static bool have_bmi2; static bool have_lzcnt; #else # define have_movbe 0 @@ -275,13 +275,14 @@ static inline int tcg_target_const_match(tcg_target_l= ong val, TCGType type, =20 #define P_EXT 0x100 /* 0x0f opcode prefix */ #define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */ -#define P_DATA16 0x400 /* 0x66 opcode prefix */ +#define P_EXT3A 0x400 /* 0x0f 0x3a opcode prefix */ +#define P_DATA16 0x800 /* 0x66 opcode prefix */ #if TCG_TARGET_REG_BITS =3D=3D 64 -# define P_ADDR32 0x800 /* 0x67 opcode prefix */ -# define P_REXW 0x1000 /* Set REX.W =3D 1 */ -# define P_REXB_R 0x2000 /* REG field as byte register */ -# define P_REXB_RM 0x4000 /* R/M field as byte register */ -# define P_GS 0x8000 /* gs segment override */ +# define P_ADDR32 0x1000 /* 0x67 opcode prefix */ +# define P_REXW 0x2000 /* Set REX.W =3D 1 */ +# define P_REXB_R 0x4000 /* REG field as byte register */ +# define P_REXB_RM 0x8000 /* R/M field as byte register */ +# define P_GS 0x10000 /* gs segment override */ #else # define P_ADDR32 0 # define P_REXW 0 @@ -289,14 +290,15 @@ static inline int tcg_target_const_match(tcg_target_l= ong val, TCGType type, # define P_REXB_RM 0 # define P_GS 0 #endif -#define P_SIMDF3 0x10000 /* 0xf3 opcode prefix */ -#define P_SIMDF2 0x20000 /* 0xf2 opcode prefix */ +#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */ +#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */ =20 #define OPC_ARITH_EvIz (0x81) #define OPC_ARITH_EvIb (0x83) #define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */ #define OPC_ANDN (0xf2 | P_EXT38) #define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3)) +#define OPC_BEXTR (0xf7 | P_EXT38) #define OPC_BSF (0xbc | P_EXT) #define OPC_BSR (0xbd | P_EXT) #define OPC_BSWAP (0xc8 | P_EXT) @@ -327,12 +329,14 @@ static inline int tcg_target_const_match(tcg_target_l= ong val, TCGType type, #define OPC_MOVSLQ (0x63 | P_REXW) #define OPC_MOVZBL (0xb6 | P_EXT) #define OPC_MOVZWL (0xb7 | P_EXT) +#define OPC_PEXT (0xf5 | P_EXT38 | P_SIMDF3) #define OPC_POP_r32 (0x58) #define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) #define OPC_PUSH_r32 (0x50) #define OPC_PUSH_Iv (0x68) #define OPC_PUSH_Ib (0x6a) #define OPC_RET (0xc3) +#define OPC_RORX (0xf0 | P_EXT3A | P_SIMDF2) #define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */ #define OPC_SHIFT_1 (0xd1) #define OPC_SHIFT_Ib (0xc1) @@ -455,6 +459,8 @@ static void tcg_out_opc(TCGContext *s, int opc, int r, = int rm, int x) tcg_out8(s, 0x0f); if (opc & P_EXT38) { tcg_out8(s, 0x38); + } else if (opc & P_EXT3A) { + tcg_out8(s, 0x3a); } } =20 @@ -475,6 +481,8 @@ static void tcg_out_opc(TCGContext *s, int opc) tcg_out8(s, 0x0f); if (opc & P_EXT38) { tcg_out8(s, 0x38); + } else if (opc & P_EXT3A) { + tcg_out8(s, 0x3a); } } tcg_out8(s, opc); @@ -491,34 +499,29 @@ static void tcg_out_modrm(TCGContext *s, int opc, int= r, int rm) tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } =20 -static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) +static void tcg_out_vex_pfx_opc(TCGContext *s, int opc, int r, int v, int = rm) { int tmp; =20 - if ((opc & (P_REXW | P_EXT | P_EXT38)) || (rm & 8)) { - /* Three byte VEX prefix. */ - tcg_out8(s, 0xc4); - - /* VEX.m-mmmm */ - if (opc & P_EXT38) { - tmp =3D 2; - } else if (opc & P_EXT) { - tmp =3D 1; - } else { - tcg_abort(); - } - tmp |=3D 0x40; /* VEX.X */ - tmp |=3D (r & 8 ? 0 : 0x80); /* VEX.R */ - tmp |=3D (rm & 8 ? 0 : 0x20); /* VEX.B */ - tcg_out8(s, tmp); + /* Three byte VEX prefix. */ + tcg_out8(s, 0xc4); =20 - tmp =3D (opc & P_REXW ? 0x80 : 0); /* VEX.W */ + /* VEX.m-mmmm */ + if (opc & P_EXT3A) { + tmp =3D 3; + } else if (opc & P_EXT38) { + tmp =3D 2; + } else if (opc & P_EXT) { + tmp =3D 1; } else { - /* Two byte VEX prefix. */ - tcg_out8(s, 0xc5); - - tmp =3D (r & 8 ? 0 : 0x80); /* VEX.R */ + tcg_abort(); } + tmp |=3D 0x40; /* VEX.X */ + tmp |=3D (r & 8 ? 0 : 0x80); /* VEX.R */ + tmp |=3D (rm & 8 ? 0 : 0x20); /* VEX.B */ + tcg_out8(s, tmp); + + tmp =3D (opc & P_REXW ? 0x80 : 0); /* VEX.W */ /* VEX.pp */ if (opc & P_DATA16) { tmp |=3D 1; /* 0x66 */ @@ -530,9 +533,43 @@ static void tcg_out_vex_modrm(TCGContext *s, int opc, = int r, int v, int rm) tmp |=3D (~v & 15) << 3; /* VEX.vvvv */ tcg_out8(s, tmp); tcg_out8(s, opc); +} + +static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm) +{ + tcg_out_vex_pfx_opc(s, opc, r, v, rm); tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); } =20 +static void tcg_out_sfx_pool_imm(TCGContext *s, int r, tcg_target_ulong da= ta) +{ + /* modrm for 64-bit rip-relative, or 32-bit absolute addressing. */ + tcg_out8(s, (LOWREGMASK(r) << 3) | 5); + + if (TCG_TARGET_REG_BITS =3D=3D 64) { + new_pool_label(s, data, R_386_PC32, s->code_ptr, -4); + } else { + new_pool_label(s, data, R_386_32, s->code_ptr, 0); + } + tcg_out32(s, 0); +} + +#if 0 +static void tcg_out_opc_pool_imm(TCGContext *s, int opc, int r, + tcg_target_ulong data) +{ + tcg_out_opc(s, opc, r, 0, 0); + tcg_out_sfx_pool_imm(s, r, data); +} +#endif + +static void tcg_out_vex_pool_imm(TCGContext *s, int opc, int r, int v, + tcg_target_ulong data) +{ + tcg_out_vex_pfx_opc(s, opc, r, v, 0); + tcg_out_sfx_pool_imm(s, r, data); +} + /* Output an opcode with a full "rm + (index< 32) * P_REXW, + a0, a1, deposit64(0, a2, a3, -1)); } break; =20 @@ -2257,12 +2307,25 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, /* We don't implement sextract_i64, as we cannot sign-extend to 64-bits without using the REX prefix that explicitly excludes access to the high-byte registers. */ - tcg_debug_assert(a2 =3D=3D 8 && args[3] =3D=3D 8); - if (a1 < 4 && a0 < 8) { - tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4); + a3 =3D args[3]; + if (a2 =3D=3D 8 && a3 =3D=3D 8) { + if (a1 < 4 && a0 < 8) { + tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4); + } else { + tcg_out_ext16s(s, a0, a1, 0); + tcg_out_shifti(s, SHIFT_SAR, a0, 8); + } } else { - tcg_out_ext16s(s, a0, a1, 0); - tcg_out_shifti(s, SHIFT_SAR, a0, 8); + /* ??? We only have one extract_i32_valid macro. But as it + happens we can perform a useful 3-operand shift. */ + tcg_debug_assert(have_bmi2); + if (a2 + a3 < 32) { + /* Rotate the field in A1 to the MSB of A0. */ + tcg_out_rorx(s, 0, a0, a1, a2 + a3); + } else { + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + } + tcg_out_shifti(s, SHIFT_SAR, a0, 32 - a3); } break; =20 --=20 2.13.3 From nobody Mon May 6 07:58:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501827932326255.1223577218774; Thu, 3 Aug 2017 23:25:32 -0700 (PDT) Received: from localhost ([::1]:38462 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddW38-0005N5-Ry for importer@patchew.org; Fri, 04 Aug 2017 02:25:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51609) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddW18-0003Zf-DR for qemu-devel@nongnu.org; Fri, 04 Aug 2017 02:23:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddW17-0005VH-9P for qemu-devel@nongnu.org; Fri, 04 Aug 2017 02:23:26 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:33528) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddW17-0005Ub-1t for qemu-devel@nongnu.org; Fri, 04 Aug 2017 02:23:25 -0400 Received: by mail-pg0-x244.google.com with SMTP id u185so936780pgb.0 for ; Thu, 03 Aug 2017 23:23:24 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id q199sm1335819pfq.135.2017.08.03.23.23.22 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 23:23:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=h7V8nRljnln2mzYsOMBJaZTFKJXHGLQipaVpf2qy0jI=; b=qoS/t7ICx39mALzzx1I9Vj+Mpv3bBAl596KAvOLjqfBEqpmAsXWRy4fR22M/ns4eHP QJmOd6tL5ZLT7uKgtP8qZLH/TSOvjqMaAIaXiKR4/j0I0k06UcQyTAes04iT2LD2elvV 7SJNvX2WxNuQwFvAtp0061E2IOcrQEllNWku40KCatgdF0wkypP4C4qKMhFKX3p8XKZK FTBXVZFl9SFepqFTLA60nXL5rIHg+dkXxRZQQdNxskdII7SvNBEsC3/zjZ9zeQkivUOr PcMhDUlyZqypV7bJnkUrDR5LjDp4iSMWYcMVBYjtGY2RzyT9XI6jEK4ZYMLgg7Qk6KVr LHPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=h7V8nRljnln2mzYsOMBJaZTFKJXHGLQipaVpf2qy0jI=; b=piO0+dfjuhl3huB8eyAEow/ju6ARepfY9MGCZWTwqL2jzK68cZ5MgZPkUqWo5q6pOo ar9wwT7xjvuD7xaj1P4D1qJ6IP9OSZwyJthzyE/jZd4dDfPPLDN8wCOYpY/HzbAN3BrI MSJnIpQbuOuIaF3CTU6FpQNIZNTx9O1sObelj747h9OQXdaxDkWAE0V6JMrWEUlDDyay 7jee8Xqh1m7lXmHsUCmNgNkIKZLJaza9Bd+/lMv2wdGel1P/tWf0AgOWd/t3Szjf9lxR yUR/zlmRa8fc8pZ6vZUcIoYX95Et+tJ9Pb+qCVzKJoEIGvofVRVizlWr5RFV48OzWzru nqyA== X-Gm-Message-State: AIVw1122YSZbGuLfJ0kO6jD5Bs7klXxGF9cz1BW6+1qPHiDTpMX2Dz6x epLkJqfC6Eyx841wQ5Q= X-Received: by 10.99.95.76 with SMTP id t73mr1251773pgb.349.1501827803828; Thu, 03 Aug 2017 23:23:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 23:23:14 -0700 Message-Id: <20170804062314.12594-7-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804062314.12594-1-rth@twiddle.net> References: <20170804062314.12594-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH for-2.11 6/6] tcg/i386: Use pdep for deposit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 4 ++- tcg/i386/tcg-target.inc.c | 82 ++++++++++++++++++++++++++++++++++++++-----= ---- 2 files changed, 70 insertions(+), 16 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 85b0ccd98c..e512648c95 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -148,7 +148,9 @@ extern bool have_popcnt; #endif =20 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ - (((ofs) =3D=3D 0 && (len) =3D=3D 8) || ((ofs) =3D=3D 8 && (len) =3D=3D= 8) || \ + (have_bmi2 || \ + ((ofs) =3D=3D 0 && (len) =3D=3D 8) || \ + ((ofs) =3D=3D 8 && (len) =3D=3D 8) || \ ((ofs) =3D=3D 0 && (len) =3D=3D 16)) #define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid =20 diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 69587c82de..aeefb72aa0 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -329,6 +329,7 @@ static inline int tcg_target_const_match(tcg_target_lon= g val, TCGType type, #define OPC_MOVSLQ (0x63 | P_REXW) #define OPC_MOVZBL (0xb6 | P_EXT) #define OPC_MOVZWL (0xb7 | P_EXT) +#define OPC_PDEP (0xf5 | P_EXT38 | P_SIMDF2) #define OPC_PEXT (0xf5 | P_EXT38 | P_SIMDF3) #define OPC_POP_r32 (0x58) #define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3) @@ -554,14 +555,12 @@ static void tcg_out_sfx_pool_imm(TCGContext *s, int r= , tcg_target_ulong data) tcg_out32(s, 0); } =20 -#if 0 static void tcg_out_opc_pool_imm(TCGContext *s, int opc, int r, tcg_target_ulong data) { tcg_out_opc(s, opc, r, 0, 0); tcg_out_sfx_pool_imm(s, r, data); } -#endif =20 static void tcg_out_vex_pool_imm(TCGContext *s, int opc, int r, int v, tcg_target_ulong data) @@ -1902,7 +1901,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - TCGArg a0, a1, a2, a3; + TCGArg a0, a1, a2, a3, a4; int c, const_a2, vexop, rexw =3D 0; =20 #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -2262,17 +2261,68 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, #endif =20 OP_32_64(deposit): - if (args[3] =3D=3D 0 && args[4] =3D=3D 8) { - /* load bits 0..7 */ - tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2, a0); - } else if (args[3] =3D=3D 8 && args[4] =3D=3D 8) { - /* load bits 8..15 */ - tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); - } else if (args[3] =3D=3D 0 && args[4] =3D=3D 16) { - /* load bits 0..15 */ - tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); - } else { - tcg_abort(); + a3 =3D args[3]; + a4 =3D args[4]; + { + tcg_target_ulong mask =3D deposit64(0, a3, a4, -1); + + if (const_args[1]) { + tcg_debug_assert(have_bmi2); + if (a3 =3D=3D 0 && a0 =3D=3D a2) { + if (a4 <=3D 32) { + tgen_arithi(s, ARITH_AND, a0, mask, 0); + } else { + tcg_out_opc_pool_imm(s, OPC_ARITH_GvEv + P_REXW + + ARITH_AND * 8, a0, mask); + } + } else { + tcg_out_vex_pool_imm(s, OPC_PDEP + + (a3 + a4 > 32) * P_REXW, + a0, a2, mask); + } + a1 &=3D ~mask; + if (a1 !=3D 0) { + if (!rexw || a1 =3D=3D (int)a1) { + tgen_arithi(s, ARITH_OR + rexw, a0, a1, 0); + } else { + tcg_out_opc_pool_imm(s, OPC_ARITH_GvEv + P_REXW + + ARITH_OR * 8, a0, a1); + } + } + } else if (a0 =3D=3D a1 && a3 =3D=3D 0 && a4 =3D=3D 8) { + /* load bits 0..7 */ + tcg_out_modrm(s, OPC_MOVB_EvGv | P_REXB_R | P_REXB_RM, a2,= a0); + } else if (a0 =3D=3D a1 && a3 =3D=3D 8 && a4 =3D=3D 8 && a0 < = 4 && a2 < 8) { + /* load bits 8..15 */ + tcg_out_modrm(s, OPC_MOVB_EvGv, a2, a0 + 4); + } else if (a0 =3D=3D a1 && a3 =3D=3D 0 && a4 =3D=3D 16) { + /* load bits 0..15 */ + tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); + } else { + TCGType type =3D rexw ? TCG_TYPE_I64 : TCG_TYPE_I32; + TCGReg t1 =3D tcg_reg_alloc_new(s, type); + TCGReg t2 =3D t1; + + tcg_debug_assert(have_bmi2); + tcg_out_movi(s, type, t1, mask); + if (a0 =3D=3D a2) { + t2 =3D tcg_reg_alloc_new(s, type); + tcg_out_vex_modrm(s, OPC_ANDN + rexw, t2, t1, a1); + if (a3 =3D=3D 0) { + tgen_arithr(s, ARITH_AND + rexw, a0, t1); + } else { + tcg_out_vex_modrm(s, OPC_PDEP + rexw, a0, a2, t1); + } + } else { + tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, t1, a1); + if (a3 =3D=3D 0) { + tgen_arithr(s, ARITH_AND + rexw, t1, a2); + } else { + tcg_out_vex_modrm(s, OPC_PDEP + rexw, t1, a2, t1); + } + } + tgen_arithr(s, ARITH_OR + rexw, a0, t2); + } } break; =20 @@ -2480,7 +2530,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) { static const TCGTargetOpDef dep =3D { .args_ct_str =3D { "Q", "0", "Q" } }; - return &dep; + static const TCGTargetOpDef pdep + =3D { .args_ct_str =3D { "r", "ri", "r" } }; + return have_bmi2 ? &pdep : &dep; } case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: --=20 2.13.3