From nobody Mon Feb 9 09:29:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501826050982424.33574402734735; Thu, 3 Aug 2017 22:54:10 -0700 (PDT) Received: from localhost ([::1]:36693 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVYn-0003f4-Kj for importer@patchew.org; Fri, 04 Aug 2017 01:54:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPY-0003q6-4W for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPW-00038a-0m for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:36 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:38628) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPV-00036b-OH for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:33 -0400 Received: by mail-pf0-x241.google.com with SMTP id h75so859450pfh.5 for ; Thu, 03 Aug 2017 22:44:33 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.31 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=5WuRhmNYy0zkJlZ8O+Y7ikF0OgtGL6YUuDmrlkKRppc=; b=sDJzy7TwfpvFs5tM0dsf+patE2nkAHyPh0Sw2rRbZrPBxbXDsPXeIll5wVWj7Ft4+h Z15PVaXzOnwU4MPS3bVgop1tLTD2cF8/PZ87+Nsi31aSzwoavYcgqpOpIc6NmwQGonf0 BsqPqY3lLjmSrHPrmB3ryTwGIszQBmd4aw/iLAEdbqCW1SIC6CIv3ARqTD4Nksha5RNd 1e8QFr1rHLtYZUzgFG80GPs9E32yT1a3K4EztKUtCBvl+26xlcPIrk0kVln0Ua6bRu3d B0OtZBpMX8Q3Ho9M5IBrjbPsqyD2ExT3tAbFjyvmEBMUah9+L9wEAok9aHDwmYIIyEJU 2Slw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=5WuRhmNYy0zkJlZ8O+Y7ikF0OgtGL6YUuDmrlkKRppc=; b=g2IxWHX+8Kl0z/QMISLGZsmabMYTjXDWQ98c8JwRWPTknY6KYeJ3ZT9N3PNk8M3XUB UH40HUCY7GLCiNcQe5qmzwlvCF996z7EPadYsYiqhCkHWeKLo0yGao2Tv9SCn/O36K74 41gL6xyYH7LaoRb4UiQh+b38xuy9kth9Ova0z/ulBT53h4denNUme6U9GiEj1z0kaa8N 94Y6Bx0XyO+WeOF2HBR3WrHS5LvoDNtwn6cU1/68Qh0Zec/w1iWwaWDX5uhSB7Nxz3Q7 UyFbdsDAQtINBW7kT/sVrnNn9XM2fQgxdjXyhTCYVcOYPwsW7MdExCMdFYVroWFTT1yL DrLQ== X-Gm-Message-State: AIVw112MQmbot2Ef3mr+lKhxicDbIsU0dkoWRPc+W37QmP5YOT45LNmk VX4v78XlNQg4x+ukt5E= X-Received: by 10.84.132.73 with SMTP id 67mr1373826ple.53.1501825472461; Thu, 03 Aug 2017 22:44:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:08 -0700 Message-Id: <20170804054426.10590-6-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH for-2.11 05/23] tcg/s390: Introduce TCG_REG_TB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 2 +- tcg/s390/tcg-target.inc.c | 71 +++++++++++++++++++++++++++++++++++++++----= ---- 2 files changed, 61 insertions(+), 12 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 8fea9646b4..8c5a30ccf8 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -95,7 +95,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 -#define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_direct_jump (s390_facilities & FACILITY_GEN_INST= _EXT) =20 #define TCG_TARGET_HAS_div2_i64 1 #define TCG_TARGET_HAS_rot_i64 1 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index ee0dff995a..e007586315 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -51,6 +51,12 @@ /* A scratch register that may be be used throughout the backend. */ #define TCG_TMP0 TCG_REG_R1 =20 +/* A scratch register that holds a pointer to the beginning of the TB. + We don't need this when we have pc-relative loads with the general + instructions extension facility. */ +#define TCG_REG_TB TCG_REG_R12 +#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT)) + #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_R13 #endif @@ -556,8 +562,8 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg dst, TCGReg src) } =20 /* load a register with an immediate value */ -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long sval) +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long sval, bool in_prologue) { static const S390Opcode lli_insns[4] =3D { RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH @@ -601,13 +607,22 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 - /* Try for PC-relative address load. */ + /* Try for PC-relative address load. For odd addresses, + attempt to use an offset from the start of the TB. */ if ((sval & 1) =3D=3D 0) { ptrdiff_t off =3D tcg_pcrel_diff(s, (void *)sval) >> 1; if (off =3D=3D (int32_t)off) { tcg_out_insn(s, RIL, LARL, ret, off); return; } + } else if (USE_REG_TB && !in_prologue) { + ptrdiff_t off =3D sval - (uintptr_t)s->code_gen_ptr; + if (off =3D=3D sextract64(off, 0, 20)) { + /* This is certain to be an address within TB, and therefore + OFF will be negative; don't try RX_LA. */ + tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off); + return; + } } =20 /* If extended immediates are not present, then we may have to issue @@ -663,6 +678,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long sval) +{ + tcg_out_movi_int(s, type, ret, sval, false); +} =20 /* Emit a load/store type instruction. Inputs are: DATA: The register to be loaded or stored. @@ -739,6 +759,13 @@ static void tcg_out_ld_abs(TCGContext *s, TCGType type= , TCGReg dest, void *abs) return; } } + if (USE_REG_TB) { + ptrdiff_t disp =3D abs - (void *)s->code_gen_ptr; + if (disp =3D=3D sextract64(disp, 0, 20)) { + tcg_out_ld(s, type, dest, TCG_REG_TB, disp); + return; + } + } =20 tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff); tcg_out_ld(s, type, dest, dest, addr & 0xffff); @@ -1690,6 +1717,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, break; =20 case INDEX_op_goto_tb: + a0 =3D args[0]; if (s->tb_jmp_insn_offset) { /* branch displacement must be aligned for atomic patching; * see if we need to add extra nop before branch @@ -1697,21 +1725,34 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { tcg_out16(s, NOP); } + tcg_debug_assert(!USE_REG_TB); tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); - s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s); + s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); s->code_ptr +=3D 2; } else { - /* load address stored at s->tb_jmp_target_addr + args[0] */ - tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_TMP0, - s->tb_jmp_target_addr + args[0]); + /* load address stored at s->tb_jmp_target_addr + a0 */ + tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, + s->tb_jmp_target_addr + a0); /* and go there */ - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_TMP0); + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); + } + s->tb_jmp_reset_offset[a0] =3D tcg_current_code_size(s); + + /* For the unlinked path of goto_tb, we need to reset + TCG_REG_TB to the beginning of this TB. */ + if (USE_REG_TB) { + int ofs =3D -tcg_current_code_size(s); + assert(ofs =3D=3D (int16_t)ofs); + tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs); } - s->tb_jmp_reset_offset[args[0]] =3D tcg_current_code_size(s); break; =20 case INDEX_op_goto_ptr: - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, args[0]); + a0 =3D args[0]; + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); + } + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); break; =20 OP_32_64(ld8u): @@ -2476,6 +2517,9 @@ static void tcg_target_init(TCGContext *s) /* XXX many insns can't be used with R0, so we better avoid it for now= */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); + if (USE_REG_TB) { + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); + } } =20 #define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ @@ -2496,12 +2540,17 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 #ifndef CONFIG_SOFTMMU if (guest_base >=3D 0x80000) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, = true); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, + tcg_target_call_iarg_regs[1]); + } + /* br %r3 (go to TB) */ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); =20 --=20 2.13.3