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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.27 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=GqD34/PvUspan+LfGNy5q6hcBVDyClZ+4jD237ehhDY=; b=f/kQ483KCJ/e8POJRRh7hkvV2nK5XfRXFIqhdTYdyWIzKFTp3g6P/WiwiMkgjujqO6 OtrllQ1vxZFDzn268uj+/k8+x4DEpPkJBVP5fK6WHLyaD8yIUZQjSIetZu2/1Oa+PB60 DXYwma6w420ufcw0q8KMg9LMPcDaJRknfRd04i5DMUu1fx/+2gewih56/XcUhB8iNyi2 ZB0KLCfbo226pE/NbxCSTGqUTeP5txNAvOPwYlS3NFvjB9Vql27DtxkU7jAobphslD4h ZcuEkVTar8TzwDL7GtceDBxIPBufz7lF0BCaLBnzAcCwT6hg2lUMlfRTdLaYKEXc8S0R 4ZBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=GqD34/PvUspan+LfGNy5q6hcBVDyClZ+4jD237ehhDY=; b=nYrlStDQi4j+rg+nuvDbWj5bA5PO0lDGHbxA/8H01tDvFtxErQKs47R55nMTpdzZJf CO28cr28vOjPT32+0qUqwPFYA3A2QJ+1pyE8YL9QVLHAq0LRJ8GzXhhKenLW+tQ27D0B oQAmUB5duph+KBl/O8+T6cQ442VnaoFMAOl1lWJRCFqesne7dQnBVCWpVYB3GqDZBYZ0 XgO7XkiW4ySJGZsHLlnCO4aKWISo5b2z0yItkvSb/1UaLgqNIDXOb3pAOHNn6lT7Xr5J iVSqV4l275xpAEIcqWQIVtwfFaRymY22gBL54TFmxyTyviGO17MDQYKAjmJdYpOvyeRQ 58Zw== X-Gm-Message-State: AIVw113lUpXdu0VqEo5oGL6SfD6n7iTXO9NigeI73AVGgsK/rDvM1Xh2 6yxnD2BUZpk2EGAOMzk= X-Received: by 10.98.223.18 with SMTP id u18mr1224861pfg.166.1501825468445; Thu, 03 Aug 2017 22:44:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:04 -0700 Message-Id: <20170804054426.10590-2-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH for-2.11 01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Replace the USE_DIRECT_JUMP ifdef with a TCG_TARGET_HAS_direct_jump boolean test. Replace the tb_set_jmp_target1 ifdef with an unconditional function tb_target_set_jmp_target. While we're touching all backends, add a parameter for tb->tc_ptr; we're going to need it shortly for some backends. Move tb_set_jmp_target and tb_add_jump from exec-all.h to cpu-exec.c. This opens the possibility for TCG_TARGET_HAS_direct_jump to be a runtime decision -- based on host cpu capabilities, the size of code_gen_buffer, or a future debugging switch. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 95 ++--------------------------------------= ---- tcg/aarch64/tcg-target.h | 3 ++ tcg/arm/tcg-target.h | 4 ++ tcg/i386/tcg-target.h | 9 +++++ tcg/ia64/tcg-target.h | 4 ++ tcg/mips/tcg-target.h | 3 ++ tcg/ppc/tcg-target.h | 2 + tcg/s390/tcg-target.h | 10 +++++ tcg/sparc/tcg-target.h | 3 ++ tcg/tcg.h | 4 +- tcg/tci/tcg-target.h | 9 +++++ accel/tcg/cpu-exec.c | 35 ++++++++++++++++ accel/tcg/translate-all.c | 14 +++---- tcg/aarch64/tcg-target.inc.c | 13 +++--- tcg/mips/tcg-target.inc.c | 3 +- tcg/ppc/tcg-target.inc.c | 6 ++- tcg/sparc/tcg-target.inc.c | 3 +- 17 files changed, 107 insertions(+), 113 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 440fc31b37..aff4d33e3c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -330,15 +330,6 @@ static inline void tb_invalidate_phys_addr(AddressSpac= e *as, hwaddr addr) #define CODE_GEN_AVG_BLOCK_SIZE 150 #endif =20 -#if defined(_ARCH_PPC) \ - || defined(__x86_64__) || defined(__i386__) \ - || defined(__sparc__) || defined(__aarch64__) \ - || defined(__s390x__) || defined(__mips__) \ - || defined(CONFIG_TCG_INTERPRETER) -/* NOTE: Direct jump patching must be atomic to be thread-safe. */ -#define USE_DIRECT_JUMP -#endif - struct TranslationBlock { target_ulong pc; /* simulated PC corresponding to this block (EIP + = CS base) */ target_ulong cs_base; /* CS base for this block */ @@ -376,11 +367,8 @@ struct TranslationBlock { */ uint16_t jmp_reset_offset[2]; /* offset of original jump target */ #define TB_JMP_RESET_OFFSET_INVALID 0xffff /* indicates no jump generated = */ -#ifdef USE_DIRECT_JUMP - uint16_t jmp_insn_offset[2]; /* offset of native jump instruction */ -#else - uintptr_t jmp_target_addr[2]; /* target address for indirect jump */ -#endif + uintptr_t jmp_target_arg[2]; /* target address or offset */ + /* Each TB has an assosiated circular list of TBs jumping to this one. * jmp_list_first points to the first TB jumping to this one. * jmp_list_next is used to point to the next TB in a list. @@ -402,84 +390,7 @@ void tb_flush(CPUState *cpu); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, target_ulong cs_base, uint32_t flags); - -#if defined(USE_DIRECT_JUMP) - -#if defined(CONFIG_TCG_INTERPRETER) -static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) -{ - /* patch the branch destination */ - atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); - /* no need to flush icache explicitly */ -} -#elif defined(_ARCH_PPC) -void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); -#define tb_set_jmp_target1 ppc_tb_set_jmp_target -#elif defined(__i386__) || defined(__x86_64__) -static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) -{ - /* patch the branch destination */ - atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); - /* no need to flush icache explicitly */ -} -#elif defined(__s390x__) -static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) -{ - /* patch the branch destination */ - intptr_t disp =3D addr - (jmp_addr - 2); - atomic_set((int32_t *)jmp_addr, disp / 2); - /* no need to flush icache explicitly */ -} -#elif defined(__aarch64__) -void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); -#define tb_set_jmp_target1 aarch64_tb_set_jmp_target -#elif defined(__sparc__) || defined(__mips__) -void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr); -#else -#error tb_set_jmp_target1 is missing -#endif - -static inline void tb_set_jmp_target(TranslationBlock *tb, - int n, uintptr_t addr) -{ - uint16_t offset =3D tb->jmp_insn_offset[n]; - tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); -} - -#else - -/* set the jump target */ -static inline void tb_set_jmp_target(TranslationBlock *tb, - int n, uintptr_t addr) -{ - tb->jmp_target_addr[n] =3D addr; -} - -#endif - -/* Called with tb_lock held. */ -static inline void tb_add_jump(TranslationBlock *tb, int n, - TranslationBlock *tb_next) -{ - assert(n < ARRAY_SIZE(tb->jmp_list_next)); - if (tb->jmp_list_next[n]) { - /* Another thread has already done this while we were - * outside of the lock; nothing to do in this case */ - return; - } - qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, - "Linking TBs %p [" TARGET_FMT_lx - "] index %d -> %p [" TARGET_FMT_lx "]\n", - tb->tc_ptr, tb->pc, n, - tb_next->tc_ptr, tb_next->pc); - - /* patch the native jump address */ - tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); - - /* add in TB jmp circular list */ - tb->jmp_list_next[n] =3D tb_next->jmp_list_first; - tb_next->jmp_list_first =3D (uintptr_t)tb | n; -} +void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); =20 /* GETPC is the true target of the return instruction that we'll execute. = */ #if defined(CONFIG_TCG_INTERPRETER) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 55a46ac825..3c3b1e603d 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -111,10 +111,13 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 +#define TCG_TARGET_HAS_direct_jump 1 =20 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { __builtin___clear_cache((char *)start, (char *)stop); } =20 +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); + #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 5ef1086710..b836f7f127 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -124,6 +124,7 @@ extern bool use_idiv_instructions; #define TCG_TARGET_HAS_div_i32 use_idiv_instructions #define TCG_TARGET_HAS_rem_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 0 =20 enum { TCG_AREG0 =3D TCG_REG_R6, @@ -134,4 +135,7 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) __builtin___clear_cache((char *) start, (char *) stop); } =20 +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); + #endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 73a15f7e80..2fd28fa6a5 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -108,6 +108,7 @@ extern bool have_popcnt; #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 1 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_TARGET_HAS_extrl_i64_i32 0 @@ -166,6 +167,14 @@ static inline void flush_icache_range(uintptr_t start,= uintptr_t stop) { } =20 +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, + uintptr_t jmp_addr, uintptr_t = addr) +{ + /* patch the branch destination */ + atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); + /* no need to flush icache explicitly */ +} + /* This defines the natural memory order supported by this * architecture before guarantees made by various barrier * instructions. diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h index 901bb7575d..5c9ca8c1ce 100644 --- a/tcg/ia64/tcg-target.h +++ b/tcg/ia64/tcg-target.h @@ -174,6 +174,7 @@ typedef enum { #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 #define TCG_TARGET_HAS_goto_ptr 0 +#define TCG_TARGET_HAS_direct_jump 0 =20 #define TCG_TARGET_deposit_i32_valid(ofs, len) ((len) <=3D 16) #define TCG_TARGET_deposit_i64_valid(ofs, len) ((len) <=3D 16) @@ -195,4 +196,7 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) asm volatile (";;sync.i;;srlz.i;;"); } =20 +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); + #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d75cb63ed3..557c8ddc46 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -131,6 +131,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_mulsh_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 1 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_TARGET_HAS_add2_i32 0 @@ -206,4 +207,6 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) cacheflush ((void *)start, stop-start, ICACHE); } =20 +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); + #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5f4a40a5b4..5bab3387e5 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -83,6 +83,7 @@ extern bool have_isa_3_00; #define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 1 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_TARGET_HAS_add2_i32 0 @@ -124,5 +125,6 @@ extern bool have_isa_3_00; #endif =20 void flush_icache_range(uintptr_t start, uintptr_t stop); +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 81fc179459..1398952d6b 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -95,6 +95,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 1 =20 #define TCG_TARGET_HAS_div2_i64 1 #define TCG_TARGET_HAS_rot_i64 1 @@ -143,4 +144,13 @@ static inline void flush_icache_range(uintptr_t start,= uintptr_t stop) { } =20 +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, + uintptr_t jmp_addr, uintptr_t = addr) +{ + /* patch the branch destination */ + intptr_t disp =3D addr - (jmp_addr - 2); + atomic_set((int32_t *)jmp_addr, disp / 2); + /* no need to flush icache explicitly */ +} + #endif diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 854a0afd70..3ac0bd33d3 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -124,6 +124,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 1 =20 #define TCG_TARGET_HAS_extrl_i64_i32 1 #define TCG_TARGET_HAS_extrh_i64_i32 1 @@ -170,4 +171,6 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) } } =20 +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); + #endif diff --git a/tcg/tcg.h b/tcg/tcg.h index 17b7750ee6..46957d9bd7 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -652,8 +652,8 @@ struct TCGContext { /* goto_tb support */ tcg_insn_unit *code_buf; uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */ - uint16_t *tb_jmp_insn_offset; /* tb->jmp_insn_offset if USE_DIRECT_JUM= P */ - uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_addr if !USE_DIRECT_J= UMP */ + uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */ + uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */ =20 TCGRegSet reserved_regs; intptr_t current_frame_offset; diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 06963288dc..036e8049c8 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -86,6 +86,7 @@ #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_goto_ptr 0 +#define TCG_TARGET_HAS_direct_jump 1 =20 #if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_TARGET_HAS_extrl_i64_i32 0 @@ -192,4 +193,12 @@ static inline void flush_icache_range(uintptr_t start,= uintptr_t stop) { } =20 +static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, + uintptr_t jmp_addr, uintptr_t = addr) +{ + /* patch the branch destination */ + atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4)); + /* no need to flush icache explicitly */ +} + #endif /* TCG_TARGET_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index d84b01d1b8..ff6866624a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -329,6 +329,41 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, targ= et_ulong pc, return qht_lookup(&tcg_ctx.tb_ctx.htable, tb_cmp, &desc, h); } =20 +void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr) +{ + if (TCG_TARGET_HAS_direct_jump) { + uintptr_t offset =3D tb->jmp_target_arg[n]; + uintptr_t tc_ptr =3D (uintptr_t)tb->tc_ptr; + tb_target_set_jmp_target(tc_ptr, tc_ptr + offset, addr); + } else { + tb->jmp_target_arg[n] =3D addr; + } +} + +/* Called with tb_lock held. */ +static inline void tb_add_jump(TranslationBlock *tb, int n, + TranslationBlock *tb_next) +{ + assert(n < ARRAY_SIZE(tb->jmp_list_next)); + if (tb->jmp_list_next[n]) { + /* Another thread has already done this while we were + * outside of the lock; nothing to do in this case */ + return; + } + qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, + "Linking TBs %p [" TARGET_FMT_lx + "] index %d -> %p [" TARGET_FMT_lx "]\n", + tb->tc_ptr, tb->pc, n, + tb_next->tc_ptr, tb_next->pc); + + /* patch the native jump address */ + tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); + + /* add in TB jmp circular list */ + tb->jmp_list_next[n] =3D tb_next->jmp_list_first; + tb_next->jmp_list_first =3D (uintptr_t)tb | n; +} + static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *last_tb, int tb_exit) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 37ecafa931..93a1cf2ba8 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1289,13 +1289,13 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->jmp_reset_offset[0] =3D TB_JMP_RESET_OFFSET_INVALID; tb->jmp_reset_offset[1] =3D TB_JMP_RESET_OFFSET_INVALID; tcg_ctx.tb_jmp_reset_offset =3D tb->jmp_reset_offset; -#ifdef USE_DIRECT_JUMP - tcg_ctx.tb_jmp_insn_offset =3D tb->jmp_insn_offset; - tcg_ctx.tb_jmp_target_addr =3D NULL; -#else - tcg_ctx.tb_jmp_insn_offset =3D NULL; - tcg_ctx.tb_jmp_target_addr =3D tb->jmp_target_addr; -#endif + if (TCG_TARGET_HAS_direct_jump) { + tcg_ctx.tb_jmp_insn_offset =3D tb->jmp_target_arg; + tcg_ctx.tb_jmp_target_addr =3D NULL; + } else { + tcg_ctx.tb_jmp_insn_offset =3D NULL; + tcg_ctx.tb_jmp_target_addr =3D tb->jmp_target_arg; + } =20 #ifdef CONFIG_PROFILER tcg_ctx.tb_count++; diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 04bc369a92..a1e5dd2f03 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -871,9 +871,8 @@ static inline void tcg_out_call(TCGContext *s, tcg_insn= _unit *target) } } =20 -#ifdef USE_DIRECT_JUMP - -void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) { tcg_insn_unit i1, i2; TCGType rt =3D TCG_TYPE_I64; @@ -898,8 +897,6 @@ void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uint= ptr_t addr) flush_icache_range(jmp_addr, jmp_addr + 8); } =20 -#endif - static inline void tcg_out_goto_label(TCGContext *s, TCGLabel *l) { if (!l->has_value) { @@ -1412,7 +1409,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset !=3D NULL) { - /* USE_DIRECT_JUMP */ + /* TCG_TARGET_HAS_direct_jump */ /* Ensure that ADRP+ADD are 8-byte aligned so that an atomic write can be used to patch the target address. */ if ((uintptr_t)s->code_ptr & 7) { @@ -1420,11 +1417,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); /* actual branch destination will be patched by - aarch64_tb_set_jmp_target later. */ + tb_target_set_jmp_target later. */ tcg_out_insn(s, 3406, ADRP, TCG_REG_TMP, 0); tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_TMP, TCG_REG= _TMP, 0); } else { - /* !USE_DIRECT_JUMP */ + /* !TCG_TARGET_HAS_direct_jump */ tcg_debug_assert(s->tb_jmp_target_addr !=3D NULL); intptr_t offset =3D tcg_pcrel_diff(s, (s->tb_jmp_target_addr += a0)) >> 2; tcg_out_insn(s, 3305, LDR, offset, TCG_REG_TMP); diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 1a8169f5fc..04f8c839fe 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -2642,7 +2642,8 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer = */ } =20 -void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) { atomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); flush_icache_range(jmp_addr, jmp_addr + 4); diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 1f690df20d..018c240f6d 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1296,7 +1296,8 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) } =20 #ifdef __powerpc64__ -void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) { tcg_insn_unit i1, i2; uint64_t pair; @@ -1328,7 +1329,8 @@ void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintpt= r_t addr) flush_icache_range(jmp_addr, jmp_addr + 8); } #else -void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) { intptr_t diff =3D addr - jmp_addr; tcg_debug_assert(in_range_b(diff)); diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 18afce2f87..06cabbedf5 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -1708,7 +1708,8 @@ void tcg_register_jit(void *buf, size_t buf_size) tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } =20 -void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) { uint32_t *ptr =3D (uint32_t *)jmp_addr; uintptr_t disp =3D addr - jmp_addr; --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501826204355277.85262780213657; Thu, 3 Aug 2017 22:56:44 -0700 (PDT) Received: from localhost ([::1]:36770 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVbG-0006ZT-9O for importer@patchew.org; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.28 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=NDOenhlzQJ0c73Yr++olgNu3o5OBxKe1YDe0ftp2YM0=; b=t/WJPGacVeVGkHEwaSFNY5cdp0q8Ps0rEPeU+/97B3TlsiI1sV3ltOP+HtDjPuds0G gCt0ipL9HFcevQLF8afc5Tdz47EV6Qd6OD1jfTmkFzf0hzy2Qj8808HEpcaYZoygtJPX /DCGNGpmcjKHVCKGT+KbLfgGnp8JYeUZmC1vtXfSzEuKyfIk1FX8nW959/09eVfLSAW+ TyX4kcStPK5W95Z5E+EXZfLHXzLc3DQ4Nw+Re5UJqvfN5UXuwFtkolaBYLRfSjFh5Vz1 uOPpG3hDXngAFHeZpbXKoj1+iDV+wvlkhEdhqZN9FKbGFuGxA/tuDxRvb2RcucgurbI0 YiQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=NDOenhlzQJ0c73Yr++olgNu3o5OBxKe1YDe0ftp2YM0=; b=bmg6VZ8sE+KfzjoVquTClDhrErDnDZFXGofq7b5nXE6aTlPR+eNCEDI+0aLA1eEdYx ShAYf9TtRT+CN5feln+mO8LxkIakGaXFdPs9t9zhf+raJMr9KkUKOZ27oed/4FFHmCci Al1dkw1FQd36LQGylGhk4Ao+UywwAt+7d40oZGZu9vBJ/u1z5dScLpnwCbJ5edYJDxHh IgHr3NGFgx7z0i8/EbvX5uj74tH13W0z69y8BKGEX/+1BjUZqXOWkTguXhBPIhtJkUib bNlElN27KXTGX9+Hz5elw2IHrKulD6QChXeeWYftjQ7QCWo/uJ1/wnMKLHgi3YzqLbh0 QGQQ== X-Gm-Message-State: AIVw113vzp4SvlF2TN6WtLfo+hQcFhlVcz9GOebJ+qJyyiIbvtCbj5MO jSClYKb9zvucHLPefPw= X-Received: by 10.98.138.22 with SMTP id y22mr1241369pfd.9.1501825469610; Thu, 03 Aug 2017 22:44:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:05 -0700 Message-Id: <20170804054426.10590-3-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH for-2.11 02/23] tcg: Rearrange ldst label tracking X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Dispense with TCGBackendData, as it has never been used for more than holding a single pointer. Use a define in the cpu/tcg-target.h to signal requirement for TCGLabelQemuLdst, so that we can drop the no-op tcg-be-null.h stubs. Rename tcg-be-ldst.h to tcg-ldst.inc.c. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- tcg/aarch64/tcg-target.h | 4 ++++ tcg/arm/tcg-target.h | 4 ++++ tcg/i386/tcg-target.h | 4 ++++ tcg/ia64/tcg-target.h | 4 ++++ tcg/mips/tcg-target.h | 4 ++++ tcg/ppc/tcg-target.h | 4 ++++ tcg/s390/tcg-target.h | 4 ++++ tcg/tcg-be-null.h | 44 -------------------------------= ---- tcg/tcg.h | 6 +++-- tcg/aarch64/tcg-target.inc.c | 3 ++- tcg/arm/tcg-target.inc.c | 3 ++- tcg/i386/tcg-target.inc.c | 4 ++-- tcg/ia64/tcg-target.inc.c | 19 ++++----------- tcg/mips/tcg-target.inc.c | 4 ++-- tcg/ppc/tcg-target.inc.c | 4 ++-- tcg/s390/tcg-target.inc.c | 4 ++-- tcg/sparc/tcg-target.inc.c | 2 -- tcg/{tcg-be-ldst.h =3D> tcg-ldst.inc.c} | 27 ++++----------------- tcg/tcg.c | 17 +++++++------- tcg/tci/tcg-target.inc.c | 2 -- 20 files changed, 61 insertions(+), 106 deletions(-) delete mode 100644 tcg/tcg-be-null.h rename tcg/{tcg-be-ldst.h =3D> tcg-ldst.inc.c} (85%) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 3c3b1e603d..484cf6236c 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -120,4 +120,8 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) =20 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif + #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index b836f7f127..55de35a691 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -138,4 +138,8 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) /* not defined -- call should be eliminated at compile time */ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif + #endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 2fd28fa6a5..11ee7fadd1 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -186,4 +186,8 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, =20 #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) =20 +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif + #endif diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h index 5c9ca8c1ce..83107e1407 100644 --- a/tcg/ia64/tcg-target.h +++ b/tcg/ia64/tcg-target.h @@ -199,4 +199,8 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) /* not defined -- call should be eliminated at compile time */ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif + #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 557c8ddc46..bea5290b9f 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -209,4 +209,8 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) =20 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif + #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5bab3387e5..c1226ea5b6 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -127,4 +127,8 @@ extern bool have_isa_3_00; void flush_icache_range(uintptr_t start, uintptr_t stop); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif + #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 1398952d6b..8fea9646b4 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -153,4 +153,8 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, /* no need to flush icache explicitly */ } =20 +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif + #endif diff --git a/tcg/tcg-be-null.h b/tcg/tcg-be-null.h deleted file mode 100644 index 5222fe29e2..0000000000 --- a/tcg/tcg-be-null.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * TCG Backend Data: No backend data - * - * Permission is hereby granted, free of charge, to any person obtaining a= copy - * of this software and associated documentation files (the "Software"), t= o deal - * in the Software without restriction, including without limitation the r= ights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included= in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN - * THE SOFTWARE. - */ - -typedef struct TCGBackendData { - /* Empty */ - char dummy; -} TCGBackendData; - - -/* - * Initialize TB backend data at the beginning of the TB. - */ - -static inline void tcg_out_tb_init(TCGContext *s) -{ -} - -/* - * Generate TB finalization at the end of block - */ - -static inline bool tcg_out_tb_finalize(TCGContext *s) -{ - return true; -} diff --git a/tcg/tcg.h b/tcg/tcg.h index 46957d9bd7..b0e00e744e 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -712,8 +712,10 @@ struct TCGContext { CPUState *cpu; /* *_trans */ TCGv_env tcg_env; /* *_exec */ =20 - /* The TCGBackendData structure is private to tcg-target.inc.c. */ - struct TCGBackendData *be; + /* These structures are private to tcg-target.inc.c. */ +#ifdef TCG_TARGET_NEED_LDST_LABELS + struct TCGLabelQemuLdst *ldst_labels; +#endif =20 TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index a1e5dd2f03..c7c751bafc 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -10,7 +10,6 @@ * See the COPYING file in the top-level directory for details. */ =20 -#include "tcg-be-ldst.h" #include "qemu/bitops.h" =20 /* We're going to re-use TCGType in setting of the SF bit, which controls @@ -1070,6 +1069,8 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, = TCGReg d, } =20 #ifdef CONFIG_SOFTMMU +#include "tcg-ldst.inc.c" + /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * TCGMemOpIdx oi, uintptr_t ra) */ diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 37efcf06af..81ea900852 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -23,7 +23,6 @@ */ =20 #include "elf.h" -#include "tcg-be-ldst.h" =20 int arm_arch =3D __ARM_ARCH; =20 @@ -1060,6 +1059,8 @@ static inline void tcg_out_mb(TCGContext *s, TCGArg a= 0) } =20 #ifdef CONFIG_SOFTMMU +#include "tcg-ldst.inc.c" + /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index e4b120a40c..1a1ad96906 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -22,8 +22,6 @@ * THE SOFTWARE. */ =20 -#include "tcg-be-ldst.h" - #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -1214,6 +1212,8 @@ static void tcg_out_nopn(TCGContext *s, int n) } =20 #if defined(CONFIG_SOFTMMU) +#include "tcg-ldst.inc.c" + /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ diff --git a/tcg/ia64/tcg-target.inc.c b/tcg/ia64/tcg-target.inc.c index bf9a97d75c..3569f2b457 100644 --- a/tcg/ia64/tcg-target.inc.c +++ b/tcg/ia64/tcg-target.inc.c @@ -1565,29 +1565,19 @@ typedef struct TCGLabelQemuLdst { struct TCGLabelQemuLdst *next; } TCGLabelQemuLdst; =20 -typedef struct TCGBackendData { - TCGLabelQemuLdst *labels; -} TCGBackendData; - -static inline void tcg_out_tb_init(TCGContext *s) -{ - s->be->labels =3D NULL; -} - static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc, tcg_insn_unit *label_ptr) { - TCGBackendData *be =3D s->be; TCGLabelQemuLdst *l =3D tcg_malloc(sizeof(*l)); =20 l->is_ld =3D is_ld; l->size =3D opc & MO_SIZE; l->label_ptr =3D label_ptr; - l->next =3D be->labels; - be->labels =3D l; + l->next =3D s->ldst_labels; + s->ldst_labels =3D l; } =20 -static bool tcg_out_tb_finalize(TCGContext *s) +static bool tcg_out_ldst_finalize(TCGContext *s) { static const void * const helpers[8] =3D { helper_ret_stb_mmu, @@ -1602,7 +1592,7 @@ static bool tcg_out_tb_finalize(TCGContext *s) tcg_insn_unit *thunks[8] =3D { }; TCGLabelQemuLdst *l; =20 - for (l =3D s->be->labels; l !=3D NULL; l =3D l->next) { + for (l =3D s->ldst_labels; l !=3D NULL; l =3D l->next) { long x =3D l->is_ld * 4 + l->size; tcg_insn_unit *dest =3D thunks[x]; =20 @@ -1767,7 +1757,6 @@ static inline void tcg_out_qemu_st(TCGContext *s, con= st TCGArg *args) } =20 #else /* !CONFIG_SOFTMMU */ -# include "tcg-be-null.h" =20 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args) { diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 04f8c839fe..750baadf37 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -24,8 +24,6 @@ * THE SOFTWARE. */ =20 -#include "tcg-be-ldst.h" - #ifdef HOST_WORDS_BIGENDIAN # define MIPS_BE 1 #else @@ -1112,6 +1110,8 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit= *arg) } =20 #if defined(CONFIG_SOFTMMU) +#include "tcg-ldst.inc.c" + static void * const qemu_ld_helpers[16] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_SB] =3D helper_ret_ldsb_mmu, diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 018c240f6d..d772faf7be 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -22,8 +22,6 @@ * THE SOFTWARE. */ =20 -#include "tcg-be-ldst.h" - #if defined _CALL_DARWIN || defined __APPLE__ #define TCG_TARGET_CALL_DARWIN #endif @@ -1418,6 +1416,8 @@ static const uint32_t qemu_exts_opc[4] =3D { }; =20 #if defined (CONFIG_SOFTMMU) +#include "tcg-ldst.inc.c" + /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) */ diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 38b9e791ee..ee0dff995a 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -24,8 +24,6 @@ * THE SOFTWARE. */ =20 -#include "tcg-be-ldst.h" - /* We only support generating code for 64-bit mode. */ #if TCG_TARGET_REG_BITS !=3D 64 #error "unsupported code generation mode" @@ -1458,6 +1456,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= MemOp opc, TCGReg data, } =20 #if defined(CONFIG_SOFTMMU) +#include "tcg-ldst.inc.c" + /* We're expecting to use a 20-bit signed offset on the tlb memory ops. Using the offset of the second entry in the last tlb table ensures that we can index all of the elements of the first entry. */ diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 06cabbedf5..bb7f7e8906 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -22,8 +22,6 @@ * THE SOFTWARE. */ =20 -#include "tcg-be-null.h" - #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { "%g0", diff --git a/tcg/tcg-be-ldst.h b/tcg/tcg-ldst.inc.c similarity index 85% rename from tcg/tcg-be-ldst.h rename to tcg/tcg-ldst.inc.c index 17777aec5a..0e14cf4357 100644 --- a/tcg/tcg-be-ldst.h +++ b/tcg/tcg-ldst.inc.c @@ -20,8 +20,6 @@ * THE SOFTWARE. */ =20 -#ifdef CONFIG_SOFTMMU - typedef struct TCGLabelQemuLdst { bool is_ld; /* qemu_ld: true, qemu_st: false */ TCGMemOpIdx oi; @@ -35,19 +33,6 @@ typedef struct TCGLabelQemuLdst { struct TCGLabelQemuLdst *next; } TCGLabelQemuLdst; =20 -typedef struct TCGBackendData { - TCGLabelQemuLdst *labels; -} TCGBackendData; - - -/* - * Initialize TB backend data at the beginning of the TB. - */ - -static inline void tcg_out_tb_init(TCGContext *s) -{ - s->be->labels =3D NULL; -} =20 /* * Generate TB finalization at the end of block @@ -56,12 +41,12 @@ static inline void tcg_out_tb_init(TCGContext *s) static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l); static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l); =20 -static bool tcg_out_tb_finalize(TCGContext *s) +static bool tcg_out_ldst_finalize(TCGContext *s) { TCGLabelQemuLdst *lb; =20 /* qemu_ld/st slow paths */ - for (lb =3D s->be->labels; lb !=3D NULL; lb =3D lb->next) { + for (lb =3D s->ldst_labels; lb !=3D NULL; lb =3D lb->next) { if (lb->is_ld) { tcg_out_qemu_ld_slow_path(s, lb); } else { @@ -85,13 +70,9 @@ static bool tcg_out_tb_finalize(TCGContext *s) =20 static inline TCGLabelQemuLdst *new_ldst_label(TCGContext *s) { - TCGBackendData *be =3D s->be; TCGLabelQemuLdst *l =3D tcg_malloc(sizeof(*l)); =20 - l->next =3D be->labels; - be->labels =3D l; + l->next =3D s->ldst_labels; + s->ldst_labels =3D l; return l; } -#else -#include "tcg-be-null.h" -#endif /* CONFIG_SOFTMMU */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 35598296c5..dd74eabb0a 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -112,10 +112,9 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, T= CGArg val, static void tcg_out_call(TCGContext *s, tcg_insn_unit *target); static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct); -static void tcg_out_tb_init(TCGContext *s); -static bool tcg_out_tb_finalize(TCGContext *s); - - +#ifdef TCG_TARGET_NEED_LDST_LABELS +static bool tcg_out_ldst_finalize(TCGContext *s); +#endif =20 static TCGRegSet tcg_target_available_regs[2]; static TCGRegSet tcg_target_call_clobber_regs; @@ -470,8 +469,6 @@ void tcg_func_start(TCGContext *s) s->gen_op_buf[0].prev =3D 0; s->gen_next_op_idx =3D 1; s->gen_next_parm_idx =3D 0; - - s->be =3D tcg_malloc(sizeof(TCGBackendData)); } =20 static inline int temp_idx(TCGContext *s, TCGTemp *ts) @@ -2619,7 +2616,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) s->code_buf =3D tb->tc_ptr; s->code_ptr =3D tb->tc_ptr; =20 - tcg_out_tb_init(s); +#ifdef TCG_TARGET_NEED_LDST_LABELS + s->ldst_labels =3D NULL; +#endif =20 num_insns =3D -1; for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { @@ -2694,9 +2693,11 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) s->gen_insn_end_off[num_insns] =3D tcg_current_code_size(s); =20 /* Generate TB finalization at the end of block */ - if (!tcg_out_tb_finalize(s)) { +#ifdef TCG_TARGET_NEED_LDST_LABELS + if (!tcg_out_ldst_finalize(s)) { return -1; } +#endif =20 /* flush instruction cache */ flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c index b6a15569f8..94461b2baf 100644 --- a/tcg/tci/tcg-target.inc.c +++ b/tcg/tci/tcg-target.inc.c @@ -22,8 +22,6 @@ * THE SOFTWARE. */ =20 -#include "tcg-be-null.h" - /* TODO list: * - See TODO comments in code. */ --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH for-2.11 03/23] tcg: Infrastructure for managing constant pools X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" A new shared header tcg-pool.inc.c adds new_pool_label, for registering a tcg_target_ulong to be emitted after the generated code, plus relocation data to install a pointer to the data. A new pointer is added to the TCGContext, so that we dump the constant pool as data, not code. Signed-off-by: Richard Henderson --- tcg/tcg.h | 4 +++ accel/tcg/translate-all.c | 22 +++++++++++- tcg/tcg-pool.inc.c | 85 +++++++++++++++++++++++++++++++++++++++++++= ++++ tcg/tcg.c | 9 +++++ 4 files changed, 119 insertions(+), 1 deletion(-) create mode 100644 tcg/tcg-pool.inc.c diff --git a/tcg/tcg.h b/tcg/tcg.h index b0e00e744e..ac94133870 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -702,6 +702,7 @@ struct TCGContext { void *code_gen_buffer; size_t code_gen_buffer_size; void *code_gen_ptr; + void *data_gen_ptr; =20 /* Threshold to flush the translated code buffer. */ void *code_gen_highwater; @@ -716,6 +717,9 @@ struct TCGContext { #ifdef TCG_TARGET_NEED_LDST_LABELS struct TCGLabelQemuLdst *ldst_labels; #endif +#ifdef TCG_TARGET_NEED_POOL_LABELS + struct TCGLabelPoolData *pool_labels; +#endif =20 TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 93a1cf2ba8..2d1ed06065 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1329,7 +1329,27 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qemu_log_in_addr_range(tb->pc)) { qemu_log_lock(); qemu_log("OUT: [size=3D%d]\n", gen_code_size); - log_disas(tb->tc_ptr, gen_code_size); + if (tcg_ctx.data_gen_ptr) { + size_t code_size =3D tcg_ctx.data_gen_ptr - tb->tc_ptr; + size_t data_size =3D gen_code_size - code_size; + size_t i; + + log_disas(tb->tc_ptr, code_size); + + for (i =3D 0; i < data_size; i +=3D sizeof(tcg_target_ulong)) { + if (sizeof(tcg_target_ulong) =3D=3D 8) { + qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n= ", + (uintptr_t)tcg_ctx.data_gen_ptr + i, + *(uint64_t *)(tcg_ctx.data_gen_ptr + i)); + } else { + qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n", + (uintptr_t)tcg_ctx.data_gen_ptr + i, + *(uint32_t *)(tcg_ctx.data_gen_ptr + i)); + } + } + } else { + log_disas(tb->tc_ptr, gen_code_size); + } qemu_log("\n"); qemu_log_flush(); qemu_log_unlock(); diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c new file mode 100644 index 0000000000..8a85131405 --- /dev/null +++ b/tcg/tcg-pool.inc.c @@ -0,0 +1,85 @@ +/* + * TCG Backend Data: constant pool. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +typedef struct TCGLabelPoolData { + struct TCGLabelPoolData *next; + tcg_target_ulong data; + tcg_insn_unit *label; + intptr_t addend; + int type; +} TCGLabelPoolData; + + +static void new_pool_label(TCGContext *s, tcg_target_ulong data, int type, + tcg_insn_unit *label, intptr_t addend) +{ + TCGLabelPoolData *n =3D tcg_malloc(sizeof(*n)); + TCGLabelPoolData *i, **pp; + + n->data =3D data; + n->label =3D label; + n->type =3D type; + n->addend =3D addend; + + /* Insertion sort on the pool. */ + for (pp =3D &s->pool_labels; (i =3D *pp) && i->data < data; pp =3D &i-= >next) { + continue; + } + n->next =3D *pp; + *pp =3D n; +} + +/* To be provided by cpu/tcg-target.inc.c. */ +static void tcg_out_nop_fill(tcg_insn_unit *p, int count); + +static bool tcg_out_pool_finalize(TCGContext *s) +{ + TCGLabelPoolData *p =3D s->pool_labels; + tcg_target_ulong d, *a; + + if (p =3D=3D NULL) { + return true; + } + + /* ??? Round up to qemu_icache_linesize, but then do not round + again when allocating the next TranslationBlock structure. */ + a =3D (void *)ROUND_UP((uintptr_t)s->code_ptr, sizeof(tcg_target_ulong= )); + tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr); + s->data_gen_ptr =3D a; + + /* Ensure the first comparison fails. */ + d =3D p->data + 1; + + for (; p !=3D NULL; p =3D p->next) { + if (p->data !=3D d) { + d =3D p->data; + if (unlikely((void *)a > s->code_gen_highwater)) { + return false; + } + *a++ =3D d; + } + patch_reloc(p->label, p->type, (intptr_t)(a - 1), p->addend); + } + + s->code_ptr =3D (void *)a; + return true; +} diff --git a/tcg/tcg.c b/tcg/tcg.c index dd74eabb0a..fd8a3dfe93 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -399,6 +399,7 @@ TranslationBlock *tcg_tb_alloc(TCGContext *s) return NULL; } s->code_gen_ptr =3D next; + s->data_gen_ptr =3D NULL; return tb; } =20 @@ -2619,6 +2620,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #ifdef TCG_TARGET_NEED_LDST_LABELS s->ldst_labels =3D NULL; #endif +#ifdef TCG_TARGET_NEED_POOL_LABELS + s->pool_labels =3D NULL; +#endif =20 num_insns =3D -1; for (oi =3D s->gen_op_buf[0].next; oi !=3D 0; oi =3D oi_next) { @@ -2698,6 +2702,11 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) return -1; } #endif +#ifdef TCG_TARGET_NEED_POOL_LABELS + if (!tcg_out_pool_finalize(s)) { + return -1; + } +#endif =20 /* flush instruction cache */ flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr); --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501825734455811.8319649479498; Thu, 3 Aug 2017 22:48:54 -0700 (PDT) Received: from localhost ([::1]:36671 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVTg-00079L-OS for importer@patchew.org; Fri, 04 Aug 2017 01:48:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59430) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPW-0003nl-Fr for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPU-00035k-Ti for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:34 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:37010) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPU-00033n-MW for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:32 -0400 Received: by mail-pg0-x244.google.com with SMTP id 83so821866pgb.4 for ; Thu, 03 Aug 2017 22:44:32 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.30 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=BuEv1csrc3JSE+NkEWeag8w9qi/jTQAr7Da/v5oxytI=; b=GWiq7y8NSeJQPVfAoPMZj7uNERDILcito5Vqq6MkQJBs5lznOGWG1Y3M6Gv/eEkkII PYuAOvTUxZXPNayvAza9QGgqQTCm1ZWU3pfLybKNol9++y28WEVr//U8eOdRS533PLf0 Ftf5pLkt2cdan8pwcwRmrYQ7sm6VKvXoOt+7D7NJl869FCpaQPgZGIuiJYZLAQPWpyoc ncyo7dJ4MpjDf8WpClLcGrlVklkU+qNeap5yKBGDoPxr86Ze1NWjhwRDu+v7bl6guC/V hORWExJMZAispC2VTKvlSToKhcYD4A8QrW/YBBXuUD2cGaie7znt4ITuE5xTZU6W3F8s dbAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=BuEv1csrc3JSE+NkEWeag8w9qi/jTQAr7Da/v5oxytI=; b=Vvnvmi7IW7sSdV4SjoXL05TDyleyImmqxxpafYUVi4Z/L46ShN1vi59RzlDuRDiCTR 0ddakLp2LDJxILT+aKO1v0V15ErSg0O6zKuCocsUUUB+Zby5r1np/Ppqme03G3Y9XpQW E4fpagt85SjpMwN5D/GF6gMKLwfs9DqPSU94bxU0RgxbJ9gxDqhz8pD/1bT9yamIIKps Kk4o2sVs54zwafyjslFkhd2hi8lTeBlKUIVFPLWE2CrurVLxorkXfGEsSPnLWALj81VY aEC0OWy2CmFhThDck71kXtu8jLxp2grE/sjQPbY6ytwXp/pjK4+ja2yOWX9dAvbFxt7p YlCQ== X-Gm-Message-State: AIVw113nxOXw79y9yzsZVN49g/MLGrzL9rvm4RSkETqW8sEtUidYcOaA Rx9MCEhwXDTUELWT+cA= X-Received: by 10.98.36.198 with SMTP id k67mr1284220pfk.154.1501825471434; Thu, 03 Aug 2017 22:44:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:07 -0700 Message-Id: <20170804054426.10590-5-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH for-2.11 04/23] tcg/i386: Store out-of-range call targets in constant pool X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Already it saves 2 bytes per call, but also the constant pool entry may well be shared across multiple calls. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 1 + tcg/i386/tcg-target.inc.c | 18 +++++++++++++++--- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 11ee7fadd1..b89dababf4 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -189,5 +189,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif +#define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 1a1ad96906..5231056fd3 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -22,6 +22,8 @@ * THE SOFTWARE. */ =20 +#include "tcg-pool.inc.c" + #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -1180,9 +1182,14 @@ static void tcg_out_branch(TCGContext *s, int call, = tcg_insn_unit *dest) tcg_out_opc(s, call ? OPC_CALL_Jz : OPC_JMP_long, 0, 0, 0); tcg_out32(s, disp); } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R10, (uintptr_t)dest); - tcg_out_modrm(s, OPC_GRP5, - call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev, TCG_REG_R10); + /* rip-relative addressing into the constant pool. + This is 6 + 8 =3D 14 bytes, as compared to using an + an immediate load 10 + 6 =3D 16 bytes, plus we may + be able to re-use the pool constant for more calls. */ + tcg_out_opc(s, OPC_GRP5, 0, 0, 0); + tcg_out8(s, (call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev) << 3 | 5); + new_pool_label(s, (uintptr_t)dest, R_386_PC32, s->code_ptr, -4); + tcg_out32(s, 0); } } =20 @@ -2595,6 +2602,11 @@ static void tcg_target_qemu_prologue(TCGContext *s) #endif } =20 +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0x90, count); +} + static void tcg_target_init(TCGContext *s) { #ifdef CONFIG_CPUID_H --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501826050982424.33574402734735; Thu, 3 Aug 2017 22:54:10 -0700 (PDT) Received: from localhost ([::1]:36693 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVYn-0003f4-Kj for importer@patchew.org; Fri, 04 Aug 2017 01:54:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPY-0003q6-4W for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPW-00038a-0m for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:36 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:38628) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPV-00036b-OH for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:33 -0400 Received: by mail-pf0-x241.google.com with SMTP id h75so859450pfh.5 for ; Thu, 03 Aug 2017 22:44:33 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.31 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=5WuRhmNYy0zkJlZ8O+Y7ikF0OgtGL6YUuDmrlkKRppc=; b=sDJzy7TwfpvFs5tM0dsf+patE2nkAHyPh0Sw2rRbZrPBxbXDsPXeIll5wVWj7Ft4+h Z15PVaXzOnwU4MPS3bVgop1tLTD2cF8/PZ87+Nsi31aSzwoavYcgqpOpIc6NmwQGonf0 BsqPqY3lLjmSrHPrmB3ryTwGIszQBmd4aw/iLAEdbqCW1SIC6CIv3ARqTD4Nksha5RNd 1e8QFr1rHLtYZUzgFG80GPs9E32yT1a3K4EztKUtCBvl+26xlcPIrk0kVln0Ua6bRu3d B0OtZBpMX8Q3Ho9M5IBrjbPsqyD2ExT3tAbFjyvmEBMUah9+L9wEAok9aHDwmYIIyEJU 2Slw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=5WuRhmNYy0zkJlZ8O+Y7ikF0OgtGL6YUuDmrlkKRppc=; b=g2IxWHX+8Kl0z/QMISLGZsmabMYTjXDWQ98c8JwRWPTknY6KYeJ3ZT9N3PNk8M3XUB UH40HUCY7GLCiNcQe5qmzwlvCF996z7EPadYsYiqhCkHWeKLo0yGao2Tv9SCn/O36K74 41gL6xyYH7LaoRb4UiQh+b38xuy9kth9Ova0z/ulBT53h4denNUme6U9GiEj1z0kaa8N 94Y6Bx0XyO+WeOF2HBR3WrHS5LvoDNtwn6cU1/68Qh0Zec/w1iWwaWDX5uhSB7Nxz3Q7 UyFbdsDAQtINBW7kT/sVrnNn9XM2fQgxdjXyhTCYVcOYPwsW7MdExCMdFYVroWFTT1yL DrLQ== X-Gm-Message-State: AIVw112MQmbot2Ef3mr+lKhxicDbIsU0dkoWRPc+W37QmP5YOT45LNmk VX4v78XlNQg4x+ukt5E= X-Received: by 10.84.132.73 with SMTP id 67mr1373826ple.53.1501825472461; Thu, 03 Aug 2017 22:44:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:08 -0700 Message-Id: <20170804054426.10590-6-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH for-2.11 05/23] tcg/s390: Introduce TCG_REG_TB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 2 +- tcg/s390/tcg-target.inc.c | 71 +++++++++++++++++++++++++++++++++++++++----= ---- 2 files changed, 61 insertions(+), 12 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 8fea9646b4..8c5a30ccf8 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -95,7 +95,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 -#define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_direct_jump (s390_facilities & FACILITY_GEN_INST= _EXT) =20 #define TCG_TARGET_HAS_div2_i64 1 #define TCG_TARGET_HAS_rot_i64 1 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index ee0dff995a..e007586315 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -51,6 +51,12 @@ /* A scratch register that may be be used throughout the backend. */ #define TCG_TMP0 TCG_REG_R1 =20 +/* A scratch register that holds a pointer to the beginning of the TB. + We don't need this when we have pc-relative loads with the general + instructions extension facility. */ +#define TCG_REG_TB TCG_REG_R12 +#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT)) + #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_R13 #endif @@ -556,8 +562,8 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TC= GReg dst, TCGReg src) } =20 /* load a register with an immediate value */ -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long sval) +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long sval, bool in_prologue) { static const S390Opcode lli_insns[4] =3D { RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH @@ -601,13 +607,22 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 - /* Try for PC-relative address load. */ + /* Try for PC-relative address load. For odd addresses, + attempt to use an offset from the start of the TB. */ if ((sval & 1) =3D=3D 0) { ptrdiff_t off =3D tcg_pcrel_diff(s, (void *)sval) >> 1; if (off =3D=3D (int32_t)off) { tcg_out_insn(s, RIL, LARL, ret, off); return; } + } else if (USE_REG_TB && !in_prologue) { + ptrdiff_t off =3D sval - (uintptr_t)s->code_gen_ptr; + if (off =3D=3D sextract64(off, 0, 20)) { + /* This is certain to be an address within TB, and therefore + OFF will be negative; don't try RX_LA. */ + tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off); + return; + } } =20 /* If extended immediates are not present, then we may have to issue @@ -663,6 +678,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long sval) +{ + tcg_out_movi_int(s, type, ret, sval, false); +} =20 /* Emit a load/store type instruction. Inputs are: DATA: The register to be loaded or stored. @@ -739,6 +759,13 @@ static void tcg_out_ld_abs(TCGContext *s, TCGType type= , TCGReg dest, void *abs) return; } } + if (USE_REG_TB) { + ptrdiff_t disp =3D abs - (void *)s->code_gen_ptr; + if (disp =3D=3D sextract64(disp, 0, 20)) { + tcg_out_ld(s, type, dest, TCG_REG_TB, disp); + return; + } + } =20 tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff); tcg_out_ld(s, type, dest, dest, addr & 0xffff); @@ -1690,6 +1717,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, break; =20 case INDEX_op_goto_tb: + a0 =3D args[0]; if (s->tb_jmp_insn_offset) { /* branch displacement must be aligned for atomic patching; * see if we need to add extra nop before branch @@ -1697,21 +1725,34 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { tcg_out16(s, NOP); } + tcg_debug_assert(!USE_REG_TB); tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); - s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s); + s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); s->code_ptr +=3D 2; } else { - /* load address stored at s->tb_jmp_target_addr + args[0] */ - tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_TMP0, - s->tb_jmp_target_addr + args[0]); + /* load address stored at s->tb_jmp_target_addr + a0 */ + tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, + s->tb_jmp_target_addr + a0); /* and go there */ - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_TMP0); + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); + } + s->tb_jmp_reset_offset[a0] =3D tcg_current_code_size(s); + + /* For the unlinked path of goto_tb, we need to reset + TCG_REG_TB to the beginning of this TB. */ + if (USE_REG_TB) { + int ofs =3D -tcg_current_code_size(s); + assert(ofs =3D=3D (int16_t)ofs); + tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs); } - s->tb_jmp_reset_offset[args[0]] =3D tcg_current_code_size(s); break; =20 case INDEX_op_goto_ptr: - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, args[0]); + a0 =3D args[0]; + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); + } + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); break; =20 OP_32_64(ld8u): @@ -2476,6 +2517,9 @@ static void tcg_target_init(TCGContext *s) /* XXX many insns can't be used with R0, so we better avoid it for now= */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); + if (USE_REG_TB) { + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); + } } =20 #define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ @@ -2496,12 +2540,17 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 #ifndef CONFIG_SOFTMMU if (guest_base >=3D 0x80000) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, = true); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, + tcg_target_call_iarg_regs[1]); + } + /* br %r3 (go to TB) */ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]); =20 --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501825589707407.4476349163946; Thu, 3 Aug 2017 22:46:29 -0700 (PDT) Received: from localhost ([::1]:36664 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVRJ-0005Ay-Ux for importer@patchew.org; Fri, 04 Aug 2017 01:46:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59534) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPZ-0003rb-Bt for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPW-0003Az-UC for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:37 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:37013) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPW-00038r-MN for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:34 -0400 Received: by mail-pg0-x243.google.com with SMTP id 83so821932pgb.4 for ; Thu, 03 Aug 2017 22:44:34 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.32 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=X/0Co6YW9K1lstOeC237kzVIM42M5nyF0b897QyeSKE=; b=jqGLG4sAeFVdowsIuLoGgG2BFeacr4PsR1bYTpRYdMqxWMHVC3+0MpaYX8YOaJfrMb bJADp3Ch0ntkNRRuE+cQ0eAITrCyIis3jA3/K/Yb7E+TGZBya9jeNhcOOEiDbDlIJxnZ 0gQ6mZVza1RtwLHgs7dmJyyZaSd918JrNpnJqhhwt5i/4KJx0LipjzAGyDz2EsjHKRas lgQ1xsa2Mn+EljK9D1WHh7pw/uaSfG0eL+QVG8XTAxTl873AyYyrY3zKspjlFnEkdu4V q5oQ4LM+R7Rw7yvLeCBB7sFuoRGJSoCZzWtqxKiha2Zp7pannLTkfasrVfcRK8BzDYOL AYUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=X/0Co6YW9K1lstOeC237kzVIM42M5nyF0b897QyeSKE=; b=j0EqWH9Knvq1F5go12RSCBYEmFX4aKC4Xwg0zv2e7GG1tMwn9+d0Ic7TdCgCdDyeVG /FX/+/74u9fY0CsSwM1hkfps43IHvaMPyong8KjTwyVTP14vmY+PTsVe62qS+CIEtriW /VnJo6eIysRWSLJQ8CPtLdXtugY5HNagQ/g6h8vHxtZoesy3oYMZWptEduwdXsxWpojI IOYZfQSRvD6grgqnm7Z22K8gC7l2oJAJReJttG7oc6C8QZ6gg3nIIHSOuX/QWBcDWzbn bOkmNWLF0fR2YkTJnNy0KCt70cFZz8GiI9f3j+JZ3tQ/e6tAtqQRdTgLCsrNsw98H2QC rnkA== X-Gm-Message-State: AIVw110wXKtYOReENEh0IrNOKYMamzALQo6aQdtgoNeZikmsueo6M5d2 VjbH7qhY64qz8U3zytY= X-Received: by 10.84.171.195 with SMTP id l61mr1452096plb.464.1501825473469; Thu, 03 Aug 2017 22:44:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:09 -0700 Message-Id: <20170804054426.10590-7-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH for-2.11 06/23] tcg/s390: Fix sign of patch_reloc addend X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We were passing in -2 instead of +2, but then ignoring the actual contents of addend in the calculation. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index e007586315..59c0da0922 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -360,21 +360,22 @@ uint64_t s390_facilities; static void patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - intptr_t pcrel2 =3D (tcg_insn_unit *)value - (code_ptr - 1); - tcg_debug_assert(addend =3D=3D -2); + intptr_t pcrel2; + + value +=3D addend; + pcrel2 =3D (tcg_insn_unit *)value - code_ptr; =20 switch (type) { case R_390_PC16DBL: - tcg_debug_assert(pcrel2 =3D=3D (int16_t)pcrel2); + assert(pcrel2 =3D=3D (int16_t)pcrel2); tcg_patch16(code_ptr, pcrel2); break; case R_390_PC32DBL: - tcg_debug_assert(pcrel2 =3D=3D (int32_t)pcrel2); + assert(pcrel2 =3D=3D (int32_t)pcrel2); tcg_patch32(code_ptr, pcrel2); break; default: - tcg_abort(); - break; + g_assert_not_reached(); } } =20 @@ -1270,11 +1271,11 @@ static void tgen_branch(TCGContext *s, int cc, TCGL= abel *l) tgen_gotoi(s, cc, l->u.value_ptr); } else if (USE_LONG_BRANCHES) { tcg_out16(s, RIL_BRCL | (cc << 4)); - tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, l, -2); + tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, l, 2); s->code_ptr +=3D 2; } else { tcg_out16(s, RI_BRC | (cc << 4)); - tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, -2); + tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2); s->code_ptr +=3D 1; } } @@ -1289,7 +1290,7 @@ static void tgen_compare_branch(TCGContext *s, S390Op= code opc, int cc, } else { /* We need to keep the offset unchanged for retranslation. */ off =3D s->code_ptr[1]; - tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, -2); + tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); } =20 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2); @@ -1307,7 +1308,7 @@ static void tgen_compare_imm_branch(TCGContext *s, S3= 90Opcode opc, int cc, } else { /* We need to keep the offset unchanged for retranslation. */ off =3D s->code_ptr[1]; - tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, -2); + tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2); } =20 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc); @@ -1571,7 +1572,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); =20 - patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, -2= ); + patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2); =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); if (TARGET_LONG_BITS =3D=3D 64) { @@ -1592,7 +1593,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) TCGMemOpIdx oi =3D lb->oi; TCGMemOp opc =3D get_memop(oi); =20 - patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, -2= ); + patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2); =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); if (TARGET_LONG_BITS =3D=3D 64) { --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501825748808789.690056374518; Thu, 3 Aug 2017 22:49:08 -0700 (PDT) Received: from localhost ([::1]:36672 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVTv-0007Mp-CK for importer@patchew.org; Fri, 04 Aug 2017 01:49:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59578) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPa-0003uS-Hj for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPY-0003Eo-Cg for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:38 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34284) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPY-0003Cc-0R for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:36 -0400 Received: by mail-pg0-x244.google.com with SMTP id y192so836589pgd.1 for ; Thu, 03 Aug 2017 22:44:35 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.33 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=3b47U70YYw63Rv/TuTHnKo9gSR1eTcZNGsfBI0EZHR0=; b=jmCHFFp3wgsCxkjwoMaCgTVE8IYWhUP4MDl0k7254VcFlGgVZtHpGmUvRdhULcyLhg nRhQAtBlguIN4DrBlha1XbkMDl/aYv9xFRi5NJWbYzt0bqOt6Qt9SoAJLWtaUYOMANyE fXPVWaXfg+FvJP2NHp8oOljLQsrJYCxn06rqnxrGXfa7x8jXLyS+JzH9LyJsSX92GajX ymih//7pRT1BKGJqaiO8l6hMAcT0gek/kq3HaSqjtcSk2/gf5Rcq2nWxcMud6RLcXM7S waUnqRRa1cdBwkchldNoedl1Jd6nTh+/JFLjtUB2MyK06+m5bvsTUT8qi4W17IZUVWoW r0cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=3b47U70YYw63Rv/TuTHnKo9gSR1eTcZNGsfBI0EZHR0=; b=kXGhVrdWbZt667uSIqT5RvMpVz2hLWQRpn2b59R9AiJe1gmnrBgKJbZbJ7tzQXxWHH 8dD1ByEM1/vxA5WBtCmtZ1FzynpbUB90CKHBBti08VdntK1EbeygP2PL+UK8IJHkAw1I rSqsp0INS9JoJgNHzreBTYhjAwpGnIs8w6FGXcHCENG5PmPsWh5fVvgKmd18pEbsr+FH Pvzd1e2fVXjFUtfleHLcEvDHWa8he2sDVqe2XejeSJyRqIhTD6TwSPtcFvpM0dEUIh0y 15nqZ4xathEdUri+F2tPRlnTFFkPOIGsZxCdbMTHG6aONP6F0KCDE9ryzJz6aOVgQ6qf +rGA== X-Gm-Message-State: AIVw110VtEJcW5M1cpLFSNIRKYWYWUIvabpLrgHSrxYkrKeBX7FcRkj7 +ZkScJbSNeo9dk/ArNI= X-Received: by 10.84.232.78 with SMTP id f14mr1333078pln.87.1501825474546; Thu, 03 Aug 2017 22:44:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:10 -0700 Message-Id: <20170804054426.10590-8-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH for-2.11 07/23] tcg/s390: Use constant pool for movi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Split out maybe_out_small_movi for use with other operations that want to add to the constant pool. Signed-off-by: Richard Henderson --- include/elf.h | 3 +- tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.inc.c | 130 +++++++++++++++++++++++++++---------------= ---- 3 files changed, 80 insertions(+), 54 deletions(-) diff --git a/include/elf.h b/include/elf.h index cd51434877..e8a515ce3d 100644 --- a/include/elf.h +++ b/include/elf.h @@ -942,8 +942,9 @@ typedef struct { #define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ #define R_390_TLS_TPOFF 56 /* Negate offset in static TLS block. */ +#define R_390_20 57 /* Keep this the last entry. */ -#define R_390_NUM 57 +#define R_390_NUM 58 =20 /* x86-64 relocation types */ #define R_X86_64_NONE 0 /* No reloc */ diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 8c5a30ccf8..18a0efac3e 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -156,5 +156,6 @@ static inline void tb_target_set_jmp_target(uintptr_t t= c_ptr, #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif +#define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 59c0da0922..29b77ff67f 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -29,6 +29,7 @@ #error "unsupported code generation mode" #endif =20 +#include "tcg-pool.inc.c" #include "elf.h" =20 /* ??? The translation blocks produced by TCG are generally small enough to @@ -361,6 +362,7 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, intptr_t value, intptr_t addend) { intptr_t pcrel2; + uint32_t old; =20 value +=3D addend; pcrel2 =3D (tcg_insn_unit *)value - code_ptr; @@ -374,6 +376,12 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int t= ype, assert(pcrel2 =3D=3D (int32_t)pcrel2); tcg_patch32(code_ptr, pcrel2); break; + case R_390_20: + assert(value =3D=3D sextract64(value, 0, 20)); + old =3D *(uint32_t *)code_ptr & 0xf00000ff; + old |=3D ((value & 0xfff) << 16) | ((value & 0xff000) >> 4); + tcg_patch32(code_ptr, old); + break; default: g_assert_not_reached(); } @@ -562,14 +570,16 @@ static void tcg_out_mov(TCGContext *s, TCGType type, = TCGReg dst, TCGReg src) } } =20 -/* load a register with an immediate value */ -static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long sval, bool in_prologue) -{ - static const S390Opcode lli_insns[4] =3D { - RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH - }; +static const S390Opcode lli_insns[4] =3D { + RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH +}; +static const S390Opcode ii_insns[4] =3D { + RI_IILL, RI_IILH, RI_IIHL, RI_IIHH +}; =20 +static bool maybe_out_small_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long sval) +{ tcg_target_ulong uval =3D sval; int i; =20 @@ -581,17 +591,37 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, /* Try all 32-bit insns that can load it in one go. */ if (sval >=3D -0x8000 && sval < 0x8000) { tcg_out_insn(s, RI, LGHI, ret, sval); - return; + return true; } =20 for (i =3D 0; i < 4; i++) { tcg_target_long mask =3D 0xffffull << i*16; if ((uval & mask) =3D=3D uval) { tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16); - return; + return true; } } =20 + return false; +} + +/* load a register with an immediate value */ +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long sval, bool in_prologue) +{ + tcg_target_ulong uval; + + /* Try all 32-bit insns that can load it in one go. */ + if (maybe_out_small_movi(s, type, ret, sval)) { + return; + } + + uval =3D sval; + if (type =3D=3D TCG_TYPE_I32) { + uval =3D (uint32_t)sval; + sval =3D (int32_t)sval; + } + /* Try all 48-bit insns that can load it in one go. */ if (s390_facilities & FACILITY_EXT_IMM) { if (sval =3D=3D (int32_t)sval) { @@ -603,7 +633,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, return; } if ((uval & 0xffffffff) =3D=3D 0) { - tcg_out_insn(s, RIL, LLIHF, ret, uval >> 31 >> 1); + tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32); return; } } @@ -626,55 +656,44 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, } } =20 - /* If extended immediates are not present, then we may have to issue - several instructions to load the low 32 bits. */ - if (!(s390_facilities & FACILITY_EXT_IMM)) { - /* A 32-bit unsigned value can be loaded in 2 insns. And given - that the lli_insns loop above did not succeed, we know that - both insns are required. */ - if (uval <=3D 0xffffffff) { - tcg_out_insn(s, RI, LLILL, ret, uval); - tcg_out_insn(s, RI, IILH, ret, uval >> 16); - return; - } + /* A 32-bit unsigned value can be loaded in 2 insns. And given + that LLILL, LLIHL, LLILF above did not succeed, we know that + both insns are required. */ + if (uval <=3D 0xffffffff) { + tcg_out_insn(s, RI, LLILL, ret, uval); + tcg_out_insn(s, RI, IILH, ret, uval >> 16); + return; + } =20 - /* If all high bits are set, the value can be loaded in 2 or 3 ins= ns. - We first want to make sure that all the high bits get set. With - luck the low 16-bits can be considered negative to perform that= for - free, otherwise we load an explicit -1. */ - if (sval >> 31 >> 1 =3D=3D -1) { - if (uval & 0x8000) { - tcg_out_insn(s, RI, LGHI, ret, uval); - } else { - tcg_out_insn(s, RI, LGHI, ret, -1); - tcg_out_insn(s, RI, IILL, ret, uval); - } - tcg_out_insn(s, RI, IILH, ret, uval >> 16); - return; + /* When allowed, stuff it in the constant pool. */ + if (!in_prologue) { + if (USE_REG_TB) { + tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, sval, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); + } else { + tcg_out_insn(s, RIL, LGRL, ret, 0); + new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); } + return; } =20 - /* If we get here, both the high and low parts have non-zero bits. */ - - /* Recurse to load the lower 32-bits. */ - tcg_out_movi(s, TCG_TYPE_I64, ret, uval & 0xffffffff); - - /* Insert data into the high 32-bits. */ - uval =3D uval >> 31 >> 1; + /* What's left is for the prologue, loading GUEST_BASE, and because + it failed to match above, is known to be a full 64-bit quantity. + We could try more than this, but it probably wouldn't pay off. */ if (s390_facilities & FACILITY_EXT_IMM) { - if (uval < 0x10000) { - tcg_out_insn(s, RI, IIHL, ret, uval); - } else if ((uval & 0xffff) =3D=3D 0) { - tcg_out_insn(s, RI, IIHH, ret, uval >> 16); - } else { - tcg_out_insn(s, RIL, IIHF, ret, uval); - } + tcg_out_insn(s, RIL, LLILF, ret, uval); + tcg_out_insn(s, RIL, IIHF, ret, uval >> 32); } else { - if (uval & 0xffff) { - tcg_out_insn(s, RI, IIHL, ret, uval); - } - if (uval & 0xffff0000) { - tcg_out_insn(s, RI, IIHH, ret, uval >> 16); + const S390Opcode *insns =3D lli_insns; + int i; + + for (i =3D 0; i < 4; i++) { + uint16_t part =3D uval >> (16 * i); + if (part) { + tcg_out_insn_RI(s, insns[i], ret, part); + insns =3D ii_insns; + } } } } @@ -2573,6 +2592,11 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); } =20 +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0x07, count * sizeof(tcg_insn_unit)); +} + typedef struct { DebugFrameHeader h; uint8_t fde_def_cfa[4]; --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501825750461107.22426053758568; Thu, 3 Aug 2017 22:49:10 -0700 (PDT) Received: from localhost ([::1]:36673 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVTx-0007S0-1H for importer@patchew.org; Fri, 04 Aug 2017 01:49:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59570) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPa-0003uM-CT for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPY-0003Fl-NA for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:38 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:33045) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPY-0003Db-F0 for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:36 -0400 Received: by mail-pg0-x241.google.com with SMTP id u185so853471pgb.0 for ; Thu, 03 Aug 2017 22:44:36 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.34 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=HK/tKI+UX+583UXkdChp1m60YTPflzL8govNBUO7npA=; b=f1z8bo5Dx2BSfKK3o6QL+QdNk+/NmY5W+IAezK13pG+t5sXYzAD83EmGcUttl/8AVF c3319+a57lmWpfIqq9AloTv5nr3LWgGuGikmxYb7epJ0QSTgXQ92zL7xPWgCpXCXzK02 FoZJDc2zhjPnLEFRZCxfVYQtur2hR0MA+X+zQpWS3YYFT0PMStjLYCus1CG4RLg7Sc7c ct3FjuRLMYWDAM9/UN+o18IQsuz6UOwz5VnCpnM9gwbN4McaoNE7g6de0vTAivKl71nd VAQzUJd7EUqJE+wiFG5IF2gaFXPA/gruDlIDCYmgCyDDbZo91ewzECQICw54sCwrEk/v P70Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=HK/tKI+UX+583UXkdChp1m60YTPflzL8govNBUO7npA=; b=OsyzM4CS/YSIEwmxvKmFNU9j8keGdJIigJhWL9jZs0A8KHPLlZjSYTA61/hOyWOBpk v0jTAWMln4jt19LsUNnZk9OW5f/lv98Oksezah3EskfSQs2SbR7bdB8UcN5xVg9ykJmt zmhY/FtrMozQ5CoaY46RveulKLVKQH9o6X3IzrSIIYUfpw0l7sarv6xl/+I0lbYr8yNm KSyQTtN4hyyojhk3iSe5YagHtrCKmLsHFGIeXtA+QXp1s7DM3Zo7evYhm1xaDw83giWp bYi4aYxxXkSilbi5Roza+mDdnpK8sBdc2zXVw98G9qMb1dfMMWgdH1FUpv6HwoHmfjlr CqHw== X-Gm-Message-State: AIVw111vW6fatOmi1nLGNLldMsYiMhdXxAxskW833uVAjUkI7sRI6rs4 Rog6C4AZUtFrNfbuUIQ= X-Received: by 10.84.231.197 with SMTP id g5mr1402260pln.152.1501825475242; Thu, 03 Aug 2017 22:44:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:11 -0700 Message-Id: <20170804054426.10590-9-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH for-2.11 08/23] tcg/s390: Use constant pool for andi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 29b77ff67f..4be57c5765 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -224,6 +224,7 @@ typedef enum S390Opcode { RXY_LRVG =3D 0xe30f, RXY_LRVH =3D 0xe31f, RXY_LY =3D 0xe358, + RXY_NG =3D 0xe380, RXY_STCY =3D 0xe372, RXY_STG =3D 0xe324, RXY_STHY =3D 0xe370, @@ -985,8 +986,17 @@ static void tgen_andi(TCGContext *s, TCGType type, TCG= Reg dest, uint64_t val) return; } =20 - /* Fall back to loading the constant. */ - tcg_out_movi(s, type, TCG_TMP0, val); + /* Use the constant pool if USE_REG_TB, but not for small constants. = */ + if (USE_REG_TB) { + if (!maybe_out_small_movi(s, type, TCG_TMP0, val)) { + tcg_out_insn(s, RXY, NG, dest, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, val & valid, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); + return; + } + } else { + tcg_out_movi(s, type, TCG_TMP0, val); + } if (type =3D=3D TCG_TYPE_I32) { tcg_out_insn(s, RR, NR, dest, TCG_TMP0); } else { @@ -2341,6 +2351,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &r_r_ri; case INDEX_op_sub_i32: case INDEX_op_sub_i64: + case INDEX_op_and_i32: + case INDEX_op_and_i64: return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); =20 case INDEX_op_mul_i32: @@ -2375,10 +2387,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_= 0_rM) : &r_0_r); =20 - case INDEX_op_and_i32: - case INDEX_op_and_i64: - return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); - case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501825597861682.779752534038; Thu, 3 Aug 2017 22:46:37 -0700 (PDT) Received: from localhost ([::1]:36665 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVRU-0005JB-HY for importer@patchew.org; Fri, 04 Aug 2017 01:46:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59680) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPd-0003xp-Kq for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPa-0003Iz-8k for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:41 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:38631) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPZ-0003Gc-Ls for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:38 -0400 Received: by mail-pf0-x243.google.com with SMTP id h75so859598pfh.5 for ; Thu, 03 Aug 2017 22:44:37 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.35 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=czNlY0dMj/Ru6QHc9HjMJ0axAnNQ21zOfbjIjGszYgA=; b=JBLkyKJiXWC8vpxSp8R/Nkv0xxDl6WtWVWXkATMOrOfQGV09EcmOTpFDebfSZDSO7+ 6fkzFlRcWMVMgW+JbKLZXMcEtUmXNEmMNNa7CGoCpd/5HD/aX9JqShU35cHHl7rLPz5M 1XBBgTdDmbHaLgEmCYqclz7QEwY+wMpE3HP6+pnmAS5WtlrulQSwTlN+lj+M+59Kf/Qu swhube8Tr3Y+XY0yRk9OZVNvOvYuJprpxLoDoyJ+2a5fYHdr0uzjGaE8h+lt1hsnL6lj XTyEaYtExABqXcp8lSu30+taFP10hlg9L2u/TyDUZsDtP2vIyFaxC71KoRcf5tB0zCgd O7aA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=czNlY0dMj/Ru6QHc9HjMJ0axAnNQ21zOfbjIjGszYgA=; b=Ha9WdNiMV+82mSnTaifGEFmk74UGYBorYZg/rXvw3a1I/vTpfXBw+SEu0hyWk16CqJ 8BLDszZOF1MpJAVN0TuvPiKDH3qkInOVfb0S4qagYawWrVyZNgoK81wzVhaC4CHNSvMa CRpbTySuhbJwt8AH7jPbSSwdZFDYn05CNjFICN0E4raVE6bNLDlFxZCyYgpLfTSlmQqI 6ojV7PWhqpfP6b+AJq/6zY+ajaTz/U4nwyz7XsxGusJAP9LizH36kgEkeM0vNRMwRHLx 6Lv1DyhGdXR9ZL7NApgloEKLL1HIisLuCBq61VhA3MFdriABcpGRIXZ3cbWjndjmX31e zXKA== X-Gm-Message-State: AIVw110AtNEpphfUQ+LDhkYATJFsfi/4aOUJ9ChCG2Ql/rYFX5iNxB4J 21N3jSoeAot9CBACoYE= X-Received: by 10.84.139.40 with SMTP id 37mr1422332plq.153.1501825476357; Thu, 03 Aug 2017 22:44:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:12 -0700 Message-Id: <20170804054426.10590-10-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH for-2.11 09/23] tcg/s390: Use constant pool for ori X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 74 ++++++++++++++++++++++---------------------= ---- 1 file changed, 34 insertions(+), 40 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 4be57c5765..83fac71c31 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -225,6 +225,7 @@ typedef enum S390Opcode { RXY_LRVH =3D 0xe31f, RXY_LY =3D 0xe358, RXY_NG =3D 0xe380, + RXY_OG =3D 0xe381, RXY_STCY =3D 0xe372, RXY_STG =3D 0xe324, RXY_STHY =3D 0xe370, @@ -1004,55 +1005,60 @@ static void tgen_andi(TCGContext *s, TCGType type, = TCGReg dest, uint64_t val) } } =20 -static void tgen64_ori(TCGContext *s, TCGReg dest, tcg_target_ulong val) +static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t va= l) { static const S390Opcode oi_insns[4] =3D { RI_OILL, RI_OILH, RI_OIHL, RI_OIHH }; - static const S390Opcode nif_insns[2] =3D { + static const S390Opcode oif_insns[2] =3D { RIL_OILF, RIL_OIHF }; =20 int i; =20 /* Look for no-op. */ - if (val =3D=3D 0) { + if (unlikely(val =3D=3D 0)) { return; } =20 - if (s390_facilities & FACILITY_EXT_IMM) { - /* Try all 32-bit insns that can perform it in one go. */ - for (i =3D 0; i < 4; i++) { - tcg_target_ulong mask =3D (0xffffull << i*16); - if ((val & mask) !=3D 0 && (val & ~mask) =3D=3D 0) { - tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16); - return; - } + /* Try all 32-bit insns that can perform it in one go. */ + for (i =3D 0; i < 4; i++) { + tcg_target_ulong mask =3D (0xffffull << i*16); + if ((val & mask) !=3D 0 && (val & ~mask) =3D=3D 0) { + tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16); + return; } + } =20 - /* Try all 48-bit insns that can perform it in one go. */ + /* Try all 48-bit insns that can perform it in one go. */ + if (s390_facilities & FACILITY_EXT_IMM) { for (i =3D 0; i < 2; i++) { tcg_target_ulong mask =3D (0xffffffffull << i*32); if ((val & mask) !=3D 0 && (val & ~mask) =3D=3D 0) { - tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32); + tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32); return; } } + } =20 + /* Use the constant pool if USE_REG_TB, but not for small constants. = */ + if (maybe_out_small_movi(s, type, TCG_TMP0, val)) { + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_insn(s, RR, OR, dest, TCG_TMP0); + } else { + tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0); + } + } else if (USE_REG_TB) { + tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, val, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); + } else { /* Perform the OR via sequential modifications to the high and low parts. Do this via recursion to handle 16-bit vs 32-bit masks in each half. */ - tgen64_ori(s, dest, val & 0x00000000ffffffffull); - tgen64_ori(s, dest, val & 0xffffffff00000000ull); - } else { - /* With no extended-immediate facility, we don't need to be so - clever. Just iterate over the insns and mask in the constant. = */ - for (i =3D 0; i < 4; i++) { - tcg_target_ulong mask =3D (0xffffull << i*16); - if ((val & mask) !=3D 0) { - tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16); - } - } + tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); + tgen_ori(s, type, dest, val & 0x00000000ffffffffull); + tgen_ori(s, type, dest, val & 0xffffffff00000000ull); } } =20 @@ -1872,7 +1878,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tgen64_ori(s, a0, a2); + tgen_ori(s, TCG_TYPE_I32, a0, a2); } else if (a0 =3D=3D a1) { tcg_out_insn(s, RR, OR, a0, a2); } else { @@ -2104,7 +2110,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen64_ori(s, a0, a2); + tgen_ori(s, TCG_TYPE_I64, a0, a2); } else if (a0 =3D=3D a1) { tcg_out_insn(s, RRE, OGR, a0, a2); } else { @@ -2312,7 +2318,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; static const TCGTargetOpDef r_0_rJ =3D { .args_ct_str =3D { "r", "0", = "rJ" } }; - static const TCGTargetOpDef r_0_rN =3D { .args_ct_str =3D { "r", "0", = "rN" } }; static const TCGTargetOpDef r_0_rM =3D { .args_ct_str =3D { "r", "0", = "rM" } }; static const TCGTargetOpDef a2_r =3D { .args_ct_str =3D { "r", "r", "0", "1", "r", "r" } }; @@ -2353,6 +2358,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_sub_i64: case INDEX_op_and_i32: case INDEX_op_and_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); =20 case INDEX_op_mul_i32: @@ -2363,19 +2370,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_mul_i64: return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_r= I); =20 - case INDEX_op_or_i32: - /* The use of [iNM] constraints are optimization only, since a full - 64-bit immediate OR can always be performed with 4 sequential - OI[LH][LH] instructions. By rejecting certain negative ranges, - the immediate load plus the reg-reg OR is smaller. */ - return (s390_facilities & FACILITY_EXT_IMM - ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_= 0_ri) - : &r_0_rN); - case INDEX_op_or_i64: - return (s390_facilities & FACILITY_EXT_IMM - ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_= 0_rM) - : &r_0_rN); - case INDEX_op_xor_i32: /* Without EXT_IMM, no immediates are supported. Otherwise, rejecting certain negative ranges leads to smaller code. */ --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501825910149810.7513762138224; Thu, 3 Aug 2017 22:51:50 -0700 (PDT) Received: from localhost ([::1]:36686 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVWW-0001OD-Mg for importer@patchew.org; Fri, 04 Aug 2017 01:51:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59681) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPd-0003xq-Ku for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPa-0003Ko-UF for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:41 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:36075) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPa-0003Ik-Kp for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:38 -0400 Received: by mail-pf0-x243.google.com with SMTP id t83so862588pfj.3 for ; Thu, 03 Aug 2017 22:44:38 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.36 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=xsoHdfR4fMdVM/BhOIjcoscDh+x3x/upgxkbcj2gXv8=; b=n4ZTzdqXZ9B3GF0aYhcI3XgFELCY2+EJtJwQGeW8LvsvrnMkCl7rn6ml/dwXg1opg6 gXOoQA32x7DEF36CPx0qbxQW82DHblyS8CqubSNtApsBFUaiLYp5nA1Nqsfnd4hSAiR+ qucx+OlzjBBrTCWBOBXfgy7VWnin9ykIE4RrD/L1liaEhktQ5xVn25KiLCiC2wZLTXwf hl5vusola9ps/VurrGpGFZXUftiEglfBN0AYqkW6FX7MdyP5BlIkiCFqiiS5aZIUNKAA NEtXGZgLSrqaf02UuYdB6JHtxyZGQPyZXEdd++MuiAnexe/pvm0oqIXPQbc3EnfLPhJh CqmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=xsoHdfR4fMdVM/BhOIjcoscDh+x3x/upgxkbcj2gXv8=; b=qE5M64vkVka/u2lW9pOGYKFKRxmirpbqGz26CMPeNHksuVFdToR+GfT3w1+FcH3xFX wDq02gH54XpvP+QcxfzmWF4+LZGmWesKrOCJMOdj8ffIfs+khTRWpz7P9j1jXCnx1yJD Ze8cHLWCaJnhCbI4GKpJwIe2oKQ/meHuoXfA/q08jaOeE01Vqsq+A/OVTFUUxeOll7TP PkWIjua0TZ1vJMUzSXLdeogVAR89yqiqN6mU4awEnxc7EdT7XYEQ3VYW1B+6y/FFGVd7 Psbbjv3TvVNqqaKfHljHybT7HkKfjjNufYjV6ziY5Vd1me82xc3X+B9WMt6wIK0wxSQ4 f4DQ== X-Gm-Message-State: AIVw111DrhQcjM5m3bvZ0EsMwRH4gq3rz98oUKPfAEs5xv1QecvuGyAx +Fs3aiGlrZN8K/WLK2Q= X-Received: by 10.84.217.142 with SMTP id p14mr1442819pli.22.1501825477306; Thu, 03 Aug 2017 22:44:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:13 -0700 Message-Id: <20170804054426.10590-11-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH for-2.11 10/23] tcg/s390: Use constant pool for xori X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 77 ++++++++++++++++++++++++-------------------= ---- 1 file changed, 40 insertions(+), 37 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 83fac71c31..b0b34fa5ab 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -39,11 +39,9 @@ =20 #define TCG_CT_CONST_S16 0x100 #define TCG_CT_CONST_S32 0x200 -#define TCG_CT_CONST_NN16 0x400 -#define TCG_CT_CONST_NN32 0x800 -#define TCG_CT_CONST_U31 0x1000 -#define TCG_CT_CONST_S33 0x2000 -#define TCG_CT_CONST_ZERO 0x4000 +#define TCG_CT_CONST_U31 0x400 +#define TCG_CT_CONST_S33 0x800 +#define TCG_CT_CONST_ZERO 0x1000 =20 /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ @@ -234,6 +232,7 @@ typedef enum S390Opcode { RXY_STRVG =3D 0xe32f, RXY_STRVH =3D 0xe33f, RXY_STY =3D 0xe350, + RXY_XG =3D 0xe382, =20 RX_A =3D 0x5a, RX_C =3D 0x59, @@ -424,12 +423,6 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, case 'J': ct->ct |=3D TCG_CT_CONST_S32; break; - case 'N': - ct->ct |=3D TCG_CT_CONST_NN16; - break; - case 'M': - ct->ct |=3D TCG_CT_CONST_NN32; - break; case 'C': /* ??? We have no insight here into whether the comparison is signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit @@ -474,10 +467,6 @@ static int tcg_target_const_match(tcg_target_long val,= TCGType type, return val =3D=3D (int32_t)val; } else if (ct & TCG_CT_CONST_S33) { return val >=3D -0xffffffffll && val <=3D 0xffffffffll; - } else if (ct & TCG_CT_CONST_NN16) { - return !(val < 0 && val =3D=3D (int16_t)val); - } else if (ct & TCG_CT_CONST_NN32) { - return !(val < 0 && val =3D=3D (int32_t)val); } else if (ct & TCG_CT_CONST_U31) { return val >=3D 0 && val <=3D 0x7fffffff; } else if (ct & TCG_CT_CONST_ZERO) { @@ -1062,14 +1051,40 @@ static void tgen_ori(TCGContext *s, TCGType type, T= CGReg dest, uint64_t val) } } =20 -static void tgen64_xori(TCGContext *s, TCGReg dest, tcg_target_ulong val) +static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t v= al) { - /* Perform the xor by parts. */ - if (val & 0xffffffff) { - tcg_out_insn(s, RIL, XILF, dest, val); + /* Try all 48-bit insns that can perform it in one go. */ + if (s390_facilities & FACILITY_EXT_IMM) { + if ((val & 0xffffffff00000000ull) =3D=3D 0) { + tcg_out_insn(s, RIL, XILF, dest, val); + return; + } + if ((val & 0x00000000ffffffffull) =3D=3D 0) { + tcg_out_insn(s, RIL, XIHF, dest, val >> 32); + return; + } } - if (val > 0xffffffff) { - tcg_out_insn(s, RIL, XIHF, dest, val >> 31 >> 1); + + /* Use the constant pool if USE_REG_TB, but not for small constants. = */ + if (maybe_out_small_movi(s, type, TCG_TMP0, val)) { + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_insn(s, RR, XR, dest, TCG_TMP0); + } else { + tcg_out_insn(s, RRE, XGR, dest, TCG_TMP0); + } + } else if (USE_REG_TB) { + tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, val, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); + } else { + /* Perform the xor by parts. */ + tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); + if (val & 0xffffffff) { + tcg_out_insn(s, RIL, XILF, dest, val); + } + if (val > 0xffffffff) { + tcg_out_insn(s, RIL, XIHF, dest, val >> 32); + } } } =20 @@ -1889,7 +1904,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tgen64_xori(s, a0, a2); + tgen_xori(s, TCG_TYPE_I32, a0, a2); } else if (a0 =3D=3D a1) { tcg_out_insn(s, RR, XR, args[0], args[2]); } else { @@ -2121,7 +2136,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen64_xori(s, a0, a2); + tgen_xori(s, TCG_TYPE_I64, a0, a2); } else if (a0 =3D=3D a1) { tcg_out_insn(s, RRE, XGR, a0, a2); } else { @@ -2313,12 +2328,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) static const TCGTargetOpDef r_rC =3D { .args_ct_str =3D { "r", "rC" } = }; static const TCGTargetOpDef r_rZ =3D { .args_ct_str =3D { "r", "rZ" } = }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; - static const TCGTargetOpDef r_r_rM =3D { .args_ct_str =3D { "r", "r", = "rM" } }; - static const TCGTargetOpDef r_0_r =3D { .args_ct_str =3D { "r", "0", "= r" } }; static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; static const TCGTargetOpDef r_0_rJ =3D { .args_ct_str =3D { "r", "0", = "rJ" } }; - static const TCGTargetOpDef r_0_rM =3D { .args_ct_str =3D { "r", "0", = "rM" } }; static const TCGTargetOpDef a2_r =3D { .args_ct_str =3D { "r", "r", "0", "1", "r", "r" } }; static const TCGTargetOpDef a2_ri @@ -2360,6 +2372,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) case INDEX_op_and_i64: case INDEX_op_or_i32: case INDEX_op_or_i64: + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); =20 case INDEX_op_mul_i32: @@ -2370,17 +2384,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_mul_i64: return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_r= I); =20 - case INDEX_op_xor_i32: - /* Without EXT_IMM, no immediates are supported. Otherwise, - rejecting certain negative ranges leads to smaller code. */ - return (s390_facilities & FACILITY_EXT_IMM - ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_= 0_ri) - : &r_0_r); - case INDEX_op_xor_i64: - return (s390_facilities & FACILITY_EXT_IMM - ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_= 0_rM) - : &r_0_r); - case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501825910310529.0344264650746; Thu, 3 Aug 2017 22:51:50 -0700 (PDT) Received: from localhost ([::1]:36685 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVWU-0001MX-SS for importer@patchew.org; Fri, 04 Aug 2017 01:51:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59685) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPd-0003y3-Nt for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPb-0003N8-RT for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:41 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:37852) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPb-0003LG-JB for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:39 -0400 Received: by mail-pf0-x244.google.com with SMTP id p13so861893pfd.4 for ; Thu, 03 Aug 2017 22:44:39 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=U3kSwZvMtpzodX5c4I3yFpcMrgZs7mUzSqWjIYEWjkc=; b=k9US7WcBsCN5D26NtCj+PiOVsK7V12h7O5qpK2ipBh0p34ArYsYKhCBioJrGMcFEQ9 6oMvVCMB4Yb8aAijhTxiNBrsZxNIJfEHWNqdxfVACePdkQqz/EvahtUFjpmN1W5RLP7l /XtMTyu2m+2EbjP+Z6Ynv5nflImpob1VhdcttI2lymnyvwoGgN2naeHNTeGSWtHMjySi CTRQ9s71o+9DMwmMlAU4txu9jlcBWFQdQXRX+guDc/j+FSAXaNkET6bwZivbcKvv/ymf d2zHGHlF8JCiOBxFWiTiIL5j8Cp9k4CKt1PJ3HZ3St9pgY84fEex2AuILm/A4QkSr6Uy Hi6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=U3kSwZvMtpzodX5c4I3yFpcMrgZs7mUzSqWjIYEWjkc=; b=DqgAqb4jYzb08Zqx0yiY+GIEdWH8dV1RpGq7N0d5Gmgn3RNuwTTohX5AfJ4TQ3KD5O r9HRXE3jJYcXT57Xh7974Jf1pBAnryw7w9XQBjZ3oIaTvEDIFZADBx4/J76UKHfOnDWF zg4bmke2RoMJ8E6X1/rokd1fySAoHUxelBdZ2jOY+JVF3sk8MmZ5jtqd3FlAANqNtNVz QIMgOTORFdozdWGUSq+XfgtMF21FTGsgBpqy0JahpUspXvO9vtgG/cLAT+RTKEyLIQjI PB1XxWidOpQbwb/ujdXJ7hyHhYrZWIkhA3S8nCRZg2qdIxxy6MJv2wrKaozN2YsCXDqy DtXA== X-Gm-Message-State: AIVw110JjnzE8oIhr7EQ8W+DYEg5ageGj3EviMgkN5zLDu8zNMm+GYdn rFkOpTUA39YaArgbnfg= X-Received: by 10.84.217.216 with SMTP id d24mr1448730plj.144.1501825478326; Thu, 03 Aug 2017 22:44:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:14 -0700 Message-Id: <20170804054426.10590-12-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH for-2.11 11/23] tcg/s390: Use constant pool for cmpi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Also use CHI/CGHI for 16-bit signed constants. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 136 +++++++++++++++++++++++-------------------= ---- 1 file changed, 67 insertions(+), 69 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index b0b34fa5ab..e7ab8e4df3 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -39,9 +39,8 @@ =20 #define TCG_CT_CONST_S16 0x100 #define TCG_CT_CONST_S32 0x200 -#define TCG_CT_CONST_U31 0x400 -#define TCG_CT_CONST_S33 0x800 -#define TCG_CT_CONST_ZERO 0x1000 +#define TCG_CT_CONST_S33 0x400 +#define TCG_CT_CONST_ZERO 0x800 =20 /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ @@ -75,6 +74,10 @@ typedef enum S390Opcode { RIL_CGFI =3D 0xc20c, RIL_CLFI =3D 0xc20f, RIL_CLGFI =3D 0xc20e, + RIL_CLRL =3D 0xc60f, + RIL_CLGRL =3D 0xc60a, + RIL_CRL =3D 0xc60d, + RIL_CGRL =3D 0xc608, RIL_IIHF =3D 0xc008, RIL_IILF =3D 0xc009, RIL_LARL =3D 0xc000, @@ -97,6 +100,8 @@ typedef enum S390Opcode { RI_AGHI =3D 0xa70b, RI_AHI =3D 0xa70a, RI_BRC =3D 0xa704, + RI_CHI =3D 0xa70e, + RI_CGHI =3D 0xa70f, RI_IIHH =3D 0xa500, RI_IIHL =3D 0xa501, RI_IILH =3D 0xa502, @@ -206,6 +211,8 @@ typedef enum S390Opcode { RXY_AG =3D 0xe308, RXY_AY =3D 0xe35a, RXY_CG =3D 0xe320, + RXY_CLG =3D 0xe321, + RXY_CLY =3D 0xe355, RXY_CY =3D 0xe359, RXY_LAY =3D 0xe371, RXY_LB =3D 0xe376, @@ -423,20 +430,6 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, case 'J': ct->ct |=3D TCG_CT_CONST_S32; break; - case 'C': - /* ??? We have no insight here into whether the comparison is - signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit - signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses - a 32-bit unsigned immediate. If we were to use the (semi) - obvious "val =3D=3D (int32_t)val" we would be enabling unsigned - comparisons vs very large numbers. The only solution is to - take the intersection of the ranges. */ - /* ??? Another possible solution is to simply lie and allow all - constants here and force the out-of-range values into a temp - register in tgen_cmp when we have knowledge of the actual - comparison code in use. */ - ct->ct |=3D TCG_CT_CONST_U31; - break; case 'Z': ct->ct |=3D TCG_CT_CONST_ZERO; break; @@ -467,8 +460,6 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, return val =3D=3D (int32_t)val; } else if (ct & TCG_CT_CONST_S33) { return val >=3D -0xffffffffll && val <=3D 0xffffffffll; - } else if (ct & TCG_CT_CONST_U31) { - return val >=3D 0 && val <=3D 0x7fffffff; } else if (ct & TCG_CT_CONST_ZERO) { return val =3D=3D 0; } @@ -1092,6 +1083,8 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGC= ond c, TCGReg r1, TCGArg c2, bool c2const, bool need_carry) { bool is_unsigned =3D is_unsigned_cond(c); + S390Opcode op; + if (c2const) { if (c2 =3D=3D 0) { if (!(is_unsigned && need_carry)) { @@ -1102,44 +1095,67 @@ static int tgen_cmp(TCGContext *s, TCGType type, TC= GCond c, TCGReg r1, } return tcg_cond_to_ltr_cond[c]; } - /* If we only got here because of load-and-test, - and we couldn't use that, then we need to load - the constant into a register. */ - if (!(s390_facilities & FACILITY_EXT_IMM)) { - c2 =3D TCG_TMP0; - tcg_out_movi(s, type, c2, 0); - goto do_reg; - } } - if (is_unsigned) { - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RIL, CLFI, r1, c2); - } else { - tcg_out_insn(s, RIL, CLGFI, r1, c2); - } - } else { + + if (!is_unsigned && c2 =3D=3D (int16_t)c2) { + op =3D (type =3D=3D TCG_TYPE_I32 ? RI_CHI : RI_CGHI); + tcg_out_insn_RI(s, op, r1, c2); + goto exit; + } + + if (s390_facilities & FACILITY_EXT_IMM) { if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RIL, CFI, r1, c2); - } else { - tcg_out_insn(s, RIL, CGFI, r1, c2); + op =3D (is_unsigned ? RIL_CLFI : RIL_CFI); + tcg_out_insn_RIL(s, op, r1, c2); + goto exit; + } else if (c2 =3D=3D (is_unsigned ? (uint32_t)c2 : (int32_t)c2= )) { + op =3D (is_unsigned ? RIL_CLGFI : RIL_CGFI); + tcg_out_insn_RIL(s, op, r1, c2); + goto exit; } } - } else { - do_reg: - if (is_unsigned) { + + /* Use the constant pool, but not for small constants. */ + if (maybe_out_small_movi(s, type, TCG_TMP0, c2)) { + c2 =3D TCG_TMP0; + /* fall through to reg-reg */ + } else if (USE_REG_TB) { if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RR, CLR, r1, c2); + op =3D (is_unsigned ? RXY_CLY : RXY_CY); + tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, (uint32_t)c2, R_390_20, s->code_ptr - 2, + 4 - (intptr_t)s->code_gen_ptr); } else { - tcg_out_insn(s, RRE, CLGR, r1, c2); + op =3D (is_unsigned ? RXY_CLG : RXY_CG); + tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, c2, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); } + goto exit; } else { if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RR, CR, r1, c2); + op =3D (is_unsigned ? RIL_CLRL : RIL_CRL); + tcg_out_insn_RIL(s, op, r1, 0); + new_pool_label(s, (uint32_t)c2, R_390_PC32DBL, + s->code_ptr - 2, 2 + 4); } else { - tcg_out_insn(s, RRE, CGR, r1, c2); + op =3D (is_unsigned ? RIL_CLGRL : RIL_CGRL); + tcg_out_insn_RIL(s, op, r1, 0); + new_pool_label(s, c2, R_390_PC32DBL, s->code_ptr - 2, 2); } + goto exit; } } + + if (type =3D=3D TCG_TYPE_I32) { + op =3D (is_unsigned ? RR_CLR : RR_CR); + tcg_out_insn_RR(s, op, r1, c2); + } else { + op =3D (is_unsigned ? RRE_CLGR : RRE_CGR); + tcg_out_insn_RRE(s, op, r1, c2); + } + + exit: return tcg_cond_to_s390_cond[c]; } =20 @@ -2325,8 +2341,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; static const TCGTargetOpDef L_L =3D { .args_ct_str =3D { "L", "L" } }; static const TCGTargetOpDef r_ri =3D { .args_ct_str =3D { "r", "ri" } = }; - static const TCGTargetOpDef r_rC =3D { .args_ct_str =3D { "r", "rC" } = }; - static const TCGTargetOpDef r_rZ =3D { .args_ct_str =3D { "r", "rZ" } = }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; @@ -2401,10 +2415,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) return &r_r_ri; =20 case INDEX_op_brcond_i32: - /* Without EXT_IMM, only the LOAD AND TEST insn is available. */ - return (s390_facilities & FACILITY_EXT_IMM ? &r_ri : &r_rZ); case INDEX_op_brcond_i64: - return (s390_facilities & FACILITY_EXT_IMM ? &r_rC : &r_rZ); + return &r_ri; =20 case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -2430,6 +2442,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &r_r; =20 case INDEX_op_clz_i64: + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: return &r_r_ri; =20 case INDEX_op_qemu_ld_i32: @@ -2446,30 +2460,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) =3D { .args_ct_str =3D { "r", "rZ", "r" } }; return &dep; } - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - { - /* Without EXT_IMM, only the LOAD AND TEST insn is available. = */ - static const TCGTargetOpDef setc_z - =3D { .args_ct_str =3D { "r", "r", "rZ" } }; - static const TCGTargetOpDef setc_c - =3D { .args_ct_str =3D { "r", "r", "rC" } }; - return (s390_facilities & FACILITY_EXT_IMM ? &setc_c : &setc_z= ); - } case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: { - /* Without EXT_IMM, only the LOAD AND TEST insn is available. = */ - static const TCGTargetOpDef movc_z - =3D { .args_ct_str =3D { "r", "r", "rZ", "r", "0" } }; - static const TCGTargetOpDef movc_c - =3D { .args_ct_str =3D { "r", "r", "rC", "r", "0" } }; + static const TCGTargetOpDef movc + =3D { .args_ct_str =3D { "r", "r", "ri", "r", "0" } }; static const TCGTargetOpDef movc_l - =3D { .args_ct_str =3D { "r", "r", "rC", "rI", "0" } }; - return (s390_facilities & FACILITY_EXT_IMM - ? (s390_facilities & FACILITY_LOAD_ON_COND2 - ? &movc_l : &movc_c) - : &movc_z); + =3D { .args_ct_str =3D { "r", "r", "ri", "rI", "0" } }; + return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &= movc); } case INDEX_op_div2_i32: case INDEX_op_div2_i64: --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501826066819783.2377626604307; Thu, 3 Aug 2017 22:54:26 -0700 (PDT) Received: from localhost ([::1]:36695 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVZ3-000405-2J for importer@patchew.org; Fri, 04 Aug 2017 01:54:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59692) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPe-0003yO-Al for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPc-0003Pl-RX for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:42 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34288) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPc-0003O9-Lv for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:40 -0400 Received: by mail-pg0-x244.google.com with SMTP id y192so836729pgd.1 for ; Thu, 03 Aug 2017 22:44:40 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=vLeKdneB1QC0NshN929RWsqX3Q88g5E4JPnA7bVKopk=; b=GICkTc3fpxraf5jl2rnvnaseWW8JdVvVX2tWuC6/nQ3no7YwWVZtZGRdgTnmDQ6ahE 5FtSfeciCcFRm6JSBdIn4QqAx3K8CL7EgRbawo43Uhxke1u6rJSzo7BwzXDpQH663zLH vSvfnxSCfVNYe3HIzejHa3BLwJ0A2NWA9WhfuOpnnEcsdPAWLdGe8JEEqjAvmYV0CzcQ yIKO4bi+Eb0gHko7enGjnSNdb5wYcB1a646UrLVJLhA/e9nRXqb5Hu6iJ1527mqBngcC AgjpSzHc69ZRAgcH0t8QqA9Ot0lucodATw+GTaSX8726qL+QcXk8rbFZQAtYlKBjL/Dm pWDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=vLeKdneB1QC0NshN929RWsqX3Q88g5E4JPnA7bVKopk=; b=gEVyY926shueVxUtQYDh5d+GqDwjK0P5B9JT5TIr9B8kUFbRN8K1djc8eJCSNuYXxg OYJ+tD6mQkH8m+rk32GmLkrDXxJicZjglNzRzb1yAZWyMALAmxqxpKd9F5HKBeX7U1xh BWCnlBIcXPM23o1NQlVQAB+kmvqSkemhuCSTYm/nAc7GJWv013bfH/cjKWntkfQ7ohAC uG8OrpRmN4jooP3M7y6KCGR7JxTfRPdrKgL6nGk0Ab3myDd/si/fA5XzwQYLKQsQf5Jd EX71RV0EDFZmpkzZmxwfxD0wVc3xUodNKM+CsG0+Edf44ENI50M3N45BA2DAo50YWWOX X3ew== X-Gm-Message-State: AIVw113RV6gjFRPFLsLWxhCdEVd1gcvAV5VoXPULSKb2uYib3TaEhBsI cXnNlmyukuoXfUFes0M= X-Received: by 10.98.217.210 with SMTP id b79mr1193397pfl.297.1501825479375; Thu, 03 Aug 2017 22:44:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:15 -0700 Message-Id: <20170804054426.10590-13-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH for-2.11 12/23] tcg/aarch64: Use constant pool for movi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 + tcg/aarch64/tcg-target.inc.c | 62 +++++++++++++++++++++++-----------------= ---- 2 files changed, 33 insertions(+), 30 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 484cf6236c..e86c2684fb 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -123,5 +123,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif +#define TCG_TARGET_NEED_POOL_LABELS =20 #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index c7c751bafc..c2f3812214 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -10,6 +10,7 @@ * See the COPYING file in the top-level directory for details. */ =20 +#include "tcg-pool.inc.c" #include "qemu/bitops.h" =20 /* We're going to re-use TCGType in setting of the SF bit, which controls @@ -587,9 +588,11 @@ static void tcg_out_logicali(TCGContext *s, AArch64Ins= n insn, TCGType ext, static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, tcg_target_long value) { - int i, wantinv, shift; tcg_target_long svalue =3D value; tcg_target_long ivalue =3D ~value; + tcg_target_long t0, t1, t2; + int s0, s1; + AArch64Insn opc; =20 /* For 32-bit values, discard potential garbage in value. For 64-bit values within [2**31, 2**32-1], we can create smaller sequences by @@ -638,38 +641,29 @@ static void tcg_out_movi(TCGContext *s, TCGType type,= TCGReg rd, } } =20 - /* Would it take fewer insns to begin with MOVN? For the value and its - inverse, count the number of 16-bit lanes that are 0. */ - for (i =3D wantinv =3D 0; i < 64; i +=3D 16) { - tcg_target_long mask =3D 0xffffull << i; - wantinv -=3D ((value & mask) =3D=3D 0); - wantinv +=3D ((ivalue & mask) =3D=3D 0); - } - - if (wantinv <=3D 0) { - /* Find the lowest lane that is not 0x0000. */ - shift =3D ctz64(value) & (63 & -16); - tcg_out_insn(s, 3405, MOVZ, type, rd, value >> shift, shift); - /* Clear out the lane that we just set. */ - value &=3D ~(0xffffUL << shift); - /* Iterate until all non-zero lanes have been processed. */ - while (value) { - shift =3D ctz64(value) & (63 & -16); - tcg_out_insn(s, 3405, MOVK, type, rd, value >> shift, shift); - value &=3D ~(0xffffUL << shift); - } + /* Would it take fewer insns to begin with MOVN? */ + if (ctpop64(value) >=3D 32) { + t0 =3D ivalue; + opc =3D I3405_MOVN; } else { - /* Like above, but with the inverted value and MOVN to start. */ - shift =3D ctz64(ivalue) & (63 & -16); - tcg_out_insn(s, 3405, MOVN, type, rd, ivalue >> shift, shift); - ivalue &=3D ~(0xffffUL << shift); - while (ivalue) { - shift =3D ctz64(ivalue) & (63 & -16); - /* Provide MOVK with the non-inverted value. */ - tcg_out_insn(s, 3405, MOVK, type, rd, ~(ivalue >> shift), shif= t); - ivalue &=3D ~(0xffffUL << shift); + t0 =3D value; + opc =3D I3405_MOVZ; + } + s0 =3D ctz64(t0) & (63 & -16); + t1 =3D t0 & ~(0xffffUL << s0); + s1 =3D ctz64(t1) & (63 & -16); + t2 =3D t1 & ~(0xffffUL << s1); + if (t2 =3D=3D 0) { + tcg_out_insn_3405(s, opc, type, rd, t0 >> s0, s0); + if (t1 !=3D 0) { + tcg_out_insn(s, 3405, MOVK, type, rd, value >> s1, s1); } + return; } + + /* For more than 2 insns, dump it into the constant pool. */ + new_pool_label(s, value, R_AARCH64_CONDBR19, s->code_ptr, 0); + tcg_out_insn(s, 3305, LDR, 0, rd); } =20 /* Define something more legible for general use. */ @@ -2030,6 +2024,14 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_insn(s, 3207, RET, TCG_REG_LR); } =20 +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i =3D 0; i < count; ++i) { + p[i] =3D NOP; + } +} + typedef struct { DebugFrameHeader h; uint8_t fde_def_cfa[4]; --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501826397822258.0115405335215; Thu, 3 Aug 2017 22:59:57 -0700 (PDT) Received: from localhost ([::1]:36856 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVeO-0001Zv-AY for importer@patchew.org; Fri, 04 Aug 2017 01:59:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59759) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPg-00041C-FJ for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPe-0003Sx-7D for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:44 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:37856) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPd-0003Qz-Ru for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:42 -0400 Received: by mail-pf0-x243.google.com with SMTP id p13so861964pfd.4 for ; Thu, 03 Aug 2017 22:44:41 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. 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X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH for-2.11 13/23] tcg/sparc: Introduce TCG_REG_TB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.inc.c | 170 +++++++++++++++++++++++++++++++++++++----= ---- 1 file changed, 140 insertions(+), 30 deletions(-) diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index bb7f7e8906..7d73c25347 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -85,6 +85,9 @@ static const char * const tcg_target_reg_names[TCG_TARGET= _NB_REGS] =3D { # define TCG_GUEST_BASE_REG TCG_REG_I5 #endif =20 +#define TCG_REG_TB TCG_REG_I1 +#define USE_REG_TB (sizeof(void *) > 4) + static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_L0, TCG_REG_L1, @@ -249,6 +252,8 @@ static const int tcg_target_call_oarg_regs[] =3D { =20 #define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) =20 +#define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0) + #ifndef ASI_PRIMARY_LITTLE #define ASI_PRIMARY_LITTLE 0x88 #endif @@ -423,10 +428,11 @@ static inline void tcg_out_movi_imm13(TCGContext *s, = TCGReg ret, int32_t arg) tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); } =20 -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long arg, bool in_prologue) { tcg_target_long hi, lo =3D (int32_t)arg; + tcg_target_long test, lsb; =20 /* Make sure we test 32-bit constants for imm13 properly. */ if (type =3D=3D TCG_TYPE_I32) { @@ -455,6 +461,27 @@ static void tcg_out_movi(TCGContext *s, TCGType type, return; } =20 + /* A 21-bit constant, shifted. */ + lsb =3D ctz64(arg); + test =3D (tcg_target_long)arg >> lsb; + if (check_fit_tl(test, 13)) { + tcg_out_movi_imm13(s, ret, test); + tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); + return; + } else if (lsb > 10 && test =3D=3D extract64(test, 0, 21)) { + tcg_out_sethi(s, ret, test << 10); + tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); + return; + } + + if (USE_REG_TB && !in_prologue) { + intptr_t diff =3D arg - (uintptr_t)s->code_gen_ptr; + if (check_fit_ptr(diff, 13)) { + tcg_out_arithi(s, ret, TCG_REG_TB, diff, ARITH_ADD); + return; + } + } + /* A 64-bit constant decomposed into 2 32-bit pieces. */ if (check_fit_i32(lo, 13)) { hi =3D (arg - lo) >> 32; @@ -470,6 +497,12 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static inline void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + tcg_out_movi_int(s, type, ret, arg, false); +} + static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, TCGReg a2, int op) { @@ -512,6 +545,11 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType = type, TCGArg val, =20 static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg) { + intptr_t diff =3D arg - (uintptr_t)s->code_gen_ptr; + if (USE_REG_TB && check_fit_ptr(diff, 13)) { + tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff); + return; + } tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff); tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff); } @@ -543,7 +581,7 @@ static void tcg_out_div32(TCGContext *s, TCGReg rd, TCG= Reg rs1, =20 static inline void tcg_out_nop(TCGContext *s) { - tcg_out_sethi(s, TCG_REG_G0, 0); + tcg_out32(s, NOP); } =20 static const uint8_t tcg_cond_to_bcond[] =3D { @@ -812,7 +850,8 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg r= l, TCGReg rh, tcg_out_mov(s, TCG_TYPE_I64, rl, tmp); } =20 -static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest) +static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest, + bool in_prologue) { ptrdiff_t disp =3D tcg_pcrel_diff(s, dest); =20 @@ -820,14 +859,15 @@ static void tcg_out_call_nodelay(TCGContext *s, tcg_i= nsn_unit *dest) tcg_out32(s, CALL | (uint32_t)disp >> 2); } else { uintptr_t desti =3D (uintptr_t)dest; - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, desti & ~0xfff); + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1, + desti & ~0xfff, in_prologue); tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL); } } =20 static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) { - tcg_out_call_nodelay(s, dest); + tcg_out_call_nodelay(s, dest, false); tcg_out_nop(s); } =20 @@ -915,7 +955,7 @@ static void build_trampolines(TCGContext *s) /* Set the env operand. */ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); /* Tail call. */ - tcg_out_call_nodelay(s, qemu_ld_helpers[i]); + tcg_out_call_nodelay(s, qemu_ld_helpers[i], true); tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); } =20 @@ -964,7 +1004,7 @@ static void build_trampolines(TCGContext *s) /* Set the env operand. */ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0); /* Tail call. */ - tcg_out_call_nodelay(s, qemu_st_helpers[i]); + tcg_out_call_nodelay(s, qemu_st_helpers[i], true); tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra); } } @@ -992,11 +1032,17 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 #ifndef CONFIG_SOFTMMU if (guest_base !=3D 0) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, = true); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif =20 + /* We choose TCG_REG_TB such that no move is required. */ + if (USE_REG_TB) { + QEMU_BUILD_BUG_ON(TCG_REG_TB !=3D TCG_REG_I1); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); + } + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL); /* delay slot */ tcg_out_nop(s); @@ -1156,7 +1202,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, func =3D qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)]; } tcg_debug_assert(func !=3D NULL); - tcg_out_call_nodelay(s, func); + tcg_out_call_nodelay(s, func, false); /* delay slot */ tcg_out_movi(s, TCG_TYPE_I32, param, oi); =20 @@ -1235,7 +1281,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a, TCGReg addr, =20 func =3D qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)]; tcg_debug_assert(func !=3D NULL); - tcg_out_call_nodelay(s, func); + tcg_out_call_nodelay(s, func, false); /* delay slot */ tcg_out_movi(s, TCG_TYPE_I32, param, oi); =20 @@ -1269,30 +1315,67 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, if (check_fit_ptr(a0, 13)) { tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); tcg_out_movi_imm13(s, TCG_REG_O0, a0); - } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); - tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR= ); + break; + } else if (USE_REG_TB) { + intptr_t tb_diff =3D a0 - (uintptr_t)s->code_gen_ptr; + if (check_fit_ptr(tb_diff, 13)) { + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); + /* Note that TCG_REG_TB has been unwound to O1. */ + tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_A= DD); + break; + } } + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff); + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN); + tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR); break; case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset) { /* direct jump method */ - s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); - /* Make sure to preserve links during retranslation. */ - tcg_out32(s, CALL | (*s->code_ptr & ~INSN_OP(-1))); + if (USE_REG_TB) { + /* make sure the patch is 8-byte aligned. */ + if ((intptr_t)s->code_ptr & 4) { + tcg_out_nop(s); + } + s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); + tcg_out_sethi(s, TCG_REG_T1, 0); + tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR); + tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL); + tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH= _ADD); + } else { + s->tb_jmp_insn_offset[a0] =3D tcg_current_code_size(s); + tcg_out32(s, CALL); + tcg_out_nop(s); + } } else { /* indirect jump method */ - tcg_out_ld_ptr(s, TCG_REG_T1, + tcg_out_ld_ptr(s, TCG_REG_TB, (uintptr_t)(s->tb_jmp_target_addr + a0)); - tcg_out_arithi(s, TCG_REG_G0, TCG_REG_T1, 0, JMPL); + tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL); + tcg_out_nop(s); + } + s->tb_jmp_reset_offset[a0] =3D c =3D tcg_current_code_size(s); + + /* For the unlinked path of goto_tb, we need to reset + TCG_REG_TB to the beginning of this TB. */ + if (USE_REG_TB) { + c =3D -c; + if (check_fit_i32(c, 13)) { + tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c); + tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, + TCG_REG_T1, ARITH_ADD); + } } - tcg_out_nop(s); - s->tb_jmp_reset_offset[a0] =3D tcg_current_code_size(s); break; case INDEX_op_goto_ptr: tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL); - tcg_out_nop(s); + if (USE_REG_TB) { + tcg_out_arith(s, TCG_REG_TB, a0, TCG_REG_G0, ARITH_OR); + } else { + tcg_out_nop(s); + } break; case INDEX_op_br: tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0)); @@ -1709,13 +1792,40 @@ void tcg_register_jit(void *buf, size_t buf_size) void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t addr) { - uint32_t *ptr =3D (uint32_t *)jmp_addr; - uintptr_t disp =3D addr - jmp_addr; + intptr_t tb_disp =3D addr - tc_ptr; + intptr_t br_disp =3D addr - jmp_addr; + tcg_insn_unit i1, i2; + + /* We can reach the entire address space for ILP32. + For LP64, the code_gen_buffer can't be larger than 2GB. */ + tcg_debug_assert(tb_disp =3D=3D (int32_t)tb_disp); + tcg_debug_assert(br_disp =3D=3D (int32_t)br_disp); + + if (!USE_REG_TB) { + atomic_set((uint32_t *)jmp_addr, deposit32(CALL, 0, 30, br_disp >>= 2)); + flush_icache_range(jmp_addr, jmp_addr + 4); + return; + } =20 - /* We can reach the entire address space for 32-bit. For 64-bit - the code_gen_buffer can't be larger than 2GB. */ - tcg_debug_assert(disp =3D=3D (int32_t)disp); + /* This does not exercise the range of the branch, but we do + still need to be able to load the new value of TCG_REG_TB. + But this does still happen quite often. */ + if (check_fit_ptr(tb_disp, 13)) { + /* ba,pt %icc, addr */ + i1 =3D (INSN_OP(0) | INSN_OP2(1) | INSN_COND(COND_A) + | BPCC_ICC | BPCC_PT | INSN_OFF19(br_disp)); + i2 =3D (ARITH_ADD | INSN_RD(TCG_REG_TB) | INSN_RS1(TCG_REG_TB) + | INSN_IMM13(tb_disp)); + } else if (tb_disp >=3D 0) { + i1 =3D SETHI | INSN_RD(TCG_REG_T1) | ((tb_disp & 0xfffffc00) >> 10= ); + i2 =3D (ARITH_OR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1) + | INSN_IMM13(tb_disp & 0x3ff)); + } else { + i1 =3D SETHI | INSN_RD(TCG_REG_T1) | ((~tb_disp & 0xfffffc00) >> 1= 0); + i2 =3D (ARITH_XOR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1) + | INSN_IMM13((tb_disp & 0x3ff) | -0x400)); + } =20 - atomic_set(ptr, deposit32(CALL, 0, 30, disp >> 2)); - flush_icache_range(jmp_addr, jmp_addr + 4); + atomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1)); + flush_icache_range(jmp_addr, jmp_addr + 8); } --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501826217090127.81552721597404; Thu, 3 Aug 2017 22:56:57 -0700 (PDT) Received: from localhost ([::1]:36771 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVbT-0006l4-6V for importer@patchew.org; Fri, 04 Aug 2017 01:56:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59762) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPg-00041H-HT for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPf-0003V0-1t for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:44 -0400 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:38173) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPe-0003TH-Pe for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:42 -0400 Received: by mail-pg0-x241.google.com with SMTP id 123so811692pga.5 for ; Thu, 03 Aug 2017 22:44:42 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.40 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=mlsMk8PZS6npqfquBK8rK+xl8vG7eDKmHuDcvTYKP24=; b=WjbKTlsyrFoshNP7F1BqR0uk0Md4MbP+iCzRP3Agquq62i1AiWI6DKlEwWIDx0WXRp CFI60bJ5Kv2ayNMaG8PCz3puEk443NZo03P6V4NW+GR8LcVB+/AFhZzuJCCJrlwgEMti EVBc2CIswwjEM7DwvODfpBtHpY6dTRbLj3WhiX0Pys8ZYJQ3pshevPjJ+35O6IT7SwuQ R4lK+0VylTanq1WdOMXyFKGGJYXLXvNOyVAtgXSYddha3vUQZGRyP0+y/XhvuZZye58k SFVW5nWDW4hYHelXyECN64M6IqrNMEVVm8U+n7ga+3cIUz85+XK5b0sY9t+iw8hnlM4I l10A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=mlsMk8PZS6npqfquBK8rK+xl8vG7eDKmHuDcvTYKP24=; b=N1nUqm4QrzeNphh3H6wivMRqp7ABeZNhuBHkVnY3vO2AN/SOgmkMJjDSvJOnx6Arj5 FlZxHOkHHSrAGd22K/VXaMgr8Skz7A629tHmSfTL6LyIFGxTq64fNGM22EYHMHKHfcc9 4Zb5IxG+Lq1Hbj1NseP0jUHi07BboTaoUWGYtOr9oz9qbradjJBhzTXplAAX/WV1JvNk MCf5++tv2mx8sEYSDh4mR3SF+dsUFzsuQH/pq0YCn0DShKbSMNiGPNPxC/S8qAr+hknp fGtybccQJv6NWXjjDOC0IZqGLiSA4u8azefFG+7qnZWuJPdjA4V89OwDazh5CjE58RPU d9aA== X-Gm-Message-State: AIVw112c3vY3Lv8czUUdWoMu3b+/vt/tI8TLOpaz3zhq9DmDbkrNc8tA XJBo/nqrBiPaYe1sfuU= X-Received: by 10.99.100.198 with SMTP id y189mr1117498pgb.355.1501825481669; Thu, 03 Aug 2017 22:44:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:17 -0700 Message-Id: <20170804054426.10590-15-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH for-2.11 14/23] tcg/sparc: Use constant pool for movi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.h | 2 ++ tcg/sparc/tcg-target.inc.c | 77 +++++++++++++++++++++++++++++++++---------= ---- 2 files changed, 58 insertions(+), 21 deletions(-) diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 3ac0bd33d3..83f9397e04 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -173,4 +173,6 @@ static inline void flush_icache_range(uintptr_t start, = uintptr_t stop) =20 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 +#define TCG_TARGET_NEED_POOL_LABELS + #endif diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 7d73c25347..bd7c1461c6 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -22,6 +22,8 @@ * THE SOFTWARE. */ =20 +#include "tcg-pool.inc.c" + #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { "%g0", @@ -292,33 +294,46 @@ static inline int check_fit_i32(int32_t val, unsigned= int bits) static void patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - uint32_t insn; + uint32_t insn =3D *code_ptr; + intptr_t pcrel; =20 - tcg_debug_assert(addend =3D=3D 0); - value =3D tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr); + value +=3D addend; + pcrel =3D tcg_ptr_byte_diff((tcg_insn_unit *)value, code_ptr); =20 switch (type) { case R_SPARC_WDISP16: - if (!check_fit_ptr(value >> 2, 16)) { - tcg_abort(); - } - insn =3D *code_ptr; + assert(check_fit_ptr(pcrel >> 2, 16)); insn &=3D ~INSN_OFF16(-1); - insn |=3D INSN_OFF16(value); - *code_ptr =3D insn; + insn |=3D INSN_OFF16(pcrel); break; case R_SPARC_WDISP19: - if (!check_fit_ptr(value >> 2, 19)) { - tcg_abort(); - } - insn =3D *code_ptr; + assert(check_fit_ptr(pcrel >> 2, 19)); insn &=3D ~INSN_OFF19(-1); - insn |=3D INSN_OFF19(value); - *code_ptr =3D insn; + insn |=3D INSN_OFF19(pcrel); + break; + case R_SPARC_13: + /* Note that we're abusing this reloc type for our own needs. */ + if (!check_fit_ptr(value, 13)) { + int adj =3D (value > 0 ? 0xff8 : -0x1000); + value -=3D adj; + assert(check_fit_ptr(value, 13)); + *code_ptr++ =3D (ARITH_ADD | INSN_RD(TCG_REG_T2) + | INSN_RS1(TCG_REG_TB) | INSN_IMM13(adj)); + insn ^=3D INSN_RS1(TCG_REG_TB) ^ INSN_RS1(TCG_REG_T2); + } + insn &=3D ~INSN_IMM13(-1); + insn |=3D INSN_IMM13(value); break; + case R_SPARC_32: + /* Note that we're abusing this reloc type for our own needs. */ + code_ptr[0] =3D deposit32(code_ptr[0], 0, 22, value >> 10); + code_ptr[1] =3D deposit32(code_ptr[1], 0, 10, value); + return; default: - tcg_abort(); + g_assert_not_reached(); } + + *code_ptr =3D insn; } =20 /* parse target specific constraints */ @@ -474,12 +489,24 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, return; } =20 - if (USE_REG_TB && !in_prologue) { - intptr_t diff =3D arg - (uintptr_t)s->code_gen_ptr; - if (check_fit_ptr(diff, 13)) { - tcg_out_arithi(s, ret, TCG_REG_TB, diff, ARITH_ADD); - return; + if (!in_prologue) { + if (USE_REG_TB) { + intptr_t diff =3D arg - (uintptr_t)s->code_gen_ptr; + if (check_fit_ptr(diff, 13)) { + tcg_out_arithi(s, ret, TCG_REG_TB, diff, ARITH_ADD); + } else { + new_pool_label(s, arg, R_SPARC_13, s->code_ptr, + -(intptr_t)s->code_gen_ptr); + tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB)); + /* May be used to extend the 13-bit range in patch_reloc. = */ + tcg_out32(s, NOP); + } + } else { + new_pool_label(s, arg, R_SPARC_32, s->code_ptr, 0); + tcg_out_sethi(s, ret, 0); + tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) | INSN_IMM13(0= )); } + return; } =20 /* A 64-bit constant decomposed into 2 32-bit pieces. */ @@ -1058,6 +1085,14 @@ static void tcg_target_qemu_prologue(TCGContext *s) #endif } =20 +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i =3D 0; i < count; ++i) { + p[i] =3D NOP; + } +} + #if defined(CONFIG_SOFTMMU) /* Perform the TLB load and compare. =20 --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501826490986665.7822229394557; Thu, 3 Aug 2017 23:01:30 -0700 (PDT) Received: from localhost ([::1]:37124 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVft-0002uW-Cl for importer@patchew.org; Fri, 04 Aug 2017 02:01:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59830) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPh-00042f-Vb for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPg-0003YI-6k for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:46 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:37030) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPf-0003Vw-Tb for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:44 -0400 Received: by mail-pg0-x242.google.com with SMTP id 83so822317pgb.4 for ; Thu, 03 Aug 2017 22:44:43 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.41 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=0nzIjXHTFwDExDbFCq8HRhgDcDJfLlfeF++robag2lE=; b=pdRyPbHeo90Wo69zmq36OsoLRgTjVWu2crZv/7Vn3k/Df3XN7P50DZ356pel3kOaq8 zccsBFoRkik2FFbVgheMrOQMVCAVv8xb2/AkkeEfNaLU3d7i3etLLF+Lsxx+93tWgaR6 pJS0hvhxTER1f1zhjpaLAwA4JPdSbmxApC7kblQ0BF2i/+vFDAcwppcyYsRqyYWXBivh LKWs4tTuaRMe89G+zrPU1pb3uPUs9/2IcdAvQezXaD5JddqxNydbhOX0lGOMFbx5uxl3 3vcbnQ0D++TcpKXlsZrzfieTHC3qd1tdXyrVbLnPaaqQnE7fBsxLQLBY1YyU/+RjiXKR D12w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=0nzIjXHTFwDExDbFCq8HRhgDcDJfLlfeF++robag2lE=; b=NieasGpZW4yhRpL31LEhYsikZK5w44zXBXuAJWT2y8B+4hGjMm62tJdxLVzKQhUn+6 nEPikK5ogXsT4StJOzBdaZjMScdDcLsNL64j8c4QKqo+vXfzMjVDwQlj4Mb5MJSVtE1V 5gFj54hvGIY0GGh+qPbwMaa8ffJnaGcPHGQVnZR8lFTVDbmfEOlT2DXJrpNgR89AvNZy 6FzZr1bTtecn/N846lVyhB9dvd+ONJYzGJMq/T5OX9YTyEeMa+nk3o01Fpr60HqkLwU6 EVV5oOO1YZYHyWjzWpPbU/Rei6vDFNellFP3nktW+4/CN3bzOz0kvvtq1aTXbS2KN8tt Fq8w== X-Gm-Message-State: AIVw113ptXszlJaAz0/8wXSjEMvwq/AI3n5Tz1fF+HWzlcx6/ZeAqJQx ddkDcN5z+O1ckD7s30k= X-Received: by 10.84.211.136 with SMTP id c8mr1399212pli.273.1501825482732; Thu, 03 Aug 2017 22:44:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:18 -0700 Message-Id: <20170804054426.10590-16-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH for-2.11 15/23] tcg/arm: Improve tlb load for armv7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use UBFX to avoid limitation on CPU_TLB_BITS. Since we're dropping the initial shift, we need to replace the page masking. We can use MOVW+BIC to do this without shifting. The result is the same size as the armv6 path with one less conditional instruction. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 72 ++++++++++++++++++++++++++++++++++----------= ---- 1 file changed, 52 insertions(+), 20 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 81ea900852..66c369c239 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1173,18 +1173,33 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); =20 - /* Should generate something like the following: - * shr tmp, addrlo, #TARGET_PAGE_BITS (1) + /* V7 generates the following: + * ubfx r0, addrlo, #TARGET_PAGE_BITS, #CPU_TLB_BITS * add r2, env, #high - * and r0, tmp, #(CPU_TLB_SIZE - 1) (2) - * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS (3) - * ldr r0, [r2, #cmp] (4) + * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS + * ldr r0, [r2, #cmp] + * ldr r2, [r2, #add] + * movw tmp, #page_align_mask + * bic tmp, addrlo, tmp + * cmp r0, tmp + * + * Otherwise we generate: + * shr tmp, addrlo, #TARGET_PAGE_BITS + * add r2, env, #high + * and r0, tmp, #(CPU_TLB_SIZE - 1) + * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS + * ldr r0, [r2, #cmp] + * ldr r2, [r2, #add] * tst addrlo, #s_mask - * ldr r2, [r2, #add] (5) * cmpeq r0, tmp, lsl #TARGET_PAGE_BITS */ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, - 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + if (use_armv7_instructions) { + tcg_out_extract(s, COND_AL, TCG_REG_R0, addrlo, + TARGET_PAGE_BITS, CPU_TLB_BITS); + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, + 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + } =20 /* We checked that the offset is contained within 16 bits above. */ if (add_off > 0xfff || (use_armv6_instructions && cmp_off > 0xff)) { @@ -1194,9 +1209,10 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg= addrlo, TCGReg addrhi, add_off -=3D cmp_off & 0xff00; cmp_off &=3D 0xff; } - - tcg_out_dat_imm(s, COND_AL, ARITH_AND, - TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1); + if (!use_armv7_instructions) { + tcg_out_dat_imm(s, COND_AL, ARITH_AND, + TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1); + } tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); =20 @@ -1212,24 +1228,40 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, } } =20 + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, add_off); + /* Check alignment. We don't support inline unaligned acceses, but we can easily support overalignment checks. */ if (a_bits < s_bits) { a_bits =3D s_bits; } - if (a_bits) { - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, (1 << a_bits) - = 1); - } =20 - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, add_off); + if (use_armv7_instructions) { + tcg_target_ulong mask =3D ~(TARGET_PAGE_MASK | ((1 << a_bits) - 1)= ); + int rot =3D encode_imm(mask); =20 - tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, 0, - TCG_REG_R0, TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BIT= S)); + if (rot >=3D 0) {=20 + tcg_out_dat_imm(s, COND_AL, ARITH_BIC, TCG_REG_TMP, addrlo, + rotl(mask, rot) | (rot << 7)); + } else { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, mask); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, + addrlo, TCG_REG_TMP, 0); + } + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP,= 0); + } else { + if (a_bits) { + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, + (1 << a_bits) - 1); + } + tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, + 0, TCG_REG_R0, TCG_REG_TMP, + SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + } =20 if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, - TCG_REG_R1, addrhi, SHIFT_IMM_LSL(0)); + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addrhi, 0); } =20 return TCG_REG_R2; --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501825756243556.2658461861251; Thu, 3 Aug 2017 22:49:16 -0700 (PDT) Received: from localhost ([::1]:36674 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVU2-0007cG-SX for importer@patchew.org; Fri, 04 Aug 2017 01:49:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59846) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPi-00043G-HD for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPh-0003c4-Hg for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:46 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:38645) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPh-0003aE-7L for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:45 -0400 Received: by mail-pf0-x242.google.com with SMTP id h75so859905pfh.5 for ; Thu, 03 Aug 2017 22:44:45 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.42 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=ypCGWAAFTT76IbFUdPsqcdHCsgwqTXS+gTjdIagqoLE=; b=e6bvcqUSnRMMhQUGbFoQAXypCzYnUyL/zFr8R0JbZ4yma08xpkpb/uHWTunUrhfm7X GuCDT10o9Bcx0JQuHapXC15eNu+As1T4fApKR3KkeZ0IHG4wdhuOH3CkuTFVk04K2tXR kx+/HR4c/oKsP4LaFqBHkBgXLBqOWi88VSt5bAvkJgfjBnWgr9yah0KyHEnRqwMuhTp4 BRZ9vCseoG+RxOkrBwYPbJ2Q0thU18j/D5tE58H59hQxhT05jRC+tIjS1vLNTLI2LzRy MO5dlxYkxDCTF73YCxTEOXLLZxwWr3fIl5JzY2swuPGsLens5gPomW34Dlq7cS7co9nn bNDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=ypCGWAAFTT76IbFUdPsqcdHCsgwqTXS+gTjdIagqoLE=; b=TOeRznrVky2K+8u+5W8Y1z12Jvi0WKgYSHqQnUYdJXIaQv0k6mCiUWgntyZzh5nFo2 0LGLcygWssq6GIs2qd/oIl1QnDD/DHHlOHDMFZYaYFPKEjnpj8N9KMAc7PX4IBneMR0M awP8Ut3AkX3WNz4esE6mOGaLRlqch4A3BT3Cg8Y67VAaDJrj0evzL5j1OlISrzUl9PkR M9FEO0CjCeZPNMyH4cgJ8KKcvjGRkW5YHTyj4PIfWRT1aRrsWbohccW+WE2dVHdlYJ6y em2m4xqVjxukJqnMN6dvso3O2OpYPDeX65B/rJ/klqjWWgkhbG8QrYzlSnX+wbz40TXT cCww== X-Gm-Message-State: AIVw113N/udb5JvwNsp089kSD2UiGBvS1kFktT9HkSDXQtyGvm8y9sAA dqi0ou6qErXecLfB2iU= X-Received: by 10.98.220.27 with SMTP id t27mr1298587pfg.32.1501825484042; Thu, 03 Aug 2017 22:44:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:19 -0700 Message-Id: <20170804054426.10590-17-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH for-2.11 16/23] tcg/arm: Tighten tlb indexing offset test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We are not going to use ldrd for loading the comparator for 32-bit guests, so don't limit cmp_off to 8 bits then. This eliminates one insn in the tlb load for some guests. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 66c369c239..6c12b169ce 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1202,7 +1202,9 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg = addrlo, TCGReg addrhi, } =20 /* We checked that the offset is contained within 16 bits above. */ - if (add_off > 0xfff || (use_armv6_instructions && cmp_off > 0xff)) { + if (add_off > 0xfff + || (use_armv6_instructions && TARGET_LONG_BITS =3D=3D 64 + && cmp_off > 0xff)) { tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, (24 << 7) | (cmp_off >> 8)); base =3D TCG_REG_R2; --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501826219611609.6147006503791; Thu, 3 Aug 2017 22:56:59 -0700 (PDT) Received: from localhost ([::1]:36772 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVbV-0006mI-VC for importer@patchew.org; Fri, 04 Aug 2017 01:56:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59951) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPm-00047h-OI for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPj-0003gg-BL for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:50 -0400 Received: from mail-pf0-x244.google.com ([2607:f8b0:400e:c00::244]:37864) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPj-0003ef-1M for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:47 -0400 Received: by mail-pf0-x244.google.com with SMTP id p13so862170pfd.4 for ; Thu, 03 Aug 2017 22:44:46 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.44 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=JwMEumvMiaJTSwmF/27zkKXW3UnhOk0WuvUsJK3jXNQ=; b=sY5aNAska+um9JOg977AFElpNE6GMcjIb1k/bGbmGNpnh1R32KK2j5skWOnCPx+9mF 4YKX5nLwgrDMTkX3XyZUedHcnQilwOxCU7eXiNDqXvPdbEjE5mBLQ6hrx2JMwZomiESQ C1Ij+A3in6xSspahtFG0eB96tCvvmqynSv+85WTH5UA2bKESljzgk2IkU35cJTOmVgsw dwSfybJM/7gvIL467BufI+cLqC1omYIyXO1Usc/JDr+1clgWyPTWGtXnu84YDdkgJhD/ go3h4I/Rl0XCQQdDWhITgZwv4332uX5UyH5Ou1odrGOiV/I+47dsmi2e3UERLaNlFvax ME1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=JwMEumvMiaJTSwmF/27zkKXW3UnhOk0WuvUsJK3jXNQ=; b=CILTHxAkMZuqIkddeSdkF27Q/UqWaVHhHcHQ1fDPIYgQ2eHE5uciKAHRz8uN6I+Wdh wXt9uPbV429hPvdQITpOvw+M1sco/voTeiaNATFrG3rn6c/7t1LIHpMsAk71mTrkzE8y /hFznxWGxIqVhCHHWlWyxXQSYufYoiIDrpgPc1fCuWhOV3mN9s3qZH9AjdhHlcUi2yUS +UgM+mMEObreANAWnzKnycp99pnW1N7qaZX2jOgIZ2OUlg9r+CFjSx5/gGmlJ0hiuwKE 0PyOT6ejWwOCHg3/XCmTT3AYiVdSpSdEjtoQFceFY+19cW9NvD7g4PHHpHWuU4yaKGBb 4kzA== X-Gm-Message-State: AIVw112df2fHLqIsng6U5k0sVRs2W1ZADhiuH4Rxv2Kaz+MNDeCYe0wj 3Tyv0pAJcLFE7de5B+A= X-Received: by 10.98.57.66 with SMTP id g63mr1245389pfa.5.1501825485305; Thu, 03 Aug 2017 22:44:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:20 -0700 Message-Id: <20170804054426.10590-18-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH for-2.11 17/23] tcg/arm: Code rearrangement X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move constants before all of the functions. Move tcg_out_ functions before all of the others. No functional change. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 599 +++++++++++++++++++++++--------------------= ---- 1 file changed, 299 insertions(+), 300 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 6c12b169ce..f40e87066f 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -85,6 +85,97 @@ static const int tcg_target_call_oarg_regs[2] =3D { =20 #define TCG_REG_TMP TCG_REG_R12 =20 +enum arm_cond_code_e { + COND_EQ =3D 0x0, + COND_NE =3D 0x1, + COND_CS =3D 0x2, /* Unsigned greater or equal */ + COND_CC =3D 0x3, /* Unsigned less than */ + COND_MI =3D 0x4, /* Negative */ + COND_PL =3D 0x5, /* Zero or greater */ + COND_VS =3D 0x6, /* Overflow */ + COND_VC =3D 0x7, /* No overflow */ + COND_HI =3D 0x8, /* Unsigned greater than */ + COND_LS =3D 0x9, /* Unsigned less or equal */ + COND_GE =3D 0xa, + COND_LT =3D 0xb, + COND_GT =3D 0xc, + COND_LE =3D 0xd, + COND_AL =3D 0xe, +}; + +#define TO_CPSR (1 << 20) + +#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) +#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) +#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) +#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) +#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) +#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) +#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) +#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) + +typedef enum { + ARITH_AND =3D 0x0 << 21, + ARITH_EOR =3D 0x1 << 21, + ARITH_SUB =3D 0x2 << 21, + ARITH_RSB =3D 0x3 << 21, + ARITH_ADD =3D 0x4 << 21, + ARITH_ADC =3D 0x5 << 21, + ARITH_SBC =3D 0x6 << 21, + ARITH_RSC =3D 0x7 << 21, + ARITH_TST =3D 0x8 << 21 | TO_CPSR, + ARITH_CMP =3D 0xa << 21 | TO_CPSR, + ARITH_CMN =3D 0xb << 21 | TO_CPSR, + ARITH_ORR =3D 0xc << 21, + ARITH_MOV =3D 0xd << 21, + ARITH_BIC =3D 0xe << 21, + ARITH_MVN =3D 0xf << 21, + + INSN_CLZ =3D 0x016f0f10, + INSN_RBIT =3D 0x06ff0f30, + + INSN_LDR_IMM =3D 0x04100000, + INSN_LDR_REG =3D 0x06100000, + INSN_STR_IMM =3D 0x04000000, + INSN_STR_REG =3D 0x06000000, + + INSN_LDRH_IMM =3D 0x005000b0, + INSN_LDRH_REG =3D 0x001000b0, + INSN_LDRSH_IMM =3D 0x005000f0, + INSN_LDRSH_REG =3D 0x001000f0, + INSN_STRH_IMM =3D 0x004000b0, + INSN_STRH_REG =3D 0x000000b0, + + INSN_LDRB_IMM =3D 0x04500000, + INSN_LDRB_REG =3D 0x06500000, + INSN_LDRSB_IMM =3D 0x005000d0, + INSN_LDRSB_REG =3D 0x001000d0, + INSN_STRB_IMM =3D 0x04400000, + INSN_STRB_REG =3D 0x06400000, + + INSN_LDRD_IMM =3D 0x004000d0, + INSN_LDRD_REG =3D 0x000000d0, + INSN_STRD_IMM =3D 0x004000f0, + INSN_STRD_REG =3D 0x000000f0, + + INSN_DMB_ISH =3D 0x5bf07ff5, + INSN_DMB_MCR =3D 0xba0f07ee, +} ARMInsn; + +static const uint8_t tcg_cond_to_arm_cond[] =3D { + [TCG_COND_EQ] =3D COND_EQ, + [TCG_COND_NE] =3D COND_NE, + [TCG_COND_LT] =3D COND_LT, + [TCG_COND_GE] =3D COND_GE, + [TCG_COND_LE] =3D COND_LE, + [TCG_COND_GT] =3D COND_GT, + /* unsigned */ + [TCG_COND_LTU] =3D COND_CC, + [TCG_COND_GEU] =3D COND_CS, + [TCG_COND_LEU] =3D COND_LS, + [TCG_COND_GTU] =3D COND_HI, +}; + static inline void reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *targ= et) { ptrdiff_t offset =3D (tcg_ptr_byte_diff(target, code_ptr) - 8) >> 2; @@ -236,183 +327,257 @@ static inline int tcg_target_const_match(tcg_target= _long val, TCGType type, } } =20 -#define TO_CPSR (1 << 20) +static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset) +{ + tcg_out32(s, (cond << 28) | 0x0a000000 | + (((offset - 8) >> 2) & 0x00ffffff)); +} =20 -typedef enum { - ARITH_AND =3D 0x0 << 21, - ARITH_EOR =3D 0x1 << 21, - ARITH_SUB =3D 0x2 << 21, - ARITH_RSB =3D 0x3 << 21, - ARITH_ADD =3D 0x4 << 21, - ARITH_ADC =3D 0x5 << 21, - ARITH_SBC =3D 0x6 << 21, - ARITH_RSC =3D 0x7 << 21, - ARITH_TST =3D 0x8 << 21 | TO_CPSR, - ARITH_CMP =3D 0xa << 21 | TO_CPSR, - ARITH_CMN =3D 0xb << 21 | TO_CPSR, - ARITH_ORR =3D 0xc << 21, - ARITH_MOV =3D 0xd << 21, - ARITH_BIC =3D 0xe << 21, - ARITH_MVN =3D 0xf << 21, +static inline void tcg_out_b_noaddr(TCGContext *s, int cond) +{ + /* We pay attention here to not modify the branch target by masking + the corresponding bytes. This ensure that caches and memory are + kept coherent during retranslation. */ + tcg_out32(s, deposit32(*s->code_ptr, 24, 8, (cond << 4) | 0x0a)); +} =20 - INSN_CLZ =3D 0x016f0f10, - INSN_RBIT =3D 0x06ff0f30, +static inline void tcg_out_bl_noaddr(TCGContext *s, int cond) +{ + /* We pay attention here to not modify the branch target by masking + the corresponding bytes. This ensure that caches and memory are + kept coherent during retranslation. */ + tcg_out32(s, deposit32(*s->code_ptr, 24, 8, (cond << 4) | 0x0b)); +} =20 - INSN_LDR_IMM =3D 0x04100000, - INSN_LDR_REG =3D 0x06100000, - INSN_STR_IMM =3D 0x04000000, - INSN_STR_REG =3D 0x06000000, +static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset) +{ + tcg_out32(s, (cond << 28) | 0x0b000000 | + (((offset - 8) >> 2) & 0x00ffffff)); +} =20 - INSN_LDRH_IMM =3D 0x005000b0, - INSN_LDRH_REG =3D 0x001000b0, - INSN_LDRSH_IMM =3D 0x005000f0, - INSN_LDRSH_REG =3D 0x001000f0, - INSN_STRH_IMM =3D 0x004000b0, - INSN_STRH_REG =3D 0x000000b0, +static inline void tcg_out_blx(TCGContext *s, int cond, int rn) +{ + tcg_out32(s, (cond << 28) | 0x012fff30 | rn); +} =20 - INSN_LDRB_IMM =3D 0x04500000, - INSN_LDRB_REG =3D 0x06500000, - INSN_LDRSB_IMM =3D 0x005000d0, - INSN_LDRSB_REG =3D 0x001000d0, - INSN_STRB_IMM =3D 0x04400000, - INSN_STRB_REG =3D 0x06400000, +static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset) +{ + tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | + (((offset - 8) >> 2) & 0x00ffffff)); +} =20 - INSN_LDRD_IMM =3D 0x004000d0, - INSN_LDRD_REG =3D 0x000000d0, - INSN_STRD_IMM =3D 0x004000f0, - INSN_STRD_REG =3D 0x000000f0, +static inline void tcg_out_dat_reg(TCGContext *s, + int cond, int opc, int rd, int rn, int rm, int shift) +{ + tcg_out32(s, (cond << 28) | (0 << 25) | opc | + (rn << 16) | (rd << 12) | shift | rm); +} =20 - INSN_DMB_ISH =3D 0x5bf07ff5, - INSN_DMB_MCR =3D 0xba0f07ee, +static inline void tcg_out_nop(TCGContext *s) +{ + if (use_armv7_instructions) { + /* Architected nop introduced in v6k. */ + /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this + also Just So Happened to do nothing on pre-v6k so that we + don't need to conditionalize it? */ + tcg_out32(s, 0xe320f000); + } else { + /* Prior to that the assembler uses mov r0, r0. */ + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 0, 0, 0, SHIFT_IMM_LSL(0)); + } +} =20 -} ARMInsn; +static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm) +{ + /* Simple reg-reg move, optimising out the 'do nothing' case */ + if (rd !=3D rm) { + tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); + } +} =20 -#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) -#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20) -#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40) -#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60) -#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10) -#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30) -#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50) -#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70) +static inline void tcg_out_bx(TCGContext *s, int cond, TCGReg rn) +{ + /* Unless the C portion of QEMU is compiled as thumb, we don't + actually need true BX semantics; merely a branch to an address + held in a register. */ + if (use_armv5t_instructions) { + tcg_out32(s, (cond << 28) | 0x012fff10 | rn); + } else { + tcg_out_mov_reg(s, cond, TCG_REG_PC, rn); + } +} =20 -enum arm_cond_code_e { - COND_EQ =3D 0x0, - COND_NE =3D 0x1, - COND_CS =3D 0x2, /* Unsigned greater or equal */ - COND_CC =3D 0x3, /* Unsigned less than */ - COND_MI =3D 0x4, /* Negative */ - COND_PL =3D 0x5, /* Zero or greater */ - COND_VS =3D 0x6, /* Overflow */ - COND_VC =3D 0x7, /* No overflow */ - COND_HI =3D 0x8, /* Unsigned greater than */ - COND_LS =3D 0x9, /* Unsigned less or equal */ - COND_GE =3D 0xa, - COND_LT =3D 0xb, - COND_GT =3D 0xc, - COND_LE =3D 0xd, - COND_AL =3D 0xe, -}; +static inline void tcg_out_dat_imm(TCGContext *s, + int cond, int opc, int rd, int rn, int im) +{ + tcg_out32(s, (cond << 28) | (1 << 25) | opc | + (rn << 16) | (rd << 12) | im); +} =20 -static const uint8_t tcg_cond_to_arm_cond[] =3D { - [TCG_COND_EQ] =3D COND_EQ, - [TCG_COND_NE] =3D COND_NE, - [TCG_COND_LT] =3D COND_LT, - [TCG_COND_GE] =3D COND_GE, - [TCG_COND_LE] =3D COND_LE, - [TCG_COND_GT] =3D COND_GT, - /* unsigned */ - [TCG_COND_LTU] =3D COND_CC, - [TCG_COND_GEU] =3D COND_CS, - [TCG_COND_LEU] =3D COND_LS, - [TCG_COND_GTU] =3D COND_HI, -}; +/* Note that this routine is used for both LDR and LDRH formats, so we do + not wish to include an immediate shift at this point. */ +static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg r= t, + TCGReg rn, TCGReg rm, bool u, bool p, bool w) +{ + tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) + | (w << 21) | (rn << 16) | (rt << 12) | rm); +} + +static void tcg_out_memop_8(TCGContext *s, int cond, ARMInsn opc, TCGReg r= t, + TCGReg rn, int imm8, bool p, bool w) +{ + bool u =3D 1; + if (imm8 < 0) { + imm8 =3D -imm8; + u =3D 0; + } + tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | + (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf= )); +} + +static void tcg_out_memop_12(TCGContext *s, int cond, ARMInsn opc, TCGReg = rt, + TCGReg rn, int imm12, bool p, bool w) +{ + bool u =3D 1; + if (imm12 < 0) { + imm12 =3D -imm12; + u =3D 0; + } + tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | + (rn << 16) | (rt << 12) | imm12); +} + +static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) +{ + tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); +} + +static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) +{ + tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); +} + +static inline void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); +} + +static inline void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); +} + +static inline void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); +} + +/* Register pre-increment with base writeback. */ +static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); +} + +static inline void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) +{ + tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); +} + +static inline void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) +{ + tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); +} =20 -static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset) +static inline void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { - tcg_out32(s, (cond << 28) | 0x0a000000 | - (((offset - 8) >> 2) & 0x00ffffff)); + tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_b_noaddr(TCGContext *s, int cond) +static inline void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { - /* We pay attention here to not modify the branch target by masking - the corresponding bytes. This ensure that caches and memory are - kept coherent during retranslation. */ - tcg_out32(s, deposit32(*s->code_ptr, 24, 8, (cond << 4) | 0x0a)); + tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_bl_noaddr(TCGContext *s, int cond) +static inline void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { - /* We pay attention here to not modify the branch target by masking - the corresponding bytes. This ensure that caches and memory are - kept coherent during retranslation. */ - tcg_out32(s, deposit32(*s->code_ptr, 24, 8, (cond << 4) | 0x0b)); + tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset) +static inline void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { - tcg_out32(s, (cond << 28) | 0x0b000000 | - (((offset - 8) >> 2) & 0x00ffffff)); + tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_blx(TCGContext *s, int cond, int rn) +static inline void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { - tcg_out32(s, (cond << 28) | 0x012fff30 | rn); + tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_blx_imm(TCGContext *s, int32_t offset) +static inline void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) { - tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) | - (((offset - 8) >> 2) & 0x00ffffff)); + tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); } =20 -static inline void tcg_out_dat_reg(TCGContext *s, - int cond, int opc, int rd, int rn, int rm, int shift) +static inline void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm12) { - tcg_out32(s, (cond << 28) | (0 << 25) | opc | - (rn << 16) | (rd << 12) | shift | rm); + tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); } =20 -static inline void tcg_out_nop(TCGContext *s) +static inline void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { - if (use_armv7_instructions) { - /* Architected nop introduced in v6k. */ - /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this - also Just So Happened to do nothing on pre-v6k so that we - don't need to conditionalize it? */ - tcg_out32(s, 0xe320f000); - } else { - /* Prior to that the assembler uses mov r0, r0. */ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 0, 0, 0, SHIFT_IMM_LSL(0)); - } + tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm) +static inline void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { - /* Simple reg-reg move, optimising out the 'do nothing' case */ - if (rd !=3D rm) { - tcg_out_dat_reg(s, cond, ARITH_MOV, rd, 0, rm, SHIFT_IMM_LSL(0)); - } + tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); } =20 -static inline void tcg_out_bx(TCGContext *s, int cond, TCGReg rn) +static inline void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, int imm8) { - /* Unless the C portion of QEMU is compiled as thumb, we don't - actually need true BX semantics; merely a branch to an address - held in a register. */ - if (use_armv5t_instructions) { - tcg_out32(s, (cond << 28) | 0x012fff10 | rn); - } else { - tcg_out_mov_reg(s, cond, TCG_REG_PC, rn); - } + tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); } =20 -static inline void tcg_out_dat_imm(TCGContext *s, - int cond, int opc, int rd, int rn, int im) +static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt, + TCGReg rn, TCGReg rm) { - tcg_out32(s, (cond << 28) | (1 << 25) | opc | - (rn << 16) | (rd << 12) | im); + tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); } =20 static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) @@ -747,172 +912,6 @@ static inline void tcg_out_sextract(TCGContext *s, in= t cond, TCGReg rd, | (ofs << 7) | ((len - 1) << 16)); } =20 -/* Note that this routine is used for both LDR and LDRH formats, so we do - not wish to include an immediate shift at this point. */ -static void tcg_out_memop_r(TCGContext *s, int cond, ARMInsn opc, TCGReg r= t, - TCGReg rn, TCGReg rm, bool u, bool p, bool w) -{ - tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) - | (w << 21) | (rn << 16) | (rt << 12) | rm); -} - -static void tcg_out_memop_8(TCGContext *s, int cond, ARMInsn opc, TCGReg r= t, - TCGReg rn, int imm8, bool p, bool w) -{ - bool u =3D 1; - if (imm8 < 0) { - imm8 =3D -imm8; - u =3D 0; - } - tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | - (rn << 16) | (rt << 12) | ((imm8 & 0xf0) << 4) | (imm8 & 0xf= )); -} - -static void tcg_out_memop_12(TCGContext *s, int cond, ARMInsn opc, TCGReg = rt, - TCGReg rn, int imm12, bool p, bool w) -{ - bool u =3D 1; - if (imm12 < 0) { - imm12 =3D -imm12; - u =3D 0; - } - tcg_out32(s, (cond << 28) | opc | (u << 23) | (p << 24) | (w << 21) | - (rn << 16) | (rt << 12) | imm12); -} - -static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0); -} - -static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_STR_IMM, rt, rn, imm12, 1, 0); -} - -static inline void tcg_out_ld32_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_st32_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_ldrd_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRD_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_ldrd_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_strd_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_strd_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STRD_REG, rt, rn, rm, 1, 1, 0); -} - -/* Register pre-increment with base writeback. */ -static inline void tcg_out_ld32_rwb(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDR_REG, rt, rn, rm, 1, 1, 1); -} - -static inline void tcg_out_st32_rwb(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STR_REG, rt, rn, rm, 1, 1, 1); -} - -static inline void tcg_out_ld16u_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRH_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_st16_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_STRH_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_ld16u_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRH_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_st16_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STRH_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_ld16s_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRSH_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_ld16s_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRSH_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_ld8_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_LDRB_IMM, rt, rn, imm12, 1, 0); -} - -static inline void tcg_out_st8_12(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm12) -{ - tcg_out_memop_12(s, cond, INSN_STRB_IMM, rt, rn, imm12, 1, 0); -} - -static inline void tcg_out_ld8_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRB_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_st8_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_STRB_REG, rt, rn, rm, 1, 1, 0); -} - -static inline void tcg_out_ld8s_8(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, int imm8) -{ - tcg_out_memop_8(s, cond, INSN_LDRSB_IMM, rt, rn, imm8, 1, 0); -} - -static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt, - TCGReg rn, TCGReg rm) -{ - tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); -} - static inline void tcg_out_ld32u(TCGContext *s, int cond, int rd, int rn, int32_t offset) { --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501825916951184.77860006640833; Thu, 3 Aug 2017 22:51:56 -0700 (PDT) Received: from localhost ([::1]:36687 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVWd-0001TX-FC for importer@patchew.org; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.45 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=GUbINzV3agUVGHQrOdgBqlgaI7Rdgw1Uy/To7ET+TCE=; b=MivKAJ939i9/Z4VTdLIhFd8n5odvMrTswZnEPxXSsEHtgzWFkQ9JnoJlQvHxNwR8q4 EeM8VydEArLLH5YZkgVESKC2e72FDwCwZXQBlO1goZU9moPuGF15bSlK1urXBoV9UXvi Z3jLOM/T88FU1VLDHbD9L7TEu/1mYfkRwkWZs4l/YM3YNBqghqmQhqff44Zk05dJYjBe 07aCquLymUqRKBw/yE0xXQ7OYAVaPf3jUQI8EPJdS/GQcJ2yqvBw+TtZmGagsRi0lBWZ DfHnvXDWMEi50iD21QnJz2YiVDb8jFdMYj1Ex+vwAZjIiCzKWXfleffGnI3Drz4bMEHC mPsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=GUbINzV3agUVGHQrOdgBqlgaI7Rdgw1Uy/To7ET+TCE=; b=VbfbjwlkTcfDbKIvg2iM4PL72+iTVyJlH6ewWOZEr8Pkw6ejr/cKnQvf3dgre5Xosd 3/f4IO2moJhor8PMEcMBUCzrP1qzQWZrTIOflKM9brlbdNbYw/HFAhFre7G6CbFJVtMr U2cQTuLfbIVQaC774UvVSBXr4RnI+8oSJjq+0PMvAm3dd6mBGeupKKDarQTEkoVPksTE EqgwwK3PuuZl9JEHxfmMAv38/tqvy/1jfmd4sHj//Ea3XsGrbbGa4rsJnjdSQOwdo8cU X01FJ1C9zci2MJgTvbCeTOJl+FtwPhUa3OFZh8xI/NILjlyPX1lNIPcNCTSz4auPG0Hh j2uQ== X-Gm-Message-State: AIVw113gOotrokwGgrmq4ZYov/dXNQDgPK2UmtYrhiOc0KK4VWNTFuWI NqjI+PHg2LSwPMXxjk4= X-Received: by 10.84.218.66 with SMTP id f2mr1398595plm.206.1501825486327; Thu, 03 Aug 2017 22:44:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:21 -0700 Message-Id: <20170804054426.10590-19-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH for-2.11 18/23] tcg/arm: Extract INSN_NOP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We'll want this for tcg_out_nop_fill. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index f40e87066f..78603a19db 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -160,8 +160,18 @@ typedef enum { =20 INSN_DMB_ISH =3D 0x5bf07ff5, INSN_DMB_MCR =3D 0xba0f07ee, + + /* Architected nop introduced in v6k. */ + /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this + also Just So Happened to do nothing on pre-v6k so that we + don't need to conditionalize it? */ + INSN_NOP_v6k =3D 0xe320f000, + /* Otherwise the assembler uses mov r0,r0 */ + INSN_NOP_v4 =3D (COND_AL << 28) | ARITH_MOV, } ARMInsn; =20 +#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4) + static const uint8_t tcg_cond_to_arm_cond[] =3D { [TCG_COND_EQ] =3D COND_EQ, [TCG_COND_NE] =3D COND_NE, @@ -375,16 +385,7 @@ static inline void tcg_out_dat_reg(TCGContext *s, =20 static inline void tcg_out_nop(TCGContext *s) { - if (use_armv7_instructions) { - /* Architected nop introduced in v6k. */ - /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this - also Just So Happened to do nothing on pre-v6k so that we - don't need to conditionalize it? */ - tcg_out32(s, 0xe320f000); - } else { - /* Prior to that the assembler uses mov r0, r0. */ - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 0, 0, 0, SHIFT_IMM_LSL(0)); - } + tcg_out32(s, INSN_NOP); } =20 static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm) --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501826065368752.6828602446345; Thu, 3 Aug 2017 22:54:25 -0700 (PDT) Received: from localhost ([::1]:36694 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVZ1-0003zG-SZ for importer@patchew.org; Fri, 04 Aug 2017 01:54:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59952) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPm-00047i-OJ for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPk-0003jj-P6 for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:50 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:36537) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPk-0003ia-HQ for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:48 -0400 Received: by mail-pg0-x244.google.com with SMTP id y129so823862pgy.3 for ; Thu, 03 Aug 2017 22:44:48 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.46 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=EjXelywn3eVixFOxqlv/9tQ6JkpZ2APpI4N6eCIqiL4=; b=OrxmNPa19iNpBDuHj9cI04oE+AbYPeQ6MA2PY+4XMt2R+EblL5oqhn2Qd6fhRM/2Oi jNsdH1zEkvz6mVF9TReleoMDeaVSxmtHBrPSAY6VQ2/HmjZjfAXR9Y1MUJ7Hmygai++B LxzXFjIyAAbeMljjssNlIleGezLD4VHYiFs7jEhJ3XwEOQzC7LV6wQ+VlifPGSM6pVWE SlTCZgGRrvD64OJKIji5cqCa1erHpse7fI3oPi6JlaB/7/ry5Pof0vABT5KoiRRYo+LK Ln86NaEmOe/YPUF18SfpYyrxYxikuP42I11+S9qOIhCUMqYRc9G3WNOekYTK4MXuw3SN aaeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=EjXelywn3eVixFOxqlv/9tQ6JkpZ2APpI4N6eCIqiL4=; b=OvG1MP1ze+G3tXehRuqH4rA1xzojgowQ9LtUcNxfzSHSBw+Xppvp9wxsiBozs9GoE/ t7k8Aay/420qH6OTKid5rElJk3ybgjMEZgRcM/snWj0ktJvu9NBWzD9dXtr09cLnUiMS 7UxmixlCHPsNpMd3yEj9xsDT9d8KtJocjSWYowZe/Xt9llQ9/XK9JJ5ImTxh1wmBrXPY 4qTm7bmr5l7bTahBMEjEYd2ysw/18X2+1SoO9J0MjL/O1AOpKBVeNq18JgCrJkbc+oGg PlAsIBtG1P6CivkEsEBAJz76nETSLJwSupWdOz3wz0uYKOYAjvM26cAQ6wNB9OlXacGV Ko4Q== X-Gm-Message-State: AIVw112Ds/EsJMoZnntMckfK2sMiaBKWQ+99jSHIgWYOj1tllfmsJJPd NMZfmqHtHWzp/c7aU5Y= X-Received: by 10.84.171.195 with SMTP id l61mr1452675plb.464.1501825487368; Thu, 03 Aug 2017 22:44:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:22 -0700 Message-Id: <20170804054426.10590-20-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH for-2.11 19/23] tcg/arm: Use constant pool for movi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 1 + tcg/arm/tcg-target.inc.c | 92 ++++++++++++++++++++++++++++++++++++++------= ---- 2 files changed, 75 insertions(+), 18 deletions(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 55de35a691..0f71a85a45 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -141,5 +141,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif +#define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 78603a19db..2736022d5a 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -23,6 +23,7 @@ */ =20 #include "elf.h" +#include "tcg-pool.inc.c" =20 int arm_arch =3D __ARM_ARCH; =20 @@ -203,9 +204,39 @@ static inline void reloc_pc24_atomic(tcg_insn_unit *co= de_ptr, tcg_insn_unit *tar static void patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - tcg_debug_assert(type =3D=3D R_ARM_PC24); tcg_debug_assert(addend =3D=3D 0); - reloc_pc24(code_ptr, (tcg_insn_unit *)value); + + if (type =3D=3D R_ARM_PC24) { + reloc_pc24(code_ptr, (tcg_insn_unit *)value); + } else if (type =3D=3D R_ARM_PC13) { + intptr_t diff =3D value - (uintptr_t)(code_ptr + 2); + tcg_insn_unit insn =3D *code_ptr; + bool u; + + if (diff >=3D -0xfff && diff <=3D 0xfff) { + u =3D (diff >=3D 0); + if (!u) { + diff =3D -diff; + } + } else { + int rd =3D extract32(insn, 12, 4); + int rt =3D rd =3D=3D TCG_REG_PC ? TCG_REG_TMP : rd; + assert(diff >=3D 0x1000 && diff < 0x100000); + /* add rt, pc, #high */ + *code_ptr++ =3D ((insn & 0xf0000000) | (1 << 25) | ARITH_ADD + | (TCG_REG_PC << 16) | (rt << 12) + | (20 << 7) | (diff >> 12)); + /* ldr rd, [rt, #low] */ + insn =3D deposit32(insn, 12, 4, rt); + diff &=3D 0xfff; + u =3D 1; + } + insn =3D deposit32(insn, 23, 1, u); + insn =3D deposit32(insn, 0, 12, diff); + *code_ptr =3D insn; + } else { + g_assert_not_reached(); + } } =20 #define TCG_CT_CONST_ARM 0x100 @@ -581,9 +612,20 @@ static inline void tcg_out_ld8s_r(TCGContext *s, int c= ond, TCGReg rt, tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0); } =20 +static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t ar= g) +{ + /* The 12-bit range on the ldr insn is sometimes a bit too small. + In order to get around that we require two insns, one of which + will usually be a nop, but may be replaced in patch_reloc. */ + new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0); + tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0); + tcg_out_nop(s); +} + static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg) { - int rot, opc, rn, diff; + int rot, diff, opc, sh1, sh2; + uint32_t tt0, tt1, tt2; =20 /* Check a single MOV/MVN before anything else. */ rot =3D encode_imm(arg); @@ -631,24 +673,30 @@ static void tcg_out_movi32(TCGContext *s, int cond, i= nt rd, uint32_t arg) return; } =20 - /* TODO: This is very suboptimal, we can easily have a constant - pool somewhere after all the instructions. */ + /* Look for sequences of two insns. If we have lots of 1's, we can + shorten the sequence by beginning with mvn and then clearing + higher bits with eor. */ + tt0 =3D arg; opc =3D ARITH_MOV; - rn =3D 0; - /* If we have lots of leading 1's, we can shorten the sequence by - beginning with mvn and then clearing higher bits with eor. */ - if (clz32(~arg) > clz32(arg)) { - opc =3D ARITH_MVN, arg =3D ~arg; + if (ctpop32(arg) > 16) { + tt0 =3D ~arg; + opc =3D ARITH_MVN; + } + sh1 =3D ctz32(tt0) & ~1; + tt1 =3D tt0 & ~(0xff << sh1); + sh2 =3D ctz32(tt1) & ~1; + tt2 =3D tt1 & ~(0xff << sh2); + if (tt2 =3D=3D 0) { + rot =3D ((32 - sh1) << 7) & 0xf00; + tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot); + rot =3D ((32 - sh2) << 7) & 0xf00; + tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd, + ((tt0 >> sh2) & 0xff) | rot); + return; } - do { - int i =3D ctz32(arg) & ~1; - rot =3D ((32 - i) << 7) & 0xf00; - tcg_out_dat_imm(s, cond, opc, rd, rn, ((arg >> i) & 0xff) | rot); - arg &=3D ~(0xff << i); =20 - opc =3D ARITH_EOR; - rn =3D rd; - } while (arg); + /* Otherwise, drop it into the constant pool. */ + tcg_out_movi_pool(s, cond, rd, arg); } =20 static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg= dst, @@ -2164,6 +2212,14 @@ static inline void tcg_out_movi(TCGContext *s, TCGTy= pe type, tcg_out_movi32(s, COND_AL, ret, arg); } =20 +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i =3D 0; i < count; ++i) { + p[i] =3D INSN_NOP; + } +} + /* Compute frame size via macros, to share between tcg_target_qemu_prologue and tcg_register_jit. */ =20 --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501826559322658.1406730713516; Thu, 3 Aug 2017 23:02:39 -0700 (PDT) Received: from localhost ([::1]:37170 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVgz-0003VE-Lq for importer@patchew.org; Fri, 04 Aug 2017 02:02:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59950) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPm-00047g-O0 for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPl-0003lj-Ii for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:50 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:34756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPl-0003k2-DJ for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:49 -0400 Received: by mail-pf0-x242.google.com with SMTP id t86so870351pfe.1 for ; Thu, 03 Aug 2017 22:44:49 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.47 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=Rd7IomQ0EbtfbSw4jt0TViOgH3Mjh2xbG5tbtxZaARg=; b=Ep2hcP5uysFbt3/hu4uGx6XiZ0SwCaPatBJGy6wY7ua55PWNQIfEKorRaTFprlwdgf KxZqndeyjFCJhauCDmPULb9CguXMrdQgk4nBfMat428AR2+v2/fDnTL9ad9IoPYwKZvl ZYQ8LGRDtUhr8NLEwOv5ZTllI2M1f7EtHr0ED3XmMHbSsEly7XdgnTd3gJZQgLrNgKb/ iDtDga5jyWs5pfPR5YV52V8evD72to8HBbisNFPM5vT/03leUd/ZkzYjj5pULZPOoIKl MYd9+BaEf9AnYxf0o80vINRxbnYkwJ+cJjIGl31wds0yTJHU/AbTLW1swqUUUVJg6+mm CXMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=Rd7IomQ0EbtfbSw4jt0TViOgH3Mjh2xbG5tbtxZaARg=; b=dr4frKlU55TPW8mW2v1eIQBIXmioHmWXaw5jmSr6+RZZ7wRXN2hPw6idwEEG6579xK zXSAeebzA+AN41oFgITHPQ6WBEMbybSC+BteXe2DftLrhN/XihgK6OcTencqDv6YM9ap DUi4ijwFL+J7g/cznwCghIWtt33j0CLDgaIUCovX+PetLFA0xAaEsTQWGovvypEik+oU NFHvV7trFDqdShhtI6SIokwRcSPUzS8T2eWoUpJ0gV9JtRBHLHd5L1ldniMZz6ksbPxH t4NP/C+CUYC5be+E1sLhdzEoKQACR4T9qI0ppssi8WKJNbGkuaDxGjpZUzPVBFCh/mZG O3/Q== X-Gm-Message-State: AHYfb5ghmM7I6HRSVuO/5gFuIUMLLQim4v66zK7qnlv24MZVGx/8y3wJ zP6iizhxzcyodPrPcT8= X-Received: by 10.84.238.140 with SMTP id v12mr878774plk.159.1501825488307; Thu, 03 Aug 2017 22:44:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:23 -0700 Message-Id: <20170804054426.10590-21-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH for-2.11 20/23] tcg/arm: Use constant pool for call X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 2736022d5a..db46aea38c 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1054,10 +1054,7 @@ static void tcg_out_goto(TCGContext *s, int cond, tc= g_insn_unit *addr) tcg_out_b(s, cond, disp); return; } - - assert(use_armv5t_instructions || (addri & 1) =3D=3D 0); - tcg_out_movi32(s, cond, TCG_REG_TMP, addri); - tcg_out_bx(s, cond, TCG_REG_TMP); + tcg_out_movi_pool(s, cond, TCG_REG_PC, addri); } =20 /* The call case is mostly used for helpers - so it's not unreasonable @@ -1081,9 +1078,9 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit= *addr) tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri); tcg_out_blx(s, COND_AL, TCG_REG_TMP); } else { + /* ??? Know that movi_pool emits exactly 2 insns. */ tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4); - tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4); - tcg_out32(s, addri); + tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri); } } =20 --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501826356471887.7549832910167; Thu, 3 Aug 2017 22:59:16 -0700 (PDT) Received: from localhost ([::1]:36844 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVdj-0000d4-3M for importer@patchew.org; Fri, 04 Aug 2017 01:59:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPp-0004Aj-8j for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPn-0003pL-4t for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:53 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:34931) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPm-0003ni-Sb for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:51 -0400 Received: by mail-pg0-x242.google.com with SMTP id l64so827436pge.2 for ; Thu, 03 Aug 2017 22:44:50 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.48 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=BU4sW2/jS3U9kafvCsjjv7mrMdhXGy1BHJABwdtD3GM=; b=CKgoTExP6G+RezUc98b+OCYkU1hMzIuLDHKflz4O8CaAGtw46tob5mRMMIv0nsXWIq cA9BrVeEjWZnEbDUZLihPg/GyG1CY6Up+IPMNtLDkVbNmyNidEY7zc7QdO2NwKDhyoQT E4BKtttsO4GG43P6GiBRnB1hfndy6T53Dt9qsoHMYeM1+yD0J3+Fu9DIvDrNqBkzi3px 8AUtFegcOXcxd8rNbZ5+7clkCN2rm6VE2j2QtgIJiQ3f++E8dOtukLVIPB2UbogEQy67 3zso/0kJ82aYsMg099mkFDpI8jFkhRk9bzi8pHtqtKiU80IRdvIt6tS5MquQEXW7rDRz x0kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=BU4sW2/jS3U9kafvCsjjv7mrMdhXGy1BHJABwdtD3GM=; b=DvBbKFSQ5q7+4ETG/yxgQNOD8iPYI6KZmmI8FmQYt00nb0HH9feZhgsBOsTwUbzmQX wvtppJCnCi4aSQ0yWQRI9VJUtB80kqDYpgDRyyYlFYKOabSV30xs2jwV6nmyiAwEMY7w 82omdYTV3IVYaPzY5ksx8LV6KJhFJs0TGa4tjIL10gt48+GCUAFQYj1C6uUSE/Ax/OWT Scbkvw4HQ0CDHWV9ndYBouhDFMDQ79BJdYQ4W9/7qW96+2CP/edcjaxXH3qPxncM7tPm 2C6eGJqXinakdnteiuV+kS2C2oj70XHI4LNRqR8I3S2sX/L/nvSlPSLYsRO2aGU+bzyH 7JVg== X-Gm-Message-State: AIVw1110FgWWV+rjvCRI7F0dTWLNGO+yCGK+Kq7/QYmHPSAmcPyIBakv x/2B/1r7d6dU/pecNuA= X-Received: by 10.84.236.70 with SMTP id h6mr1404523pln.339.1501825489467; Thu, 03 Aug 2017 22:44:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:24 -0700 Message-Id: <20170804054426.10590-22-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH for-2.11 21/23] tcg/ppc: Change TCG_REG_RA to TCG_REG_TB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" At this point the conversion is a wash. Loading of TB+ofs is smaller, but the actual return address from exit_tb is larger. There are a few more insns required to transition between TBs. But the expectation is that accesses to the constant pool will on the whole be smaller. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 273 +++++++++++++++++++++----------------------= ---- 1 file changed, 122 insertions(+), 151 deletions(-) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index d772faf7be..bc14d2c9c6 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -39,29 +39,8 @@ # define TCG_REG_TMP1 TCG_REG_R12 #endif =20 -/* For the 64-bit target, we don't like the 5 insn sequence needed to build - full 64-bit addresses. Better to have a base register to which we can - apply a 32-bit displacement. - - There are generally three items of interest: - (1) helper functions in the main executable, - (2) TranslationBlock data structures, - (3) the return address in the epilogue. - - For user-only, we USE_STATIC_CODE_GEN_BUFFER, so the code_gen_buffer - will be inside the main executable, and thus near enough to make a - pointer to the epilogue be within 2GB of all helper functions. - - For softmmu, we'll let the kernel choose the address of code_gen_buffer, - and odds are it'll be somewhere close to the main malloc arena, and so - a pointer to the epilogue will be within 2GB of the TranslationBlocks. - - For --enable-pie, everything will be kinda near everything else, - somewhere in high memory. - - Thus we choose to keep the return address in a call-saved register. */ -#define TCG_REG_RA TCG_REG_R31 -#define USE_REG_RA (TCG_TARGET_REG_BITS =3D=3D 64) +#define TCG_REG_TB TCG_REG_R31 +#define USE_REG_TB (TCG_TARGET_REG_BITS =3D=3D 64) =20 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */ #define SZP ((int)sizeof(void *)) @@ -614,50 +593,68 @@ static inline void tcg_out_shri64(TCGContext *s, TCGR= eg dst, TCGReg src, int c) tcg_out_rld(s, RLDICL, dst, src, 64 - c, c); } =20 -static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg) +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long arg, bool in_prologue) { - if (arg =3D=3D (int16_t) arg) { + intptr_t tb_diff; + int32_t high; + + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); + + if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { + arg =3D (int32_t)arg; + } + + /* Load 16-bit immediates with one insn. */ + if (arg =3D=3D (int16_t)arg) { tcg_out32(s, ADDI | TAI(ret, 0, arg)); - } else { + return; + } + + /* Load addresses within the TB with one insn. */ + tb_diff =3D arg - (intptr_t)s->code_gen_ptr; + if (!in_prologue && USE_REG_TB && tb_diff =3D=3D (int16_t)tb_diff) { + tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); + return; + } + + /* Load 32-bit immediates with two insns. */ + if (TCG_TARGET_REG_BITS =3D=3D 32 || arg =3D=3D (int32_t)arg) { tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); if (arg & 0xffff) { tcg_out32(s, ORI | SAI(ret, ret, arg)); } + return; } -} - -static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, - tcg_target_long arg) -{ - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); - if (type =3D=3D TCG_TYPE_I32 || arg =3D=3D (int32_t)arg) { - tcg_out_movi32(s, ret, arg); - } else if (arg =3D=3D (uint32_t)arg && !(arg & 0x8000)) { + if (arg =3D=3D (uint32_t)arg && !(arg & 0x8000)) { tcg_out32(s, ADDI | TAI(ret, 0, arg)); tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); - } else { - int32_t high; + return; + } =20 - if (USE_REG_RA) { - intptr_t diff =3D arg - (intptr_t)tb_ret_addr; - if (diff =3D=3D (int32_t)diff) { - tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_RA, diff); - return; - } - } + /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */ + if (!in_prologue && USE_REG_TB && tb_diff =3D=3D (int32_t)tb_diff) { + tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff); + return; + } =20 - high =3D arg >> 31 >> 1; - tcg_out_movi32(s, ret, high); - if (high) { - tcg_out_shli64(s, ret, ret, 32); - } - if (arg & 0xffff0000) { - tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); - } - if (arg & 0xffff) { - tcg_out32(s, ORI | SAI(ret, ret, arg)); - } + high =3D arg >> 31 >> 1; + tcg_out_movi(s, TCG_TYPE_I32, ret, high); + if (high) { + tcg_out_shli64(s, ret, ret, 32); } + if (arg & 0xffff0000) { + tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); + } + if (arg & 0xffff) { + tcg_out32(s, ORI | SAI(ret, ret, arg)); + } +} + +static inline void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long arg) +{ + tcg_out_movi_int(s, type, ret, arg, false); } =20 static bool mask_operand(uint32_t c, int *mb, int *me) @@ -1293,49 +1290,43 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) tcg_out32(s, insn); } =20 -#ifdef __powerpc64__ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t addr) { - tcg_insn_unit i1, i2; - uint64_t pair; - intptr_t diff =3D addr - jmp_addr; - - if (in_range_b(diff)) { - i1 =3D B | (diff & 0x3fffffc); - i2 =3D NOP; - } else if (USE_REG_RA) { - intptr_t lo, hi; - diff =3D addr - (uintptr_t)tb_ret_addr; - lo =3D (int16_t)diff; - hi =3D (int32_t)(diff - lo); - tcg_debug_assert(diff =3D=3D hi + lo); - i1 =3D ADDIS | TAI(TCG_REG_TMP1, TCG_REG_RA, hi >> 16); - i2 =3D ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, lo); - } else { - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32 || addr =3D=3D (int= 32_t)addr); - i1 =3D ADDIS | TAI(TCG_REG_TMP1, 0, addr >> 16); - i2 =3D ORI | SAI(TCG_REG_TMP1, TCG_REG_TMP1, addr); - } + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_insn_unit i1, i2; + intptr_t tb_diff =3D addr - tc_ptr; + intptr_t br_diff =3D addr - (jmp_addr + 4); + uint64_t pair; + + /* This does not exercise the range of the branch, but we do + still need to be able to load the new value of TCG_REG_TB. + But this does still happen quite often. */ + if (tb_diff =3D=3D (int16_t)tb_diff) { + i1 =3D ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff); + i2 =3D B | (br_diff & 0x3fffffc); + } else { + intptr_t lo =3D (int16_t)tb_diff; + intptr_t hi =3D (int32_t)(tb_diff - lo); + assert(tb_diff =3D=3D hi + lo); + i1 =3D ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16); + i2 =3D ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo); + } #ifdef HOST_WORDS_BIGENDIAN - pair =3D (uint64_t)i1 << 32 | i2; + pair =3D (uint64_t)i1 << 32 | i2; #else - pair =3D (uint64_t)i2 << 32 | i1; + pair =3D (uint64_t)i2 << 32 | i1; #endif =20 - atomic_set((uint64_t *)jmp_addr, pair); - flush_icache_range(jmp_addr, jmp_addr + 8); -} -#else -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, - uintptr_t addr) -{ - intptr_t diff =3D addr - jmp_addr; - tcg_debug_assert(in_range_b(diff)); - atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc)); - flush_icache_range(jmp_addr, jmp_addr + 4); + atomic_set((uint64_t *)jmp_addr, pair); + flush_icache_range(jmp_addr, jmp_addr + 8); + } else { + intptr_t diff =3D addr - jmp_addr; + tcg_debug_assert(in_range_b(diff)); + atomic_set((uint32_t *)jmp_addr, B | (diff & 0x3fffffc)); + flush_icache_range(jmp_addr, jmp_addr + 4); + } } -#endif =20 static void tcg_out_call(TCGContext *s, tcg_insn_unit *target) { @@ -1897,44 +1888,20 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 #ifndef CONFIG_SOFTMMU if (guest_base) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, = true); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR); - - if (USE_REG_RA) { -#ifdef _CALL_AIX - /* Make the caller load the value as the TOC into R2. */ - tb_ret_addr =3D s->code_ptr + 2; - desc[1] =3D tb_ret_addr; - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_RA, TCG_REG_R2); - tcg_out32(s, BCCTR | BO_ALWAYS); -#elif defined(_CALL_ELF) && _CALL_ELF =3D=3D 2 - /* Compute from the incoming R12 value. */ - tb_ret_addr =3D s->code_ptr + 2; - tcg_out32(s, ADDI | TAI(TCG_REG_RA, TCG_REG_R12, - tcg_ptr_byte_diff(tb_ret_addr, s->code_buf= ))); - tcg_out32(s, BCCTR | BO_ALWAYS); -#else - /* Reserve max 5 insns for the constant load. */ - tb_ret_addr =3D s->code_ptr + 6; - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)tb_ret_addr); - tcg_out32(s, BCCTR | BO_ALWAYS); - while (s->code_ptr < tb_ret_addr) { - tcg_out32(s, NOP); - } -#endif - } else { - tcg_out32(s, BCCTR | BO_ALWAYS); - tb_ret_addr =3D s->code_ptr; + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs= [1]); } + tcg_out32(s, BCCTR | BO_ALWAYS); =20 /* Epilogue */ - tcg_debug_assert(tb_ret_addr =3D=3D s->code_ptr); - s->code_gen_epilogue =3D tb_ret_addr; + s->code_gen_epilogue =3D tb_ret_addr =3D s->code_ptr; =20 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFS= ET); for (i =3D 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { @@ -1954,44 +1921,48 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc= , const TCGArg *args, =20 switch (opc) { case INDEX_op_exit_tb: - if (USE_REG_RA) { - ptrdiff_t disp =3D tcg_pcrel_diff(s, tb_ret_addr); - - /* Use a direct branch if we can, otherwise use the value in R= A. - Note that the direct branch is always backward, thus we need - to account for the possibility of 5 insns from the movi. */ - if (!in_range_b(disp - 20)) { - tcg_out32(s, MTSPR | RS(TCG_REG_RA) | CTR); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]); - tcg_out32(s, BCCTR | BO_ALWAYS); - break; - } - } tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]); tcg_out_b(s, 0, tb_ret_addr); break; case INDEX_op_goto_tb: - tcg_debug_assert(s->tb_jmp_insn_offset); - /* Direct jump. */ -#ifdef __powerpc64__ - /* Ensure the next insns are 8-byte aligned. */ - if ((uintptr_t)s->code_ptr & 7) { - tcg_out32(s, NOP); - } - s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s); - /* To be replaced by either a branch+nop or a load into TMP1. */ - s->code_ptr +=3D 2; - tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); + if (s->tb_jmp_insn_offset) { + /* Direct jump. */ + if (TCG_TARGET_REG_BITS =3D=3D 64) { + /* Ensure the next insns are 8-byte aligned. */ + if ((uintptr_t)s->code_ptr & 7) { + tcg_out32(s, NOP); + } + s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s= ); + tcg_out32(s, ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, 0)); + tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, 0)); + } else { + s->tb_jmp_insn_offset[args[0]] =3D tcg_current_code_size(s= ); + tcg_out32(s, B); + s->tb_jmp_reset_offset[args[0]] =3D tcg_current_code_size(= s); + break; + } + } else { + /* Indirect jump. */ + tcg_debug_assert(s->tb_jmp_insn_offset =3D=3D NULL); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TB, 0, + (intptr_t)(s->tb_jmp_insn_offset + args[0])); + } + tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); tcg_out32(s, BCCTR | BO_ALWAYS); -#else - /* To be replaced by a branch. */ - s->code_ptr++; -#endif - s->tb_jmp_reset_offset[args[0]] =3D tcg_current_code_size(s); + s->tb_jmp_reset_offset[args[0]] =3D c =3D tcg_current_code_size(s); + if (USE_REG_TB) { + /* For the unlinked case, need to reset TCG_REG_TB. */ + c =3D -c; + assert(c =3D=3D (int16_t)c); + tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, c)); + } break; case INDEX_op_goto_ptr: tcg_out32(s, MTSPR | RS(args[0]) | CTR); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, 0); + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]); + } + tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); tcg_out32(s, BCCTR | BO_ALWAYS); break; case INDEX_op_br: @@ -2761,8 +2732,8 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ #endif tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */ - if (USE_REG_RA) { - tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return addr = */ + if (USE_REG_TB) { + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */ } } =20 --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=kDaZKPZ+qGIvGuQ/c4u6UAvwkpHrBioMfnL6xFXBg9g=; b=pOjkU5HA223wXExm16jV/jqQnCRKEHwir3GPcuHOTR/W/7CePXu0ra8BaL8uoX2YjO PfIcDbinEmLNH9Z4POgTC68GHa4457T0XEPhxldMyU0j5eFvKr9HyMHwES7b85+eWaDB yPY/8coCwnNBFN/imQyTDpt/w7NvzCJLicfxPUAr9NHtBamBgttJTS16zVH/O9VERheJ Iau+NtGcT7lmNanPnPKoyIluOJE195/PvFtf6zY3uGfl0SYGVpCS8rHfEctMqD7B65fs ZOnS99JVzeanChALleRylWt+u9FygM+gwS0kRkntTViP06MoUjFRg6p9u/J08wsDss+r NwSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=kDaZKPZ+qGIvGuQ/c4u6UAvwkpHrBioMfnL6xFXBg9g=; b=jaiFFdJkuJNw5hw7w+49NOVwvIyPDzEbMjzxZuyPX1RgxQZV7KgBPI/IX7Ny9hqn/j x/kk0pcO0EX1QOlTfKyEH76yJ1Okn76gFZlAaZOYbOfwX9nRiyzz4SHtw7XiFCe4HKTq heTxTaXaxPVyC6sc96dipAYUo/7F0xLo7EpYeFKTC0TdSupOdYWLoISSbg0kD+wRli9Z a3/Jt870iwXKYSMXwKNQm1/QXsS6yvKEIEPKFKItYfHarE/6a+wZfTWItLPbbdqUfnV3 lJ4va0rYdmgm1lmYM1Mo59Nj3QrPqUx3fXuiT0Nf6bvnf9RPdUpaad2mwlckRcmhc4/i xMBw== X-Gm-Message-State: AIVw113kSThGX+cwJgsorrYZhSqLDPwslH3RQ+W47ZFCSdnyZIdqWhEM +xTvtVVLGdUsc//Vd3I= X-Received: by 10.84.139.40 with SMTP id 37mr1422892plq.153.1501825490148; Thu, 03 Aug 2017 22:44:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:25 -0700 Message-Id: <20170804054426.10590-23-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH for-2.11 22/23] tcg/ppc: Look for shifted constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index bc14d2c9c6..4b32809217 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -598,6 +598,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, { intptr_t tb_diff; int32_t high; + int lsb; =20 tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); =20 @@ -638,6 +639,14 @@ static void tcg_out_movi_int(TCGContext *s, TCGType ty= pe, TCGReg ret, return; } =20 + lsb =3D ctz64(arg); + high =3D arg >> lsb; + if (arg =3D=3D (int16_t)arg) { + tcg_out32(s, ADDI | TAI(ret, 0, high)); + tcg_out_shli64(s, ret, ret, lsb); + return; + } + high =3D arg >> 31 >> 1; tcg_out_movi(s, TCG_TYPE_I32, ret, high); if (high) { --=20 2.13.3 From nobody Mon May 6 15:23:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501826073193635.8649077272298; Thu, 3 Aug 2017 22:54:33 -0700 (PDT) Received: from localhost ([::1]:36696 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVZ9-00047a-Qq for importer@patchew.org; Fri, 04 Aug 2017 01:54:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60050) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVPp-0004Av-GF for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVPo-0003sq-HR for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:53 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:33067) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVPo-0003rE-CI for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:44:52 -0400 Received: by mail-pg0-x242.google.com with SMTP id u185so854016pgb.0 for ; Thu, 03 Aug 2017 22:44:52 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id o14sm1061063pfi.158.2017.08.03.22.44.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:44:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=0CbqG/jCmy9nKLrHCKRdJkneOc8A7e+qahK61diRF3I=; b=aTXA2AuVuKHnyWgBZErorcOBW2XL19Kk96+n1FjxeZD+16yMR28WaEaoIg3BA+BBZJ 99+ojCfYcUyItJTPUYUXDvAb47OjJz97RABPUoweaaSbx1IAjYW5hHZsgEl6LzU4gPtM bQETtCFDkmZQ+Por1fID/39ojONCAOymQjbycx1AuXKJDE1ewGNzZyBpxbDC7LW2LCta iRP/kxEGPsoGgD4MIS/jQrUCYDSWLHXAnZaglxoniBnS62YdgK4R4Jt1CfSt6/Qd/OJ4 cDGNELt1TwWxV9zEtMYWo0lFVolQl2ZxkUah6qZFMmh7QiKqNyY+bvL12Nc3D11NkRLX bCGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=0CbqG/jCmy9nKLrHCKRdJkneOc8A7e+qahK61diRF3I=; b=eLUoDIRnKcoacqJZp3FcG2jBZu3QmY+c85hrrsRzb1a5D351nZS/alFevTORMhIyR4 Ywu+++yPlx0wTAsOE0hxTzxnSIBdCAb6ECM7e33QESVqmxda5s5An+BAQpiLL9W5US7p fDH8rFcpmUXbEnduTzl6Ki8hNT7kpqtWXybwv/Rpd3A9Wf+qEvVRjLBpSpLIW+2cZQUA M9myiD/PvDBYwmLRFCy5tXbUBYpj2eFVnmgrpqkhNO34Fgo56V49HdQKyPiI/WNVcnbh wFtAeeRQewMxPIne6/DA/YSgV/ZQQ8o7lPMXuHs//lirRXmN+/n6rGh5XghDMUwyw3yI PFvg== X-Gm-Message-State: AIVw110v4xIvmGJBp7EyM18ekJeymn0cLyCWnVNweGbFHXfgimADernJ HFgldIzaKq85Gqd4Fdc= X-Received: by 10.84.195.131 with SMTP id j3mr1361597pld.147.1501825491280; Thu, 03 Aug 2017 22:44:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:44:26 -0700 Message-Id: <20170804054426.10590-24-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804054426.10590-1-rth@twiddle.net> References: <20170804054426.10590-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH for-2.11 23/23] tcg/ppc: Use constant pool for movi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.h | 1 + tcg/ppc/tcg-target.inc.c | 34 ++++++++++++++++++++++++++++++---- 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index c1226ea5b6..e10d7e4411 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -130,5 +130,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uin= tptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif +#define TCG_TARGET_NEED_POOL_LABELS =20 #endif diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 4b32809217..7598157e5f 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -22,6 +22,9 @@ * THE SOFTWARE. */ =20 +#include "elf.h" +#include "tcg-pool.inc.c" + #if defined _CALL_DARWIN || defined __APPLE__ #define TCG_TARGET_CALL_DARWIN #endif @@ -58,8 +61,6 @@ =20 static tcg_insn_unit *tb_ret_addr; =20 -#include "elf.h" - bool have_isa_2_06; bool have_isa_3_00; =20 @@ -224,9 +225,12 @@ static inline void tcg_out_bc_noaddr(TCGContext *s, in= t insn) static void patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - tcg_insn_unit *target =3D (tcg_insn_unit *)value; + tcg_insn_unit *target; + tcg_insn_unit old; + + value +=3D addend; + target =3D (tcg_insn_unit *)value; =20 - tcg_debug_assert(addend =3D=3D 0); switch (type) { case R_PPC_REL14: reloc_pc14(code_ptr, target); @@ -234,6 +238,12 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int t= ype, case R_PPC_REL24: reloc_pc24(code_ptr, target); break; + case R_PPC_ADDR16: + assert(value =3D=3D (int16_t)value); + old =3D *code_ptr; + old =3D deposit32(old, 0, 16, value); + *code_ptr =3D old; + break; default: tcg_abort(); } @@ -647,6 +657,14 @@ static void tcg_out_movi_int(TCGContext *s, TCGType ty= pe, TCGReg ret, return; } =20 + /* Use the constant pool, if possible. */ + if (!in_prologue && USE_REG_TB) { + new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, + -(intptr_t)s->code_gen_ptr); + tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); + return; + } + high =3D arg >> 31 >> 1; tcg_out_movi(s, TCG_TYPE_I32, ret, high); if (high) { @@ -1829,6 +1847,14 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is_64) #endif } =20 +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i =3D 0; i < count; ++i) { + p[i] =3D NOP; + } +} + /* Parameters for function call generation, used in tcg.c. */ #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_EXTEND_ARGS 1 --=20 2.13.3