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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id m5sm1053099pfg.22.2017.08.03.22.28.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:28:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=LK6jCXZlW11PmWP2G3sEq1hN5ofU9z75iA45nh/Sjyk=; b=OFW6a+M+cVqKCoKjSTYNr3GSrffXDMXbwBXWGjpQnDd1DmAOQvi1Mes7d4LfTNcNry V2ZnSg0mpkxW31rxC81CreNqBO0ilAx5tXfOB7adRbqFBKG2Hsn1UQHECzS3w1nylBCl 4AGVzmzUvbpnQ0snrd9ReKmhb74JhtVWd08AKjZsDDURbLqA97sctusRpiko4QJ6sglI zAH75n+We3gdt/YYt8VWjp2z+Xvm8aMqWD9oCw7mqbiKrIOBJZbjQrsD5BsS3s7f+bHi LF2cBTWplU+72+AloXah8EPtOeQFbQ4pHbZCY9rh18gcQkeU1L7rrECU1zunRvCsyDAk F3zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=LK6jCXZlW11PmWP2G3sEq1hN5ofU9z75iA45nh/Sjyk=; b=kKcI8vI9SbJeuKhIo+sgZ2OQEi2FG03RJ+TQiJbWjeaEY0CZogpJIn7uhZfhp2p+iW 179/RBkU8MK4jOtZr39e0dE0K812MAYt/05IghZedevXU8KzYnIIf9/utFw2HphksrLn SSqiRjmvCCZdMBAoIZMqfs6n5ZQLMLjxbm5Tgb88K5tvl18VtbeMTZAnL9uEsYHqTwLd /VDSMPYGvhjTByfQzNxF1+/0jnZuFZ3cJwNNS0CeWoSshvZ0fPUab6qW0WYhb7mh8b6p VWS3PgpjidGRW5hCLv2qh9cF/tfXvP/NivQVKq/JIFyIDndSK/BBmzTdoBR/F6J1Mamh c5iQ== X-Gm-Message-State: AIVw113e+pKucupOBLaeCQ2D3UA1d4dB0/Pbm724PMqF5CHFsLtUQasb 6upRCa9X9FfVpnZVrts= X-Received: by 10.84.151.68 with SMTP id i62mr1367424pli.225.1501824517184; Thu, 03 Aug 2017 22:28:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:28:23 -0700 Message-Id: <20170804052833.10187-2-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804052833.10187-1-rth@twiddle.net> References: <20170804052833.10187-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL for-2.10 1/3] tcg/arm: Fix runtime overalignment test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Patch 85aa80813dd changed the IF emitting the TST instruction, but failed to change the ?: converting CMP to CMPEQ, so the result of the TST is ignored. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index d1793ec77d..37efcf06af 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1223,7 +1223,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg = addrlo, TCGReg addrhi, /* Load the tlb addend. */ tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, add_off); =20 - tcg_out_dat_reg(s, (s_bits ? COND_EQ : COND_AL), ARITH_CMP, 0, + tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, 0, TCG_REG_R0, TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BIT= S)); =20 if (TARGET_LONG_BITS =3D=3D 64) { --=20 2.13.3 From nobody Sat Apr 27 19:54:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501824958181138.71382684762227; Thu, 3 Aug 2017 22:35:58 -0700 (PDT) Received: from localhost ([::1]:35884 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVHA-0005xW-DD for importer@patchew.org; Fri, 04 Aug 2017 01:35:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36238) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVA9-0007TI-Id for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVA7-00017l-MT for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:41 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:33122) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVA7-00016E-EO for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:39 -0400 Received: by mail-pf0-x243.google.com with SMTP id c65so839069pfl.0 for ; Thu, 03 Aug 2017 22:28:39 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id m5sm1053099pfg.22.2017.08.03.22.28.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:28:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=1AIMEQXWdR4xXK0tyNaKaDMVCufMu0reV9VdCroiOK0=; b=oTZ2zvP8Sfc3PlftYG7GR1Pqm2E2T/8EIzr5QnGNUCWPlMeq7HlS3ifeZhefhl9o/r si4gMvHP4An+yKlWuVbu6npw3mwDFZPeXevIaPjCJQMR3hcCnEob3BC0VPb0NIhERlym AAZ+po/MDgVp6OcarGGDqfP3TGf+9iwcgCQw6jolDG3t+s5ZV/JCQW1PUnp6xZD8oxzw NPX7UGPCqNEe5zxCP1BMufb2JG92jGvuGmi0L6q+PWNo9ADShqR67m3I06K15e1I50eJ 2BJytFomcE3Omj6KXEHY+55q6BtuxZHoDSf5R5GixJ0zVMNNHUif5K7YRsxpCHudURro AOXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=1AIMEQXWdR4xXK0tyNaKaDMVCufMu0reV9VdCroiOK0=; b=Wou3kEgVb1i2Pkp2+wuTLiERZ0jOhLH4Tbr/pjYCkp/JCbrZD37E2KFXztdvtlCUgK 9142sXFAKLnuKc4LHxmNHqjCqVG8nNlJ+NftSgSmJHloYZtjcBhR1gjW058vE7w6QRAG 22gDfDDHu5wp3mkgy5UyBfPma1nJKymCu8iwMCHuMomvkKEWjzpPyHdSGHfWRerTAWvd xm2kP6Gs1EMJRakZFxl58a0p7hQja7l0J1LGL/lpEtzTdnjPPG28qJnPy/O5fWzlt+zG M8e1vhvRyVDYYVJH8QI6wUoXKwMuHPrMTLEc0RfJ+BOXMJTeYqR3xUaBtSY+0K7Lq4zV +FyA== X-Gm-Message-State: AIVw113HL4nQqpNDJhjFLXL/VJkI+ZvTBxXxTP+zRfHytfOQNyCg3Omx U2fPO4B1cwsUQG/PkoA= X-Received: by 10.84.234.8 with SMTP id m8mr1340247plk.1.1501824518216; Thu, 03 Aug 2017 22:28:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:28:24 -0700 Message-Id: <20170804052833.10187-3-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804052833.10187-1-rth@twiddle.net> References: <20170804052833.10187-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 1/8] tcg/s390: Fully convert tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use a switch instead of searching a table. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 278 +++++++++++++++++++++++++-----------------= ---- 1 file changed, 154 insertions(+), 124 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 5d7083e90c..d34649eb13 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -2246,134 +2246,164 @@ static inline void tcg_out_op(TCGContext *s, TCGO= pcode opc, } } =20 -static const TCGTargetOpDef s390_op_defs[] =3D { - { INDEX_op_exit_tb, { } }, - { INDEX_op_goto_tb, { } }, - { INDEX_op_br, { } }, - { INDEX_op_goto_ptr, { "r" } }, - - { INDEX_op_ld8u_i32, { "r", "r" } }, - { INDEX_op_ld8s_i32, { "r", "r" } }, - { INDEX_op_ld16u_i32, { "r", "r" } }, - { INDEX_op_ld16s_i32, { "r", "r" } }, - { INDEX_op_ld_i32, { "r", "r" } }, - { INDEX_op_st8_i32, { "r", "r" } }, - { INDEX_op_st16_i32, { "r", "r" } }, - { INDEX_op_st_i32, { "r", "r" } }, - - { INDEX_op_add_i32, { "r", "r", "ri" } }, - { INDEX_op_sub_i32, { "r", "0", "ri" } }, - { INDEX_op_mul_i32, { "r", "0", "rK" } }, - - { INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } }, - { INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } }, - - { INDEX_op_and_i32, { "r", "0", "ri" } }, - { INDEX_op_or_i32, { "r", "0", "rO" } }, - { INDEX_op_xor_i32, { "r", "0", "rX" } }, - - { INDEX_op_neg_i32, { "r", "r" } }, - - { INDEX_op_shl_i32, { "r", "0", "ri" } }, - { INDEX_op_shr_i32, { "r", "0", "ri" } }, - { INDEX_op_sar_i32, { "r", "0", "ri" } }, - - { INDEX_op_rotl_i32, { "r", "r", "ri" } }, - { INDEX_op_rotr_i32, { "r", "r", "ri" } }, - - { INDEX_op_ext8s_i32, { "r", "r" } }, - { INDEX_op_ext8u_i32, { "r", "r" } }, - { INDEX_op_ext16s_i32, { "r", "r" } }, - { INDEX_op_ext16u_i32, { "r", "r" } }, - - { INDEX_op_bswap16_i32, { "r", "r" } }, - { INDEX_op_bswap32_i32, { "r", "r" } }, - - { INDEX_op_add2_i32, { "r", "r", "0", "1", "rA", "r" } }, - { INDEX_op_sub2_i32, { "r", "r", "0", "1", "rA", "r" } }, - - { INDEX_op_brcond_i32, { "r", "rC" } }, - { INDEX_op_setcond_i32, { "r", "r", "rC" } }, - { INDEX_op_movcond_i32, { "r", "r", "rC", "r", "0" } }, - { INDEX_op_deposit_i32, { "r", "rZ", "r" } }, - { INDEX_op_extract_i32, { "r", "r" } }, - - { INDEX_op_qemu_ld_i32, { "r", "L" } }, - { INDEX_op_qemu_ld_i64, { "r", "L" } }, - { INDEX_op_qemu_st_i32, { "L", "L" } }, - { INDEX_op_qemu_st_i64, { "L", "L" } }, - - { INDEX_op_ld8u_i64, { "r", "r" } }, - { INDEX_op_ld8s_i64, { "r", "r" } }, - { INDEX_op_ld16u_i64, { "r", "r" } }, - { INDEX_op_ld16s_i64, { "r", "r" } }, - { INDEX_op_ld32u_i64, { "r", "r" } }, - { INDEX_op_ld32s_i64, { "r", "r" } }, - { INDEX_op_ld_i64, { "r", "r" } }, - - { INDEX_op_st8_i64, { "r", "r" } }, - { INDEX_op_st16_i64, { "r", "r" } }, - { INDEX_op_st32_i64, { "r", "r" } }, - { INDEX_op_st_i64, { "r", "r" } }, - - { INDEX_op_add_i64, { "r", "r", "ri" } }, - { INDEX_op_sub_i64, { "r", "0", "ri" } }, - { INDEX_op_mul_i64, { "r", "0", "rK" } }, - - { INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } }, - { INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } }, - { INDEX_op_mulu2_i64, { "b", "a", "0", "r" } }, - - { INDEX_op_and_i64, { "r", "0", "ri" } }, - { INDEX_op_or_i64, { "r", "0", "rO" } }, - { INDEX_op_xor_i64, { "r", "0", "rX" } }, - - { INDEX_op_neg_i64, { "r", "r" } }, - - { INDEX_op_shl_i64, { "r", "r", "ri" } }, - { INDEX_op_shr_i64, { "r", "r", "ri" } }, - { INDEX_op_sar_i64, { "r", "r", "ri" } }, - - { INDEX_op_rotl_i64, { "r", "r", "ri" } }, - { INDEX_op_rotr_i64, { "r", "r", "ri" } }, - - { INDEX_op_ext8s_i64, { "r", "r" } }, - { INDEX_op_ext8u_i64, { "r", "r" } }, - { INDEX_op_ext16s_i64, { "r", "r" } }, - { INDEX_op_ext16u_i64, { "r", "r" } }, - { INDEX_op_ext32s_i64, { "r", "r" } }, - { INDEX_op_ext32u_i64, { "r", "r" } }, - - { INDEX_op_ext_i32_i64, { "r", "r" } }, - { INDEX_op_extu_i32_i64, { "r", "r" } }, - - { INDEX_op_bswap16_i64, { "r", "r" } }, - { INDEX_op_bswap32_i64, { "r", "r" } }, - { INDEX_op_bswap64_i64, { "r", "r" } }, - - { INDEX_op_clz_i64, { "r", "r", "ri" } }, - - { INDEX_op_add2_i64, { "r", "r", "0", "1", "rA", "r" } }, - { INDEX_op_sub2_i64, { "r", "r", "0", "1", "rA", "r" } }, - - { INDEX_op_brcond_i64, { "r", "rC" } }, - { INDEX_op_setcond_i64, { "r", "r", "rC" } }, - { INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } }, - { INDEX_op_deposit_i64, { "r", "0", "r" } }, - { INDEX_op_extract_i64, { "r", "r" } }, - - { INDEX_op_mb, { } }, - { -1 }, -}; - static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - int i, n =3D ARRAY_SIZE(s390_op_defs); + static const TCGTargetOpDef r =3D { .args_ct_str =3D { "r" } }; + static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; + static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; + static const TCGTargetOpDef L_L =3D { .args_ct_str =3D { "L", "L" } }; + static const TCGTargetOpDef r_rC =3D { .args_ct_str =3D { "r", "rC" } = }; + static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; + static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; + static const TCGTargetOpDef r_0_rK =3D { .args_ct_str =3D { "r", "0", = "rK" } }; + static const TCGTargetOpDef r_0_rO =3D { .args_ct_str =3D { "r", "0", = "rO" } }; + static const TCGTargetOpDef r_0_rX =3D { .args_ct_str =3D { "r", "0", = "rX" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return &r_r; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + return &r_r_ri; + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + return &r_0_ri; + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + return &r_0_rK; + case INDEX_op_or_i32: + case INDEX_op_or_i64: + return &r_0_rO; + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + return &r_0_rX; + case INDEX_op_and_i32: + case INDEX_op_and_i64: + return &r_0_ri; + + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + return &r_0_ri; + + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + return &r_r_ri; + + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + return &r_r_ri; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return &r_rC; + + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + return &r_r; + + case INDEX_op_clz_i64: + return &r_r_ri; + + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_i64: + return &r_L; + case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_i32: + return &L_L; =20 - for (i =3D 0; i < n; ++i) { - if (s390_op_defs[i].op =3D=3D op) { - return &s390_op_defs[i]; + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + { + static const TCGTargetOpDef dep + =3D { .args_ct_str =3D { "r", "rZ", "r" } }; + return &dep; } + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + { + static const TCGTargetOpDef setc + =3D { .args_ct_str =3D { "r", "r", "rC" } }; + return &setc; + } + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: + { + static const TCGTargetOpDef movc + =3D { .args_ct_str =3D { "r", "r", "rC", "r", "0" } }; + return &movc; + } + case INDEX_op_div2_i32: + case INDEX_op_div2_i64: + case INDEX_op_divu2_i32: + case INDEX_op_divu2_i64: + { + static const TCGTargetOpDef div2 + =3D { .args_ct_str =3D { "b", "a", "0", "1", "r" } }; + return &div2; + } + case INDEX_op_mulu2_i64: + { + static const TCGTargetOpDef mul2 + =3D { .args_ct_str =3D { "b", "a", "0", "r" } }; + return &mul2; + } + case INDEX_op_add2_i32: + case INDEX_op_add2_i64: + case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: + { + static const TCGTargetOpDef arith2 + =3D { .args_ct_str =3D { "r", "r", "0", "1", "rA", "r" } }; + return &arith2; + } + + default: + break; } return NULL; } --=20 2.13.3 From nobody Sat Apr 27 19:54:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501824795483982.4420312976771; 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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id m5sm1053099pfg.22.2017.08.03.22.28.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:28:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7/4GzL9wpw32MSXX43rRby94r1xXISy1VtpRt7eg3j0=; b=JuTXDBuW3RX6Ife9MImOR/QUNlmOY83/TtYOZ0NEanUQPkXaOryJcKOgG9NOLfBDNI z0u6eQS0DqmPtTPdyHgkT8+3oytWGbjnYKZNYP9ofT8stn/JX/NNaTLqNe1IFslCpRD8 7ds+B/eostRAYsbo+PEYk0bRoO9vHQ3ooz40PW3QmA7IT0KnMFZXlTjsIoIeTbdFZfKR wAPvkOAOW9WYbctPWZOMZX+BWeFK7bEUFIVGgkEL3qtXz9z2C+oRdvzCZLk5EJRf0kfm uGvyZbKyNnjLu67oTYtqSPhdjT34p9LnJ28Km6kTXswI+IRWVroMn1zDWz/lstde/+j2 xFBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=7/4GzL9wpw32MSXX43rRby94r1xXISy1VtpRt7eg3j0=; b=Dv9LtN6zHIaWAFZQb6gIycI83r6sUPLzExtdDJVL/0zd7i+hlx9zI4I2OiN+DrnRjr ahGcl0JBoTFYAIWP3Gko4G9mvHXBmct3s/EHpLAJvzDIzYy8qu2/SDH/ryg+EFKd1zc8 hpkTIYtIvvg9ojbj8s4uaziIzGEZX8kx6DgTVrpe08r71PLIz6CQZQgkDBhcLAlvZ7K7 bTdWe+qelrU9nAEbb05UK9yXJuEDAN7yqVKKIH9opfJtkjG/j5Hxtq5uxvuyEXQwAtIK JL18j4st6VFBSN6ogQ29ig0m0upA5MzMMuM+D4ZsTkCq4xX4xgjbkP30NJEv8C6n2jlk TVDA== X-Gm-Message-State: AIVw112S3xk5tadJqVkpYJSnlOOYvYCGiglfxFsW3SI5v93OBG26tEdk cEuECogBbQnJNkpKnHE= X-Received: by 10.84.174.67 with SMTP id q61mr1367522plb.469.1501824519388; Thu, 03 Aug 2017 22:28:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:28:25 -0700 Message-Id: <20170804052833.10187-4-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804052833.10187-1-rth@twiddle.net> References: <20170804052833.10187-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL for-2.10 2/3] target/s390x: Fix CSST for 16-byte store X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Found by Coverity (CID 1378273). Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reported-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target/s390x/mem_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index cdc78aa3d4..c71dce4b1e 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1580,6 +1580,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3= , uint64_t a1, uint64_t a2) cpu_stq_data_ra(env, a2 + 0, svh, ra); cpu_stq_data_ra(env, a2 + 8, svl, ra); } + break; default: g_assert_not_reached(); } --=20 2.13.3 From nobody Sat Apr 27 19:54:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501824797251722.9588205009502; Thu, 3 Aug 2017 22:33:17 -0700 (PDT) Received: from localhost ([::1]:35744 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVEZ-00036o-RK for importer@patchew.org; Fri, 04 Aug 2017 01:33:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36297) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVAB-0007Tn-3o for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVA9-0001Bt-QU for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:43 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:34321) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVA9-0001Aq-JJ for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:41 -0400 Received: by mail-pf0-x243.google.com with SMTP id t86so835766pfe.1 for ; Thu, 03 Aug 2017 22:28:41 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id m5sm1053099pfg.22.2017.08.03.22.28.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:28:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=vUxIavbcZGSnXzzqLMLtqCsSyL9AzS8IIPH9T9Nmf5w=; b=ksiUxa6pD9Sbp6gz8teq6f3HLVedfh1sgQ7/sp0GxCwKQXfpx367Jd6IdD1P5ZMsyi XJxX992dajoRDINdVtR2NxrZoHkY8bOd8QXEa+kLnCdtqBHQxfAIMwr5e0OmAlUAgVdm g4PNwiBf6Szt+HgVnwXhKQ67bMtqQ+tpo7npocIHbs0vcUY/e9c3uu8m1Y6Lent+tcWe SmMydbGmgWnq3Z+y7A5DGszX7aU/kZJ0TON5K4j8tLS+/tv2r/cP4HWlcwwJprQ5rO0i L6tvV3vaOShPructFLt2kMevGRJViLL+HvWpEZkK/JL8tY0nxayw0zWrRGIMvguKQ99O S4KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=vUxIavbcZGSnXzzqLMLtqCsSyL9AzS8IIPH9T9Nmf5w=; b=AsKJQwnoUzPGdh4To3b7qCrn4veOpn+rWvAI7RlaapZGOY8IPUuHx0Ln4yOWALqZCo 4UukqHZqImFrz9DXN4iDT2VsNtU3DV49WpiKBhDl2J8TXbvaHibK9N9c642A8wq+f18S 0QDjP4dodEc6+QtCOu6SPdrWWy4cTXU+QFTzIbSui3I+Q1chJItjHEx8tUYwgYj/1hjs qOZAmoPKEEf5IBEVHa5TootevEgRQj81GXzgAjbaNZ+mblmzng8+t1+8bMw0z1Ci/tAX u42mj9ifE9cX9ITlx8o8GutLDobAq5T/HD6vxffzqctfNOS7TCC4MpT31k/w+0317xQV qxlg== X-Gm-Message-State: AIVw113NbbOOFbmQGjIcKQI1SKSUKMydP4zbUbDhPRAqi3QoVb/s9CxG y2Hax2T50nx2l21nrwU= X-Received: by 10.99.140.76 with SMTP id q12mr1144884pgn.45.1501824520479; Thu, 03 Aug 2017 22:28:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:28:26 -0700 Message-Id: <20170804052833.10187-5-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804052833.10187-1-rth@twiddle.net> References: <20170804052833.10187-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 2/8] tcg/s390: Merge cmpi facilities check to tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 68 +++++++++++++++++++++----------------------= ---- 1 file changed, 30 insertions(+), 38 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index d34649eb13..e075b4844a 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -41,7 +41,7 @@ #define TCG_CT_CONST_MULI 0x100 #define TCG_CT_CONST_ORI 0x200 #define TCG_CT_CONST_XORI 0x400 -#define TCG_CT_CONST_CMPI 0x800 +#define TCG_CT_CONST_U31 0x800 #define TCG_CT_CONST_ADLI 0x1000 #define TCG_CT_CONST_ZERO 0x2000 =20 @@ -398,7 +398,18 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, ct->ct |=3D TCG_CT_CONST_XORI; break; case 'C': - ct->ct |=3D TCG_CT_CONST_CMPI; + /* ??? We have no insight here into whether the comparison is + signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit + signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses + a 32-bit unsigned immediate. If we were to use the (semi) + obvious "val =3D=3D (int32_t)val" we would be enabling unsigned + comparisons vs very large numbers. The only solution is to + take the intersection of the ranges. */ + /* ??? Another possible solution is to simply lie and allow all + constants here and force the out-of-range values into a temp + register in tgen_cmp when we have knowledge of the actual + comparison code in use. */ + ct->ct |=3D TCG_CT_CONST_U31; break; case 'Z': ct->ct |=3D TCG_CT_CONST_ZERO; @@ -463,35 +474,6 @@ static int tcg_match_xori(TCGType type, tcg_target_lon= g val) return 1; } =20 -/* Imediates to be used with comparisons. */ - -static int tcg_match_cmpi(TCGType type, tcg_target_long val) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - /* The COMPARE IMMEDIATE instruction is available. */ - if (type =3D=3D TCG_TYPE_I32) { - /* We have a 32-bit immediate and can compare against anything= . */ - return 1; - } else { - /* ??? We have no insight here into whether the comparison is - signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-b= it - signed immediate, and the COMPARE LOGICAL IMMEDIATE insn us= es - a 32-bit unsigned immediate. If we were to use the (semi) - obvious "val =3D=3D (int32_t)val" we would be enabling unsi= gned - comparisons vs very large numbers. The only solution is to - take the intersection of the ranges. */ - /* ??? Another possible solution is to simply lie and allow all - constants here and force the out-of-range values into a temp - register in tgen_cmp when we have knowledge of the actual - comparison code in use. */ - return val >=3D 0 && val <=3D 0x7fffffff; - } - } else { - /* Only the LOAD AND TEST instruction is available. */ - return val =3D=3D 0; - } -} - /* Immediates to be used with add2/sub2. */ =20 static int tcg_match_add2i(TCGType type, tcg_target_long val) @@ -537,8 +519,8 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, return tcg_match_ori(type, val); } else if (ct & TCG_CT_CONST_XORI) { return tcg_match_xori(type, val); - } else if (ct & TCG_CT_CONST_CMPI) { - return tcg_match_cmpi(type, val); + } else if (ct & TCG_CT_CONST_U31) { + return val >=3D 0 && val <=3D 0x7fffffff; } else if (ct & TCG_CT_CONST_ZERO) { return val =3D=3D 0; } @@ -2252,7 +2234,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef r_r =3D { .args_ct_str =3D { "r", "r" } }; static const TCGTargetOpDef r_L =3D { .args_ct_str =3D { "r", "L" } }; static const TCGTargetOpDef L_L =3D { .args_ct_str =3D { "L", "L" } }; + static const TCGTargetOpDef r_ri =3D { .args_ct_str =3D { "r", "ri" } = }; static const TCGTargetOpDef r_rC =3D { .args_ct_str =3D { "r", "rC" } = }; + static const TCGTargetOpDef r_rZ =3D { .args_ct_str =3D { "r", "rZ" } = }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; static const TCGTargetOpDef r_0_rK =3D { .args_ct_str =3D { "r", "0", = "rK" } }; @@ -2320,8 +2304,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) return &r_r_ri; =20 case INDEX_op_brcond_i32: + /* Without EXT_IMM, only the LOAD AND TEST insn is available. */ + return (s390_facilities & FACILITY_EXT_IMM ? &r_ri : &r_rZ); case INDEX_op_brcond_i64: - return &r_rC; + return (s390_facilities & FACILITY_EXT_IMM ? &r_rC : &r_rZ); =20 case INDEX_op_bswap16_i32: case INDEX_op_bswap16_i64: @@ -2366,16 +2352,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: { - static const TCGTargetOpDef setc + /* Without EXT_IMM, only the LOAD AND TEST insn is available. = */ + static const TCGTargetOpDef setc_z + =3D { .args_ct_str =3D { "r", "r", "rZ" } }; + static const TCGTargetOpDef setc_c =3D { .args_ct_str =3D { "r", "r", "rC" } }; - return &setc; + return (s390_facilities & FACILITY_EXT_IMM ? &setc_c : &setc_z= ); } case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: { - static const TCGTargetOpDef movc + /* Without EXT_IMM, only the LOAD AND TEST insn is available. = */ + static const TCGTargetOpDef movc_z + =3D { .args_ct_str =3D { "r", "r", "rZ", "r", "0" } }; + static const TCGTargetOpDef movc_c =3D { .args_ct_str =3D { "r", "r", "rC", "r", "0" } }; - return &movc; + return (s390_facilities & FACILITY_EXT_IMM ? &movc_c : &movc_z= ); } case INDEX_op_div2_i32: case INDEX_op_div2_i64: --=20 2.13.3 From nobody Sat Apr 27 19:54:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501824634421977.8344967777077; Thu, 3 Aug 2017 22:30:34 -0700 (PDT) Received: from localhost ([::1]:35735 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVBx-0000o8-15 for importer@patchew.org; Fri, 04 Aug 2017 01:30:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36308) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVAB-0007Tz-FB for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVAA-0001Ck-KM for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:43 -0400 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:38826) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVAA-0001C4-ET for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:42 -0400 Received: by mail-pg0-x243.google.com with SMTP id 123so778259pga.5 for ; Thu, 03 Aug 2017 22:28:42 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id m5sm1053099pfg.22.2017.08.03.22.28.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:28:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZTvm9dawsrAvg/0kp+KzEWsiNH8QxHZk2ZLtJWCc5UU=; b=kyTMZVbXPPxyEd7Ry79NHNc6W/SNYd2wo52v+uaKx4XJEj6uKsM+oAnrwz+S142uEP 5szQgIx/8ITBMvL5vffyaJkNhDAZQD4RQt9k78waVxNP/sOm00mw3m3NRt4qzQPGC6zU wumherBOl9sjdAlxvZ6CitCMOV5Z46vJYi59klvngnRbMe15Yl8P/holfsWvAIlWTqt4 OeR90GvqB75XkJ3Yhe9S99Te7FIE0BQzFW8otb76rYGOKNctF5sOuHvsAeUnAYLuwaiN mKW06eeTBIu5hx0UYdypfNhjPD3DrtokoUim+f8sklaUEiOfGBXmWUJ+F6cfrzl46q+i TgvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=ZTvm9dawsrAvg/0kp+KzEWsiNH8QxHZk2ZLtJWCc5UU=; b=HvEzc1hKZ8ZLNCxW+s191EeZIhHhbo8nHMCGPJkL/O5jAPRN1WMzBMmko6aO7pKNeo PHxlr7WIZsdsuiImk3idbNyweTtdaafn0zpV/XdTs0PEsAbxZ5U9JI0v3aVmxiDgGzBR VJyu4iBLdH9sd8AqeKOUCJMLXiw9vdGyHV4Lk7LPyRO2vIj82QoIIU3lzeOiFJpGSaER iqLtv3jFHU91g3BaQ6jo0eWKviwTu9qb1wUrzTVETsCeXfc0mtTi+JGpVz6WwAd/yliK 0IZkDBkuy2gnfWU9AWOGxrsfL5WWGSM4Xvfo/kojhsEYQEL/USmTkE+VVH9wGMbfP0Eq LN5w== X-Gm-Message-State: AIVw112OUGxJ5dDU+60VdAEAJxSkWlKtCK9xBL6/DRfZ6hmf7taE9iC+ Xd7jC3LXdBncky5GVr4= X-Received: by 10.99.2.148 with SMTP id 142mr1149568pgc.164.1501824521365; Thu, 03 Aug 2017 22:28:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:28:27 -0700 Message-Id: <20170804052833.10187-6-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804052833.10187-1-rth@twiddle.net> References: <20170804052833.10187-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL for-2.10 3/3] tcg: Increase minimum alignment from tcg_malloc to 8 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For a 64-bit ILP32 host, aligning to sizeof(long) is not enough. Guess the minimum for any host is 8, as that covers uint64_t. Qemu doesn't use a host long double or host vectors, except in extremely limited circumstances. Fixes a bus error for a sparc v8plus host. Signed-off-by: Richard Henderson --- tcg/tcg.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index da78721a0d..17b7750ee6 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -762,7 +762,10 @@ static inline void *tcg_malloc(int size) { TCGContext *s =3D &tcg_ctx; uint8_t *ptr, *ptr_end; - size =3D (size + sizeof(long) - 1) & ~(sizeof(long) - 1); + + /* ??? This is a weak placeholder for minimum malloc alignment. */ + size =3D QEMU_ALIGN_UP(size, 8); + ptr =3D s->pool_cur; ptr_end =3D ptr + size; if (unlikely(ptr_end > s->pool_end)) { --=20 2.13.3 From nobody Sat Apr 27 19:54:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501824802329244.00419194778442; Thu, 3 Aug 2017 22:33:22 -0700 (PDT) Received: from localhost ([::1]:35745 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVEe-0003Al-RA for importer@patchew.org; Fri, 04 Aug 2017 01:33:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36376) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVAC-0007V4-UY for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVAB-0001EK-Im for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:44 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:34324) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVAB-0001D0-ED for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:43 -0400 Received: by mail-pf0-x242.google.com with SMTP id t86so835836pfe.1 for ; Thu, 03 Aug 2017 22:28:43 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id m5sm1053099pfg.22.2017.08.03.22.28.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:28:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZzsK3pv2nCbKukJF7e3nVGFgyIuWEr2QzecpxPKW2kA=; b=qv677EycMOkP/Wi+ZBg0FnD5lKHxhZtte3O0TIEK7P1xrRI9xgYYQmHXsq4Sh5kq9L g84lCJRBT1bjU2Af11uDnsz/zoSzmJm0OMG4IhU4sPy1NW6lvk7/64YEuNwhTk4Zr322 /5Y1imO8FkeAb//IHfTSOHQlwLedoZQuO5c3QFLGplUs1zQZ+XYEg/Bu5TTrhSk2hDZa SLceEjJ84Fs1gCFIj89O8nghr8Lm3E85OYACuOYTEVnJ375KT7xFl7Vq9asLIjKKPxWz DJRO3EOvR+QnLxXiCJ1nSVA0W7w2R9ExRtt5q+salVIpjymtn5yxwOhBu2eqI25MQvtl Xk0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=ZzsK3pv2nCbKukJF7e3nVGFgyIuWEr2QzecpxPKW2kA=; b=uJ8v7klES6YaPN/oPQ/2/hL7+8A2IdifQATGJGmQAbn8E6uC8MobJd5Pmc4VYq4Mfx ucPgybBRkYDF/KgN9ZVLLJgFqSQsM84U6hLPpJAu/mb7axEKGW9xJo8KmUbinAFA2LqT XJPvUjGFjyucWLgi8uaiz5gTCMTTykonKQnXlEdT4isLZo7dDzMkhLxBrY7V4Mb9M8yj ABI/pxHMC+1AU7QPI3S99rTYdipuL70AYI1zhS8+tDRYK/eshABMGJCxNLvNUR+hCObk RPRAMRN1axyPVG5T9gDxsNsOSCowgiodCCuxRSgE8MzhyTumFKeT1vE2Gj9Q+CgH5RHW SdjQ== X-Gm-Message-State: AIVw111VMH+UW5XUH6C9zIangn4JR5vnq0A2+QJHR4FGdgks9s+wsVoT WpalY79nbrHDuupGrWI= X-Received: by 10.99.112.16 with SMTP id l16mr1091337pgc.143.1501824522253; Thu, 03 Aug 2017 22:28:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:28:28 -0700 Message-Id: <20170804052833.10187-7-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804052833.10187-1-rth@twiddle.net> References: <20170804052833.10187-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH 3/8] tcg/s390: Merge muli facilities check to tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 45 +++++++++++++++++++++++++------------------= -- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index e075b4844a..ff3f644f8e 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -38,12 +38,13 @@ a 32-bit displacement here Just In Case. */ #define USE_LONG_BRANCHES 0 =20 -#define TCG_CT_CONST_MULI 0x100 -#define TCG_CT_CONST_ORI 0x200 -#define TCG_CT_CONST_XORI 0x400 -#define TCG_CT_CONST_U31 0x800 -#define TCG_CT_CONST_ADLI 0x1000 -#define TCG_CT_CONST_ZERO 0x2000 +#define TCG_CT_CONST_S16 0x100 +#define TCG_CT_CONST_S32 0x200 +#define TCG_CT_CONST_ORI 0x400 +#define TCG_CT_CONST_XORI 0x800 +#define TCG_CT_CONST_U31 0x1000 +#define TCG_CT_CONST_ADLI 0x2000 +#define TCG_CT_CONST_ZERO 0x4000 =20 /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ @@ -388,8 +389,11 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, case 'A': ct->ct |=3D TCG_CT_CONST_ADLI; break; - case 'K': - ct->ct |=3D TCG_CT_CONST_MULI; + case 'I': + ct->ct |=3D TCG_CT_CONST_S16; + break; + case 'J': + ct->ct |=3D TCG_CT_CONST_S32; break; case 'O': ct->ct |=3D TCG_CT_CONST_ORI; @@ -503,16 +507,10 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, } =20 /* The following are mutually exclusive. */ - if (ct & TCG_CT_CONST_MULI) { - /* Immediates that may be used with multiply. If we have the - general-instruction-extensions, then we have MULTIPLY SINGLE - IMMEDIATE with a signed 32-bit, otherwise we have only - MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - if (s390_facilities & FACILITY_GEN_INST_EXT) { - return val =3D=3D (int32_t)val; - } else { - return val =3D=3D (int16_t)val; - } + if (ct & TCG_CT_CONST_S16) { + return val =3D=3D (int16_t)val; + } else if (ct & TCG_CT_CONST_S32) { + return val =3D=3D (int32_t)val; } else if (ct & TCG_CT_CONST_ADLI) { return tcg_match_add2i(type, val); } else if (ct & TCG_CT_CONST_ORI) { @@ -2239,7 +2237,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef r_rZ =3D { .args_ct_str =3D { "r", "rZ" } = }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; - static const TCGTargetOpDef r_0_rK =3D { .args_ct_str =3D { "r", "0", = "rK" } }; + static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; + static const TCGTargetOpDef r_0_rJ =3D { .args_ct_str =3D { "r", "0", = "rJ" } }; static const TCGTargetOpDef r_0_rO =3D { .args_ct_str =3D { "r", "0", = "rO" } }; static const TCGTargetOpDef r_0_rX =3D { .args_ct_str =3D { "r", "0", = "rX" } }; =20 @@ -2274,9 +2273,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) case INDEX_op_sub_i32: case INDEX_op_sub_i64: return &r_0_ri; + case INDEX_op_mul_i32: + /* If we have the general-instruction-extensions, then we have + MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we + have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ + return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_r= I); case INDEX_op_mul_i64: - return &r_0_rK; + return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_r= I); + case INDEX_op_or_i32: case INDEX_op_or_i64: return &r_0_rO; --=20 2.13.3 From nobody Sat Apr 27 19:54:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501825111229750.2311768157849; Thu, 3 Aug 2017 22:38:31 -0700 (PDT) Received: from localhost ([::1]:35979 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVJa-00081Z-OY for importer@patchew.org; Fri, 04 Aug 2017 01:38:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36391) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVAD-0007YP-Nq for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVAC-0001GB-Of for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:45 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:37681) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVAC-0001Eu-GX for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:44 -0400 Received: by mail-pg0-x244.google.com with SMTP id 83so789166pgb.4 for ; Thu, 03 Aug 2017 22:28:44 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id m5sm1053099pfg.22.2017.08.03.22.28.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:28:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=JNnZ+xpRDYAJ19JYipi9Tbdso194ocixTivlCgCkM8I=; b=l53DMUpC3yGxr8S4nHEMvYecpMNT9LBFMfiWwz4UGyAMsX2zRdqW3eX+HiZjFJNgAP yBenjdNngwppwmqVKi+AYD+394spod99/e2BMkH6fcbkSzJj5G/3NU1RoCv22dipEL4v 5HZSscnOWQHuSJM7wVHemJwptUZB28Sk9kdyN0DgDKNQRH8jFTGPouvlz6AsSUTZ2ZSN Tm4MXW08BjXsNTOX2kZMHthdKI4RLPHPH+xrIMFx10moHSReKXSWG+ttuGD/9sWvMqF1 bP8arey9dHh0CcHcystW8KC3ODqnOFGasRfTHlFjgB3MLwBYvfVC8QUJ5L/Hm42X+eTz jV/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=JNnZ+xpRDYAJ19JYipi9Tbdso194ocixTivlCgCkM8I=; b=jicw9SYH37P7Mdv4L+4xW7OqCovE0sBuwmUOK9Tfiao/sth84PddMwJBGQTbJtMp1i eRNL2KRO/HvEokV/mH0+X1yFv2oWshcdQ3xUVDArEbMPe4HzZy2eEgfdMFgW2euU4Ksf PInhBilqz9b+VWIXcDFdkTByB0ZbhiRrs6kzrTsG5LXooeK9N2+K2aVU3yoYMKbY6YAr PR8rCk9OlY9o4xJx2nRRnFOw+2ONAHRS74MqwUU5sD4TT2np5GpZoGsu363O2MNKLefa BoaSSTtq7p+9xAEdNiyxxu5hPikM7Dps/N2QtG8H1UicL52Ae8lWggLXciuvDeRDFLTE 7uMA== X-Gm-Message-State: AIVw111vMFAZy80i+/y4H4ztt7oGSzKAo3XcBKYKSa2kr7xPGdUlcWtZ EWGmH4L/nCc84LEgBQs= X-Received: by 10.99.55.79 with SMTP id g15mr1157177pgn.28.1501824523356; Thu, 03 Aug 2017 22:28:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:28:29 -0700 Message-Id: <20170804052833.10187-8-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804052833.10187-1-rth@twiddle.net> References: <20170804052833.10187-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 4/8] tcg/s390: Merge add2i facilities check to tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 38 ++++++++++++++------------------------ 1 file changed, 14 insertions(+), 24 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index ff3f644f8e..6b08ccea6d 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -43,7 +43,7 @@ #define TCG_CT_CONST_ORI 0x400 #define TCG_CT_CONST_XORI 0x800 #define TCG_CT_CONST_U31 0x1000 -#define TCG_CT_CONST_ADLI 0x2000 +#define TCG_CT_CONST_S33 0x2000 #define TCG_CT_CONST_ZERO 0x4000 =20 /* Several places within the instruction set 0 means "no register" @@ -387,7 +387,7 @@ static const char *target_parse_constraint(TCGArgConstr= aint *ct, tcg_regset_set_reg(ct->u.regs, TCG_REG_R3); break; case 'A': - ct->ct |=3D TCG_CT_CONST_ADLI; + ct->ct |=3D TCG_CT_CONST_S33; break; case 'I': ct->ct |=3D TCG_CT_CONST_S16; @@ -478,20 +478,6 @@ static int tcg_match_xori(TCGType type, tcg_target_lon= g val) return 1; } =20 -/* Immediates to be used with add2/sub2. */ - -static int tcg_match_add2i(TCGType type, tcg_target_long val) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - if (type =3D=3D TCG_TYPE_I32) { - return 1; - } else if (val >=3D -0xffffffffll && val <=3D 0xffffffffll) { - return 1; - } - } - return 0; -} - /* Test if a constant matches the constraint. */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) @@ -511,8 +497,8 @@ static int tcg_target_const_match(tcg_target_long val, = TCGType type, return val =3D=3D (int16_t)val; } else if (ct & TCG_CT_CONST_S32) { return val =3D=3D (int32_t)val; - } else if (ct & TCG_CT_CONST_ADLI) { - return tcg_match_add2i(type, val); + } else if (ct & TCG_CT_CONST_S33) { + return val >=3D -0xffffffffll && val <=3D 0xffffffffll; } else if (ct & TCG_CT_CONST_ORI) { return tcg_match_ori(type, val); } else if (ct & TCG_CT_CONST_XORI) { @@ -2241,6 +2227,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) static const TCGTargetOpDef r_0_rJ =3D { .args_ct_str =3D { "r", "0", = "rJ" } }; static const TCGTargetOpDef r_0_rO =3D { .args_ct_str =3D { "r", "0", = "rO" } }; static const TCGTargetOpDef r_0_rX =3D { .args_ct_str =3D { "r", "0", = "rX" } }; + static const TCGTargetOpDef a2_r + =3D { .args_ct_str =3D { "r", "r", "0", "1", "r", "r" } }; + static const TCGTargetOpDef a2_ri + =3D { .args_ct_str =3D { "r", "r", "0", "1", "ri", "r" } }; + static const TCGTargetOpDef a2_rA + =3D { .args_ct_str =3D { "r", "r", "0", "1", "rA", "r" } }; =20 switch (op) { case INDEX_op_goto_ptr: @@ -2389,15 +2381,13 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) =3D { .args_ct_str =3D { "b", "a", "0", "r" } }; return &mul2; } + case INDEX_op_add2_i32: - case INDEX_op_add2_i64: case INDEX_op_sub2_i32: + return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r); + case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - { - static const TCGTargetOpDef arith2 - =3D { .args_ct_str =3D { "r", "r", "0", "1", "rA", "r" } }; - return &arith2; - } + return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r); =20 default: break; --=20 2.13.3 From nobody Sat Apr 27 19:54:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501824639690991.1803446533454; Thu, 3 Aug 2017 22:30:39 -0700 (PDT) Received: from localhost ([::1]:35738 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVC2-0000z9-9W for importer@patchew.org; Fri, 04 Aug 2017 01:30:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36426) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVAE-0007bH-Td for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVAD-0001Gz-L9 for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:46 -0400 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:34327) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVAD-0001GO-E2 for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:45 -0400 Received: by mail-pf0-x242.google.com with SMTP id t86so835884pfe.1 for ; Thu, 03 Aug 2017 22:28:45 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id m5sm1053099pfg.22.2017.08.03.22.28.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:28:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=u1SrIbErFj1GWeBgChkAVAjy4jOBnc6gZM1ocPLydPQ=; b=eohi9PadoTQb7sjSRYkqRI7LJ5gh5UWVYQSj2sox1eRXAGaXpnebZEVnTRno8XV7wX 1DyjcOW+LUDdICJRZu9s5VX3Lpaq+XP/vVb/4FqsAZFgnWAAcb1xh5MTedtAIIH++uAV 5r5JrK3zqdhxmUA/kQeuB7zVBle9xY/+JGueexMemZ0zsalZNs0W5QtLQMjKnwJ6+wRJ 3CR9IPq2xUCJDfemHcmrrm/67xbHUNz1e9loAlL25o/VWi9c29jMKefF2ldj7rhz0VmD 1AndLu1bGHrvzpAI4jnrsOlSs3iu7U0XD5RnBBUYWaDaQ2bA3FzehzSOUqWG41N/uEpF KLHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=u1SrIbErFj1GWeBgChkAVAjy4jOBnc6gZM1ocPLydPQ=; b=Z56HoHg3fui8ygzcS5QetI7W11frhjbXfAmiWjCSZhGXTuepbopMLSDnWn0Wtr3Eh1 JUReH56oBmb8YfNjkS8Lmx5DHg/ij7EkHzzR1aSKsphVDePbHmkL2boHYrSCLrMNga4x Xp2vo278QQwFrLOeN4KnGUHOEG0/BpU6hNJKnTN8gJM9UqtnT/Js+HOD4+t+UxrJMz/O 2OQeM3eRa9jh+xtYwUrl63TjEHfcUDYJqSUtwDLGKdb44QOvopbsOglJW3/F6zpuoz1f r2g/aoV5V2kw2zKhGc7fX9ga0jsW/xMv5nZnQi41YyrDpobIAdyJxVsYjQyaGoj6eqev N6+Q== X-Gm-Message-State: AIVw112UsAvQ1oS12K+EcY0uoUdcvxlVGYoOikVnXkIsh+2LbB+h5bci oov+t41RL+k2HyEqQUQ= X-Received: by 10.98.59.193 with SMTP id w62mr1138221pfj.335.1501824524320; Thu, 03 Aug 2017 22:28:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:28:30 -0700 Message-Id: <20170804052833.10187-9-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804052833.10187-1-rth@twiddle.net> References: <20170804052833.10187-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH 5/8] tcg/s390: Merge ori+xori facilities check to tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 101 +++++++++++++++---------------------------= ---- 1 file changed, 33 insertions(+), 68 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 6b08ccea6d..5414c9d879 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -40,8 +40,8 @@ =20 #define TCG_CT_CONST_S16 0x100 #define TCG_CT_CONST_S32 0x200 -#define TCG_CT_CONST_ORI 0x400 -#define TCG_CT_CONST_XORI 0x800 +#define TCG_CT_CONST_NN16 0x400 +#define TCG_CT_CONST_NN32 0x800 #define TCG_CT_CONST_U31 0x1000 #define TCG_CT_CONST_S33 0x2000 #define TCG_CT_CONST_ZERO 0x4000 @@ -395,11 +395,11 @@ static const char *target_parse_constraint(TCGArgCons= traint *ct, case 'J': ct->ct |=3D TCG_CT_CONST_S32; break; - case 'O': - ct->ct |=3D TCG_CT_CONST_ORI; + case 'N': + ct->ct |=3D TCG_CT_CONST_NN16; break; - case 'X': - ct->ct |=3D TCG_CT_CONST_XORI; + case 'M': + ct->ct |=3D TCG_CT_CONST_NN32; break; case 'C': /* ??? We have no insight here into whether the comparison is @@ -424,60 +424,6 @@ static const char *target_parse_constraint(TCGArgConst= raint *ct, return ct_str; } =20 -/* Immediates to be used with logical OR. This is an optimization only, - since a full 64-bit immediate OR can always be performed with 4 sequent= ial - OI[LH][LH] instructions. What we're looking for is immediates that we - can load efficiently, and the immediate load plus the reg-reg OR is - smaller than the sequential OI's. */ - -static int tcg_match_ori(TCGType type, tcg_target_long val) -{ - if (s390_facilities & FACILITY_EXT_IMM) { - if (type =3D=3D TCG_TYPE_I32) { - /* All 32-bit ORs can be performed with 1 48-bit insn. */ - return 1; - } - } - - /* Look for negative values. These are best to load with LGHI. */ - if (val < 0) { - if (val =3D=3D (int16_t)val) { - return 0; - } - if (s390_facilities & FACILITY_EXT_IMM) { - if (val =3D=3D (int32_t)val) { - return 0; - } - } - } - - return 1; -} - -/* Immediates to be used with logical XOR. This is almost, but not quite, - only an optimization. XOR with immediate is only supported with the - extended-immediate facility. That said, there are a few patterns for - which it is better to load the value into a register first. */ - -static int tcg_match_xori(TCGType type, tcg_target_long val) -{ - if ((s390_facilities & FACILITY_EXT_IMM) =3D=3D 0) { - return 0; - } - - if (type =3D=3D TCG_TYPE_I32) { - /* All 32-bit XORs can be performed with 1 48-bit insn. */ - return 1; - } - - /* Look for negative values. These are best to load with LGHI. */ - if (val < 0 && val =3D=3D (int32_t)val) { - return 0; - } - - return 1; -} - /* Test if a constant matches the constraint. */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct) @@ -499,10 +445,10 @@ static int tcg_target_const_match(tcg_target_long val= , TCGType type, return val =3D=3D (int32_t)val; } else if (ct & TCG_CT_CONST_S33) { return val >=3D -0xffffffffll && val <=3D 0xffffffffll; - } else if (ct & TCG_CT_CONST_ORI) { - return tcg_match_ori(type, val); - } else if (ct & TCG_CT_CONST_XORI) { - return tcg_match_xori(type, val); + } else if (ct & TCG_CT_CONST_NN16) { + return !(val < 0 && val =3D=3D (int16_t)val); + } else if (ct & TCG_CT_CONST_NN32) { + return !(val < 0 && val =3D=3D (int32_t)val); } else if (ct & TCG_CT_CONST_U31) { return val >=3D 0 && val <=3D 0x7fffffff; } else if (ct & TCG_CT_CONST_ZERO) { @@ -2222,11 +2168,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) static const TCGTargetOpDef r_rC =3D { .args_ct_str =3D { "r", "rC" } = }; static const TCGTargetOpDef r_rZ =3D { .args_ct_str =3D { "r", "rZ" } = }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; + static const TCGTargetOpDef r_0_r =3D { .args_ct_str =3D { "r", "0", "= r" } }; static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; static const TCGTargetOpDef r_0_rJ =3D { .args_ct_str =3D { "r", "0", = "rJ" } }; - static const TCGTargetOpDef r_0_rO =3D { .args_ct_str =3D { "r", "0", = "rO" } }; - static const TCGTargetOpDef r_0_rX =3D { .args_ct_str =3D { "r", "0", = "rX" } }; + static const TCGTargetOpDef r_0_rN =3D { .args_ct_str =3D { "r", "0", = "rN" } }; + static const TCGTargetOpDef r_0_rM =3D { .args_ct_str =3D { "r", "0", = "rM" } }; static const TCGTargetOpDef a2_r =3D { .args_ct_str =3D { "r", "r", "0", "1", "r", "r" } }; static const TCGTargetOpDef a2_ri @@ -2275,11 +2222,29 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_r= I); =20 case INDEX_op_or_i32: + /* The use of [iNM] constraints are optimization only, since a full + 64-bit immediate OR can always be performed with 4 sequential + OI[LH][LH] instructions. By rejecting certain negative ranges, + the immediate load plus the reg-reg OR is smaller. */ + return (s390_facilities & FACILITY_EXT_IMM + ? &r_0_ri + : &r_0_rN); case INDEX_op_or_i64: - return &r_0_rO; + return (s390_facilities & FACILITY_EXT_IMM + ? &r_0_rM + : &r_0_rN); + case INDEX_op_xor_i32: + /* Without EXT_IMM, no immediates are supported. Otherwise, + rejecting certain negative ranges leads to smaller code. */ + return (s390_facilities & FACILITY_EXT_IMM + ? &r_0_ri + : &r_0_r); case INDEX_op_xor_i64: - return &r_0_rX; + return (s390_facilities & FACILITY_EXT_IMM + ? &r_0_rM + : &r_0_r); + case INDEX_op_and_i32: case INDEX_op_and_i64: return &r_0_ri; --=20 2.13.3 From nobody Sat Apr 27 19:54:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501824810090692.4487971209195; Thu, 3 Aug 2017 22:33:30 -0700 (PDT) Received: from localhost ([::1]:35746 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVEm-0003HX-Mo for importer@patchew.org; Fri, 04 Aug 2017 01:33:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36470) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVAG-0007f7-CG for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVAE-0001I8-QF for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:48 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:33910) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVAE-0001HQ-Hk for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:46 -0400 Received: by mail-pg0-x242.google.com with SMTP id y192so803236pgd.1 for ; Thu, 03 Aug 2017 22:28:46 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id m5sm1053099pfg.22.2017.08.03.22.28.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:28:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZzOQcxP9s6jKeIJ4rIh+gzYTzAmYoTWmnfWvZFU4YGg=; b=nbHZYYabQDFOczttL+XSwV9N7MQVNM8MCyOyWPHNt6R1SopMGYf4d5gJwK0DeKX10u WGheFzsoQYdpJAUOib3snu9IfyS67ocx3TooOifptRW4fgvbwh2Nvsm/5M9y3xq8NBLV pVsl8wSeshUXZbEV/lJ+rAOjkQvT9QhjfhbDpGE3xpv1okG05J82P/n3halmT+sysh44 03eHhZPQHZfCcfXufa61Tt44SiQB1JvBgincjZ98hYJJMpPg/fbfhxQpmvWNtrJBccb3 zKFywt4Fb5nW+rvbr0V3wpz22mvb4iD9n+ZzDctNSmwTBmjWKTCCwU0zkxkT1Z7R0yzJ BsTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=ZzOQcxP9s6jKeIJ4rIh+gzYTzAmYoTWmnfWvZFU4YGg=; b=B1wzQ7aL/waDDnYVhAQAyfiZGF+Um7rjHYgEIYKrrFYhoNqlW3QdbsBBVQoZZidg6F YBuPMxWAj0leSE6BTJQEHxlpjN5oqhnvjWcE6fXHYIF3d4G9u2FvaQXoqr1vyMUQTYqa Frm9p77q13zGL0OcuwZ9BC+5qzVTZ+QBvTbRUMEd+B+PVh0XvzJrB+JrtP7/ekywquiI 0Ly8QSnMbjobl/7UAOTwi9c2dlGPoScOz/pw0e2Mf+KCnH3y/SOblZ9UGJ7P3Ko+Jq+F Y+y7QRnzBQAgnU33xQb3KS6QnxgjzL4RuD6KYDDjKj8J3m6Bv6XTrVugynWjFsprqHF7 cvYQ== X-Gm-Message-State: AIVw113VCVLqIbNF0BRrop8Fe5JztevkRhpGSwt8jvZLNB4T6kU/VxgP w0B2IBefbE4s2243OVg= X-Received: by 10.98.206.194 with SMTP id y185mr1209420pfg.312.1501824525358; Thu, 03 Aug 2017 22:28:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:28:31 -0700 Message-Id: <20170804052833.10187-10-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804052833.10187-1-rth@twiddle.net> References: <20170804052833.10187-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH 6/8] tcg/s390: Use distinct-operands facility X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows using a 3-operand insn form for some arithmetic, logicals and shifts. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.inc.c | 118 +++++++++++++++++++++++++++++++++++-------= ---- 2 files changed, 91 insertions(+), 28 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 957f0c0afe..1b5eb22c26 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -58,6 +58,7 @@ typedef enum TCGReg { #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34)) #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND +#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND =20 extern uint64_t s390_facilities; =20 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 5414c9d879..a80b07db65 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -159,6 +159,16 @@ typedef enum S390Opcode { =20 RRF_LOCR =3D 0xb9f2, RRF_LOCGR =3D 0xb9e2, + RRF_NRK =3D 0xb9f4, + RRF_NGRK =3D 0xb9e4, + RRF_ORK =3D 0xb9f6, + RRF_OGRK =3D 0xb9e6, + RRF_SRK =3D 0xb9f9, + RRF_SGRK =3D 0xb9e9, + RRF_SLRK =3D 0xb9fb, + RRF_SLGRK =3D 0xb9eb, + RRF_XRK =3D 0xb9f7, + RRF_XGRK =3D 0xb9e7, =20 RR_AR =3D 0x1a, RR_ALR =3D 0x1e, @@ -179,8 +189,11 @@ typedef enum S390Opcode { RSY_RLL =3D 0xeb1d, RSY_RLLG =3D 0xeb1c, RSY_SLLG =3D 0xeb0d, + RSY_SLLK =3D 0xebdf, RSY_SRAG =3D 0xeb0a, + RSY_SRAK =3D 0xebdc, RSY_SRLG =3D 0xeb0c, + RSY_SRLK =3D 0xebde, =20 RS_SLL =3D 0x89, RS_SRA =3D 0x8a, @@ -1065,23 +1078,29 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, case TCG_COND_GEU: do_geu: /* We need "real" carry semantics, so use SUBTRACT LOGICAL - instead of COMPARE LOGICAL. This needs an extra move. */ - tcg_out_mov(s, type, TCG_TMP0, c1); + instead of COMPARE LOGICAL. This may need an extra move. */ if (c2const) { - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_mov(s, type, TCG_TMP0, c1); if (type =3D=3D TCG_TYPE_I32) { tcg_out_insn(s, RIL, SLFI, TCG_TMP0, c2); } else { tcg_out_insn(s, RIL, SLGFI, TCG_TMP0, c2); } + } else if (s390_facilities & FACILITY_DISTINCT_OPS) { + if (type =3D=3D TCG_TYPE_I32) { + tcg_out_insn(s, RRF, SLRK, TCG_TMP0, c1, c2); + } else { + tcg_out_insn(s, RRF, SLGRK, TCG_TMP0, c1, c2); + } } else { + tcg_out_mov(s, type, TCG_TMP0, c1); if (type =3D=3D TCG_TYPE_I32) { tcg_out_insn(s, RR, SLR, TCG_TMP0, c2); } else { tcg_out_insn(s, RRE, SLGR, TCG_TMP0, c2); } - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); } + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); tcg_out_insn(s, RRE, ALCGR, dest, dest); return; =20 @@ -1648,7 +1667,7 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - S390Opcode op; + S390Opcode op, op2; TCGArg a0, a1, a2; =20 switch (opc) { @@ -1753,29 +1772,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, if (const_args[2]) { a2 =3D -a2; goto do_addi_32; + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RR, SR, a0, a2); + } else { + tcg_out_insn(s, RRF, SRK, a0, a1, a2); } - tcg_out_insn(s, RR, SR, args[0], args[2]); break; =20 case INDEX_op_and_i32: + a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; if (const_args[2]) { - tgen_andi(s, TCG_TYPE_I32, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen_andi(s, TCG_TYPE_I32, a0, a2); + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RR, NR, a0, a2); } else { - tcg_out_insn(s, RR, NR, args[0], args[2]); + tcg_out_insn(s, RRF, NRK, a0, a1, a2); } break; case INDEX_op_or_i32: + a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; if (const_args[2]) { - tgen64_ori(s, args[0], args[2] & 0xffffffff); + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen64_ori(s, a0, a2); + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RR, OR, a0, a2); } else { - tcg_out_insn(s, RR, OR, args[0], args[2]); + tcg_out_insn(s, RRF, ORK, a0, a1, a2); } break; case INDEX_op_xor_i32: + a0 =3D args[0], a1 =3D args[1], a2 =3D (uint32_t)args[2]; if (const_args[2]) { - tgen64_xori(s, args[0], args[2] & 0xffffffff); - } else { + tcg_out_mov(s, TCG_TYPE_I32, a0, a1); + tgen64_xori(s, a0, a2); + } else if (a0 =3D=3D a1) { tcg_out_insn(s, RR, XR, args[0], args[2]); + } else { + tcg_out_insn(s, RRF, XRK, a0, a1, a2); } break; =20 @@ -1804,18 +1838,31 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, =20 case INDEX_op_shl_i32: op =3D RS_SLL; + op2 =3D RSY_SLLK; do_shift32: - if (const_args[2]) { - tcg_out_sh32(s, op, args[0], TCG_REG_NONE, args[2]); + a0 =3D args[0], a1 =3D args[1], a2 =3D (int32_t)args[2]; + if (a0 =3D=3D a1) { + if (const_args[2]) { + tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2); + } else { + tcg_out_sh32(s, op, a0, a2, 0); + } } else { - tcg_out_sh32(s, op, args[0], args[2], 0); + /* Using tcg_out_sh64 here for the format; it is a 32-bit shif= t. */ + if (const_args[2]) { + tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2); + } else { + tcg_out_sh64(s, op2, a0, a1, a2, 0); + } } break; case INDEX_op_shr_i32: op =3D RS_SRL; + op2 =3D RSY_SRLK; goto do_shift32; case INDEX_op_sar_i32: op =3D RS_SRA; + op2 =3D RSY_SRAK; goto do_shift32; =20 case INDEX_op_rotl_i32: @@ -1957,30 +2004,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, if (const_args[2]) { a2 =3D -a2; goto do_addi_64; + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RRE, SGR, a0, a2); } else { - tcg_out_insn(s, RRE, SGR, args[0], args[2]); + tcg_out_insn(s, RRF, SGRK, a0, a1, a2); } break; =20 case INDEX_op_and_i64: + a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); tgen_andi(s, TCG_TYPE_I64, args[0], args[2]); - } else { + } else if (a0 =3D=3D a1) { tcg_out_insn(s, RRE, NGR, args[0], args[2]); + } else { + tcg_out_insn(s, RRF, NGRK, a0, a1, a2); } break; case INDEX_op_or_i64: + a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { - tgen64_ori(s, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen64_ori(s, a0, a2); + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RRE, OGR, a0, a2); } else { - tcg_out_insn(s, RRE, OGR, args[0], args[2]); + tcg_out_insn(s, RRF, OGRK, a0, a1, a2); } break; case INDEX_op_xor_i64: + a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; if (const_args[2]) { - tgen64_xori(s, args[0], args[2]); + tcg_out_mov(s, TCG_TYPE_I64, a0, a1); + tgen64_xori(s, a0, a2); + } else if (a0 =3D=3D a1) { + tcg_out_insn(s, RRE, XGR, a0, a2); } else { - tcg_out_insn(s, RRE, XGR, args[0], args[2]); + tcg_out_insn(s, RRF, XGRK, a0, a1, a2); } break; =20 @@ -2168,6 +2229,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) static const TCGTargetOpDef r_rC =3D { .args_ct_str =3D { "r", "rC" } = }; static const TCGTargetOpDef r_rZ =3D { .args_ct_str =3D { "r", "rZ" } = }; static const TCGTargetOpDef r_r_ri =3D { .args_ct_str =3D { "r", "r", = "ri" } }; + static const TCGTargetOpDef r_r_rM =3D { .args_ct_str =3D { "r", "r", = "rM" } }; static const TCGTargetOpDef r_0_r =3D { .args_ct_str =3D { "r", "0", "= r" } }; static const TCGTargetOpDef r_0_ri =3D { .args_ct_str =3D { "r", "0", = "ri" } }; static const TCGTargetOpDef r_0_rI =3D { .args_ct_str =3D { "r", "0", = "rI" } }; @@ -2211,7 +2273,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpc= ode op) return &r_r_ri; case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return &r_0_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); =20 case INDEX_op_mul_i32: /* If we have the general-instruction-extensions, then we have @@ -2227,32 +2289,32 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGO= pcode op) OI[LH][LH] instructions. By rejecting certain negative ranges, the immediate load plus the reg-reg OR is smaller. */ return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_ri + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_= 0_ri) : &r_0_rN); case INDEX_op_or_i64: return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_rM + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_= 0_rM) : &r_0_rN); =20 case INDEX_op_xor_i32: /* Without EXT_IMM, no immediates are supported. Otherwise, rejecting certain negative ranges leads to smaller code. */ return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_ri + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_= 0_ri) : &r_0_r); case INDEX_op_xor_i64: return (s390_facilities & FACILITY_EXT_IMM - ? &r_0_rM + ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_= 0_rM) : &r_0_r); =20 case INDEX_op_and_i32: case INDEX_op_and_i64: - return &r_0_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); =20 case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return &r_0_ri; + return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_r= i); =20 case INDEX_op_shl_i64: case INDEX_op_shr_i64: --=20 2.13.3 From nobody Sat Apr 27 19:54:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501825111766805.1378963403331; Thu, 3 Aug 2017 22:38:31 -0700 (PDT) Received: from localhost ([::1]:35980 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVJc-00083F-BR for importer@patchew.org; Fri, 04 Aug 2017 01:38:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36543) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVAJ-0007oo-9x for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVAF-0001JY-Ss for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:51 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:38226) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVAF-0001Ia-KR for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:47 -0400 Received: by mail-pf0-x243.google.com with SMTP id h75so825863pfh.5 for ; Thu, 03 Aug 2017 22:28:47 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id m5sm1053099pfg.22.2017.08.03.22.28.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:28:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=HhsxOCaoAPK6bTW/4HnNpTXQysKEGmb2HUcbj1xW3Sw=; b=CrKuiCmLeT4z+YnRnIZCTsfK/cpQyjJR17yAwqQ7lXaV6KKl+iaiTr70pMe5d/FqqS H6mDJeu50D8OmSTQNx13mO7XPzLeZ67wSkxx4rMC+iRVHFOoDMchEXy+DM7yRwfuYy5G PSWdrGSCWvOLzSwXzd99N+4U4Pu6YNeR8tgi7beqtfr7jQM+2HmDE+10H0W3x3J3IJCZ /jqAYAzUMscqTcmUrKhuLvLYrZSc0nIt/hxMWAObP8iFmVCerL+x/jRbxZLcWLU1UwR+ UrQ0aRmmDvH3d2HpKXEL6aELgyKcaxcvlZFMAB80+l/TJGu8tY4xaJ2Sbky2UK9LQJeo gTLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=HhsxOCaoAPK6bTW/4HnNpTXQysKEGmb2HUcbj1xW3Sw=; b=YHIGyexQgO2IjsLthzJoJzKJQSXV2t4uPMPP8SZMLnPS3NmXdhlNNi3x8CmMR9MqhS 9VOL3ttHw6SsMGS7Kuv95n5kFF/RCxJrrCiaVNxIZh7g22cvN2Tx9yWeXI+ui7Dt+ejv IaLvIo3hFUZHGdeZ9JcYYR186G9yS9FoxqbKRQAac5p3uBiakBeoOa5a5q8iZOZXM7sA QeCywhRJbj/v3AB+/PgNdzXSc8pEJYs8mjtTLsPsgw0eCKakGzGFJpbTjMyKKCa5BUOI sAQsoAfX3VaOeJX8j5hVlYX862bX+ILAi3JFLHZL2q/xEK9+elbhiZGTEcgRJi83z9tK Dr7A== X-Gm-Message-State: AIVw110dPommpm6rPkhOYGhFsBiWr6h+6bMbZ0UpomJewjVYRw4ApLBO fw4DdWcuTaw3xtnlpQU= X-Received: by 10.98.73.198 with SMTP id r67mr1207300pfi.83.1501824526549; Thu, 03 Aug 2017 22:28:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:28:32 -0700 Message-Id: <20170804052833.10187-11-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804052833.10187-1-rth@twiddle.net> References: <20170804052833.10187-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 7/8] tcg/s390: Use load-on-condition-2 facility X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows LOAD HALFWORD IMMEDIATE ON CONDITION, eliminating one insn in some common cases. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 1 + tcg/s390/tcg-target.inc.c | 79 +++++++++++++++++++++++++++++++++++++------= ---- 2 files changed, 63 insertions(+), 17 deletions(-) diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 1b5eb22c26..81fc179459 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -59,6 +59,7 @@ typedef enum TCGReg { #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND +#define FACILITY_LOAD_ON_COND2 (1ULL << (63 - 53)) =20 extern uint64_t s390_facilities; =20 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index a80b07db65..0de968fde2 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -122,6 +122,7 @@ typedef enum S390Opcode { RIE_CLGIJ =3D 0xec7d, RIE_CLRJ =3D 0xec77, RIE_CRJ =3D 0xec76, + RIE_LOCGHI =3D 0xec46, RIE_RISBG =3D 0xec55, =20 RRE_AGR =3D 0xb908, @@ -495,6 +496,13 @@ static void tcg_out_insn_RI(TCGContext *s, S390Opcode = op, TCGReg r1, int i2) tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff)); } =20 +static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1, + int i2, int m3) +{ + tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3); + tcg_out32(s, (i2 << 16) | (op & 0xff)); +} + static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int = i2) { tcg_out16(s, op | (r1 << 4)); @@ -1063,7 +1071,20 @@ static void tgen_setcond(TCGContext *s, TCGType type= , TCGCond cond, TCGReg dest, TCGReg c1, TCGArg c2, int c2const) { int cc; + bool have_loc; =20 + /* With LOC2, we can always emit the minimum 3 insns. */ + if (s390_facilities & FACILITY_LOAD_ON_COND2) { + /* Emit: d =3D 0, d =3D (cc ? 1 : d). */ + cc =3D tgen_cmp(s, type, cond, c1, c2, c2const, false); + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc); + return; + } + + have_loc =3D (s390_facilities & FACILITY_LOAD_ON_COND) !=3D 0; + + /* For HAVE_LOC, only the path through do_greater is smaller. */ switch (cond) { case TCG_COND_GTU: case TCG_COND_GT: @@ -1076,6 +1097,9 @@ static void tgen_setcond(TCGContext *s, TCGType type,= TCGCond cond, return; =20 case TCG_COND_GEU: + if (have_loc) { + goto do_loc; + } do_geu: /* We need "real" carry semantics, so use SUBTRACT LOGICAL instead of COMPARE LOGICAL. This may need an extra move. */ @@ -1105,10 +1129,17 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, return; =20 case TCG_COND_LEU: + if (have_loc) { + goto do_loc; + } + /* fallthru */ case TCG_COND_LTU: case TCG_COND_LT: /* Swap operands so that we can use GEU/GTU/GT. */ if (c2const) { + if (have_loc) { + goto do_loc; + } tcg_out_movi(s, type, TCG_TMP0, c2); c2 =3D c1; c2const =3D 0; @@ -1133,6 +1164,9 @@ static void tgen_setcond(TCGContext *s, TCGType type,= TCGCond cond, break; =20 case TCG_COND_EQ: + if (have_loc) { + goto do_loc; + } /* X =3D=3D 0 is X <=3D 0 is 0 >=3D X. */ if (c2const && c2 =3D=3D 0) { tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0); @@ -1148,33 +1182,39 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, } =20 cc =3D tgen_cmp(s, type, cond, c1, c2, c2const, false); - if (s390_facilities & FACILITY_LOAD_ON_COND) { - /* Emit: d =3D 0, t =3D 1, d =3D (cc ? t : d). */ - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); - tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); - } else { - /* Emit: d =3D 1; if (cc) goto over; d =3D 0; over: */ - tcg_out_movi(s, type, dest, 1); - tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); - tcg_out_movi(s, type, dest, 0); - } + /* Emit: d =3D 1; if (cc) goto over; d =3D 0; over: */ + tcg_out_movi(s, type, dest, 1); + tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); + tcg_out_movi(s, type, dest, 0); + return; + + do_loc: + cc =3D tgen_cmp(s, type, cond, c1, c2, c2const, false); + /* Emit: d =3D 0, t =3D 1, d =3D (cc ? t : d). */ + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); + tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); } =20 static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg de= st, - TCGReg c1, TCGArg c2, int c2const, TCGReg r3) + TCGReg c1, TCGArg c2, int c2const, + TCGArg v3, int v3const) { int cc; if (s390_facilities & FACILITY_LOAD_ON_COND) { cc =3D tgen_cmp(s, type, c, c1, c2, c2const, false); - tcg_out_insn(s, RRF, LOCGR, dest, r3, cc); + if (v3const) { + tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc); + } else { + tcg_out_insn(s, RRF, LOCGR, dest, v3, cc); + } } else { c =3D tcg_invert_cond(c); cc =3D tgen_cmp(s, type, c, c1, c2, c2const, false); =20 /* Emit: if (cc) goto over; dest =3D r3; over: */ tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); - tcg_out_insn(s, RRE, LGR, dest, r3); + tcg_out_insn(s, RRE, LGR, dest, v3); } } =20 @@ -1937,7 +1977,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, break; case INDEX_op_movcond_i32: tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], - args[2], const_args[2], args[3]); + args[2], const_args[2], args[3], const_args[3]); break; =20 case INDEX_op_qemu_ld_i32: @@ -2170,7 +2210,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, break; case INDEX_op_movcond_i64: tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], - args[2], const_args[2], args[3]); + args[2], const_args[2], args[3], const_args[3]); break; =20 OP_32_64(deposit): @@ -2391,7 +2431,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOp= code op) =3D { .args_ct_str =3D { "r", "r", "rZ", "r", "0" } }; static const TCGTargetOpDef movc_c =3D { .args_ct_str =3D { "r", "r", "rC", "r", "0" } }; - return (s390_facilities & FACILITY_EXT_IMM ? &movc_c : &movc_z= ); + static const TCGTargetOpDef movc_l + =3D { .args_ct_str =3D { "r", "r", "rC", "rI", "0" } }; + return (s390_facilities & FACILITY_EXT_IMM + ? (s390_facilities & FACILITY_LOAD_ON_COND2 + ? &movc_l : &movc_c) + : &movc_z); } case INDEX_op_div2_i32: case INDEX_op_div2_i64: --=20 2.13.3 From nobody Sat Apr 27 19:54:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501824959747362.56720931248844; Thu, 3 Aug 2017 22:35:59 -0700 (PDT) Received: from localhost ([::1]:35885 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVHC-0005ye-8Z for importer@patchew.org; Fri, 04 Aug 2017 01:35:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddVAJ-0007ol-90 for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddVAG-0001Kv-VU for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:51 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:33140) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddVAG-0001K6-Ow for qemu-devel@nongnu.org; Fri, 04 Aug 2017 01:28:48 -0400 Received: by mail-pf0-x241.google.com with SMTP id c65so839372pfl.0 for ; Thu, 03 Aug 2017 22:28:48 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id m5sm1053099pfg.22.2017.08.03.22.28.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 03 Aug 2017 22:28:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=oXYvLE8W8YadM64rw0/aki5E8ulI/G93cEBcIQM0j+U=; b=YUkjSd7tDVuxs6RejFWvNC2AxhtZiP5tZ6+hsGldJSKioY6QbI43ahhLEodP4xhaSY 5qcgXS+608TTwDlrQBB/4mPpn+LHWjh6jFdT7WVk1/Sv4c7omcc5OvnQSeWnOdnzyc/d JyokV2gAG4ApCWoVe6gDKuFlFlo+0M8q/TfMUM2LYw69aR8jekFpwOOqavQJ0UDvdPn9 yaHFNKokP1WqU1l/jAD8hrDMbA5xVfjoRaQOi+o9h+mE3+wdFWm75wXvQI8R3Vd2ZoYG 8/VtCvZxV0WOBOLefw2+9pPjL+xR6DB+yP9NztQ6TV87hutdKRcAZw/+Oytxm6ovMrWy Z5+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=oXYvLE8W8YadM64rw0/aki5E8ulI/G93cEBcIQM0j+U=; b=o8Lzq9odC6d/TcvN1t6r3MT0SI9NcWVzOXaAA1C5qVu8NDo9joDVF3hikWmPGyWcSF q1QQ/MmbAFsbqTsODE+XyeTV9cdd0RCJZLURPYgbSEUpdxt02JmUMHCnbTsd63yFhUKV 1Ola97tHhqGjKzNLH33aWn3w9aLf2X5bMTweAz3zK6gMnanDwFwaWgj6AKVLVG49dA6w TZk4vTRZ+NqEyCACp7+QYE/KtT2WDSabIWkGWtc6e8xwYaLPjZgUbr5uI1QHfjixfUt0 RecD24ca/W0VLIucJVX1/vTa5kB4l6+nAz6SzG+D7wYQ2/FFCQvXcv+jL6F1Qtjyc5F/ esyg== X-Gm-Message-State: AIVw110jHiwhvYqEd+nZFRK5xevHycCQmPNcfGum2vJn1uZpoNkEKUpB Lliu9O6a3vRWiyCrwwA= X-Received: by 10.98.100.204 with SMTP id y195mr1145509pfb.303.1501824527599; Thu, 03 Aug 2017 22:28:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 3 Aug 2017 22:28:33 -0700 Message-Id: <20170804052833.10187-12-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170804052833.10187-1-rth@twiddle.net> References: <20170804052833.10187-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH 8/8] tcg/s390: Use slbgr for setcond le and leu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: borntraeger@de.ibm.com, cohuck@redhat.com, agraf@suse.de Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 119 +++++++++++++++++-------------------------= ---- 1 file changed, 43 insertions(+), 76 deletions(-) diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 0de968fde2..38b9e791ee 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1084,11 +1084,20 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, =20 have_loc =3D (s390_facilities & FACILITY_LOAD_ON_COND) !=3D 0; =20 - /* For HAVE_LOC, only the path through do_greater is smaller. */ + /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */ + restart: switch (cond) { + case TCG_COND_NE: + /* X !=3D 0 is X > 0. */ + if (c2const && c2 =3D=3D 0) { + cond =3D TCG_COND_GTU; + } else { + break; + } + /* fallthru */ + case TCG_COND_GTU: case TCG_COND_GT: - do_greater: /* The result of a compare has CC=3D2 for GT and CC=3D3 unused. ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */ tgen_cmp(s, type, cond, c1, c2, c2const, true); @@ -1096,49 +1105,33 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, tcg_out_insn(s, RRE, ALCGR, dest, dest); return; =20 - case TCG_COND_GEU: - if (have_loc) { - goto do_loc; - } - do_geu: - /* We need "real" carry semantics, so use SUBTRACT LOGICAL - instead of COMPARE LOGICAL. This may need an extra move. */ - if (c2const) { - tcg_out_mov(s, type, TCG_TMP0, c1); - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RIL, SLFI, TCG_TMP0, c2); - } else { - tcg_out_insn(s, RIL, SLGFI, TCG_TMP0, c2); - } - } else if (s390_facilities & FACILITY_DISTINCT_OPS) { - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RRF, SLRK, TCG_TMP0, c1, c2); - } else { - tcg_out_insn(s, RRF, SLGRK, TCG_TMP0, c1, c2); - } + case TCG_COND_EQ: + /* X =3D=3D 0 is X <=3D 0. */ + if (c2const && c2 =3D=3D 0) { + cond =3D TCG_COND_LEU; } else { - tcg_out_mov(s, type, TCG_TMP0, c1); - if (type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RR, SLR, TCG_TMP0, c2); - } else { - tcg_out_insn(s, RRE, SLGR, TCG_TMP0, c2); - } + break; } - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_insn(s, RRE, ALCGR, dest, dest); - return; + /* fallthru */ =20 case TCG_COND_LEU: - if (have_loc) { - goto do_loc; - } - /* fallthru */ + case TCG_COND_LE: + /* As above, but we're looking for borrow, or !carry. + The second insn computes d - d - borrow, or -1 for true + and 0 for false. So we must mask to 1 bit afterward. */ + tgen_cmp(s, type, cond, c1, c2, c2const, true); + tcg_out_insn(s, RRE, SLBGR, dest, dest); + tgen_andi(s, type, dest, 1); + return; + + case TCG_COND_GEU: case TCG_COND_LTU: case TCG_COND_LT: - /* Swap operands so that we can use GEU/GTU/GT. */ + case TCG_COND_GE: + /* Swap operands so that we can use LEU/GTU/GT/LE. */ if (c2const) { if (have_loc) { - goto do_loc; + break; } tcg_out_movi(s, type, TCG_TMP0, c2); c2 =3D c1; @@ -1149,51 +1142,25 @@ static void tgen_setcond(TCGContext *s, TCGType typ= e, TCGCond cond, c1 =3D c2; c2 =3D t; } - if (cond =3D=3D TCG_COND_LEU) { - goto do_geu; - } cond =3D tcg_swap_cond(cond); - goto do_greater; - - case TCG_COND_NE: - /* X !=3D 0 is X > 0. */ - if (c2const && c2 =3D=3D 0) { - cond =3D TCG_COND_GTU; - goto do_greater; - } - break; - - case TCG_COND_EQ: - if (have_loc) { - goto do_loc; - } - /* X =3D=3D 0 is X <=3D 0 is 0 >=3D X. */ - if (c2const && c2 =3D=3D 0) { - tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 0); - c2 =3D c1; - c2const =3D 0; - c1 =3D TCG_TMP0; - goto do_geu; - } - break; + goto restart; =20 default: - break; + g_assert_not_reached(); } =20 cc =3D tgen_cmp(s, type, cond, c1, c2, c2const, false); - /* Emit: d =3D 1; if (cc) goto over; d =3D 0; over: */ - tcg_out_movi(s, type, dest, 1); - tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); - tcg_out_movi(s, type, dest, 0); - return; - - do_loc: - cc =3D tgen_cmp(s, type, cond, c1, c2, c2const, false); - /* Emit: d =3D 0, t =3D 1, d =3D (cc ? t : d). */ - tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); - tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); + if (have_loc) { + /* Emit: d =3D 0, t =3D 1, d =3D (cc ? t : d). */ + tcg_out_movi(s, TCG_TYPE_I64, dest, 0); + tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); + tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc); + } else { + /* Emit: d =3D 1; if (cc) goto over; d =3D 0; over: */ + tcg_out_movi(s, type, dest, 1); + tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1); + tcg_out_movi(s, type, dest, 0); + } } =20 static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg de= st, --=20 2.13.3