From nobody Wed Nov 5 00:16:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500930345864879.5534094953707; Mon, 24 Jul 2017 14:05:45 -0700 (PDT) Received: from localhost ([::1]:57033 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZkXv-0006nE-J5 for importer@patchew.org; Mon, 24 Jul 2017 17:05:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58399) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZkVV-0005Sb-Vi for qemu-devel@nongnu.org; Mon, 24 Jul 2017 17:03:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZkVS-0002UD-Ri for qemu-devel@nongnu.org; Mon, 24 Jul 2017 17:03:13 -0400 Received: from mail-yw0-x244.google.com ([2607:f8b0:4002:c05::244]:37047) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZkVS-0002Tt-NQ for qemu-devel@nongnu.org; Mon, 24 Jul 2017 17:03:10 -0400 Received: by mail-yw0-x244.google.com with SMTP id h189so5752235ywf.4 for ; Mon, 24 Jul 2017 14:03:09 -0700 (PDT) Received: from localhost.localdomain ([98.192.46.210]) by smtp.gmail.com with ESMTPSA id h186sm2618488ywf.11.2017.07.24.14.03.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 24 Jul 2017 14:03:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=vatdRTjiux8E8PXafzSM4YbAuBYxKeLh/OjPzutuiEo=; b=OTRS7VwTHK71EvVs0AQT5OT0rVhfjhDrR4Gp1M85/9FeK9nvgnRM9Mae2bBGVHHQwK xkH9GtyJl5OQ/8hDGnSQkNmu0DvcuCRq4BEAptyb+bgsFtnPMqiZ08z07wSm2K08FJyt cAzzZKmynYQNd7AgLL4NUzrqy6s8Pv5KOUTQuJodkLjNO5mnHVfWYGK+IS1Ph14yMBDW XzlXNIfdXKkSLjw/yGDcokftF0RHle1IrNil3ssGZBhIzuv8H9+VYGBF+DmysBlAJT86 DPUqVCrfvw+WX19m8skwLLKH1nBbVLdSM91OZk8khHbKG136V5nknAN2CkuYuJ8idH6I uTVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=vatdRTjiux8E8PXafzSM4YbAuBYxKeLh/OjPzutuiEo=; b=G++BimqgQ6Ay+aEd2iJJ/XcUFJsLTqUTbsSJciq/yPLVGjb1oWHKEjaHS+YNHEl8B9 1Camd1u3yr6lWHTwFSpVXQjgOvCrcTfOdRPbxX5JyAXCB7txkm2B6uVXrCKyEaFnVBgD sinr9YaBK7J7xyTWIAkVPueYg+lLg/WNJiLNdhdxevTb9YaDtdSXa++LRFntQtDOrXnS dJ5X8R9LBlMgBaJiKQQoFLNWBjv7gU+6CwqXdcWvbuppSBvtVI78XSUcQlJRhx9oRN2W 5XKVObZD/dJPLjlBsTZzxyz5/xVWqBTDEEzv3D/bPzbG4KioNKilHdBhieCrPmI8Yt8q 4T/Q== X-Gm-Message-State: AIVw113XOJl5LEnt0IOjEeg6b5DGaegIIPXtJA3aGqJ6CqocR3/YaLXl BmhwgxzPUKb0RA== X-Received: by 10.129.90.131 with SMTP id o125mr14209019ywb.61.1500930187598; Mon, 24 Jul 2017 14:03:07 -0700 (PDT) From: Pranith Kumar To: alex.bennee@linaro.org Date: Mon, 24 Jul 2017 17:03:06 -0400 Message-Id: <20170724210306.18428-1-bobby.prani@gmail.com> X-Mailer: git-send-email 2.13.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4002:c05::244 Subject: [Qemu-devel] [RFC PATCH] tcg/softmmu: Increase size of TLB cache X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch increases the number of entries we allow in the TLB. I went over a few architectures to see if increasing it is problematic. Only armv6 seems to have a limitation that only 8 bits can be used for indexing these entries. For other architectures, I increased the number of TLB entries to a 4K-sized cache. Signed-off-by: Pranith Kumar --- include/exec/cpu-defs.h | 5 ++++- tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 1 + tcg/s390/tcg-target.h | 1 + tcg/sparc/tcg-target.h | 1 + 6 files changed, 10 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 29b3c2ada8..cb81232b83 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -64,6 +64,9 @@ typedef uint64_t target_ulong; #define CPU_TLB_ENTRY_BITS 5 #endif =20 +#ifndef CPU_TLB_BITS_MAX +# define CPU_TLB_BITS_MAX 8 +#endif /* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in CPU_TLB_BITS to ensure that * the TLB is not unnecessarily small, but still small enough for the * TLB lookup instruction sequence used by the TCG target. @@ -87,7 +90,7 @@ typedef uint64_t target_ulong; * of tlb_table inside env (which is non-trivial but not huge). */ #define CPU_TLB_BITS \ - MIN(8, \ + MIN(CPU_TLB_BITS_MAX, \ TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ (NB_MMU_MODES <=3D 1 ? 0 : \ NB_MMU_MODES <=3D 2 ? 1 : \ diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 55a46ac825..f428e09c98 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -15,6 +15,7 @@ =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24 +#define CPU_TLB_BITS_MAX 12 #undef TCG_TARGET_STACK_GROWSUP =20 typedef enum { diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 73a15f7e80..35c27a977b 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -162,6 +162,8 @@ extern bool have_popcnt; # define TCG_AREG0 TCG_REG_EBP #endif =20 +#define CPU_TLB_BITS_MAX 12 + static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d75cb63ed3..fd9046b7ad 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -37,6 +37,7 @@ =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 +#define CPU_TLB_BITS_MAX 12 #define TCG_TARGET_NB_REGS 32 =20 typedef enum { diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 957f0c0afe..218be322ad 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -27,6 +27,7 @@ =20 #define TCG_TARGET_INSN_UNIT_SIZE 2 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 19 +#define CPU_TLB_BITS_MAX 12 =20 typedef enum TCGReg { TCG_REG_R0 =3D 0, diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 854a0afd70..9fd59a64f2 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -29,6 +29,7 @@ =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 +#define CPU_TLB_BITS_MAX 12 #define TCG_TARGET_NB_REGS 32 =20 typedef enum { --=20 2.13.0