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X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH v15 24/32] target/arm: [tcg] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002534291.22386.13499916738708680298.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.c | 161 ++++++++++++++++++++++++++-------------------= ---- 1 file changed, 84 insertions(+), 77 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0b4cb1e463..bacc0303e5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12027,85 +12027,13 @@ static void arm_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) dc->base.pc_next =3D dc->pc; } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { - DisasContext dc1, *dc =3D &dc1; - int max_insns; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_tr_tb_start(&dc->base, cs); - - do { - dc->base.num_insns++; - arm_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { - gen_io_start(); - } - - arm_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >=3D max_insns)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - if (tb->cflags & CF_LAST_IO) { - if (dc->condjmp) { - /* FIXME: This can theoretically happen with self-modifying - code. */ - cpu_abort(cs, "IO on conditional branch instruction"); - } - gen_io_end(); + if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) { + /* FIXME: This can theoretically happen with self-modifying code. = */ + cpu_abort(cpu, "IO on conditional branch instruction"); } =20 /* At this stage dc->condjmp will only be set when the skipped @@ -12211,6 +12139,85 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) gen_goto_tb(dc, 1, dc->pc); } } +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext dc1, *dc =3D &dc1; + int max_insns; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cs, tb); + return; + } + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + + max_insns =3D tb->cflags & CF_COUNT_MASK; + if (max_insns =3D=3D 0) { + max_insns =3D CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns =3D TCG_MAX_INSNS; + } + max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); + + gen_tb_start(tb); + + tcg_clear_temp_count(); + arm_tr_tb_start(&dc->base, cs); + + do { + dc->base.num_insns++; + arm_tr_insn_start(&dc->base, cs); + + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc =3D=3D dc->base.pc_next) { + if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { + break; + } + } + } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } + } + + if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { + gen_io_start(); + } + + arm_tr_translate_insn(&dc->base, cs); + + if (tcg_check_temp_count()) { + fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", + dc->pc); + } + + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >=3D max_insns)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); + + if (dc->base.tb->cflags & CF_LAST_IO) { + gen_io_end(); + } + + arm_tr_tb_stop(&dc->base, cs); =20 gen_tb_end(tb, dc->base.num_insns); =20 --=20 2.13.3