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X-Received-From: 2607:f8b0:400d:c0d::243 Subject: [Qemu-devel] [PATCH v15 01/32] tcg: Add generic DISAS_NORETURN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 This will allow some amount of cleanup to happen before switching the backends over to enum DisasJumpType. Reviewed-by: Emilio G. Cota Reviewed-by: Llu=C3=ADs Vilanova Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 440fc31b37..b434988979 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -63,6 +63,7 @@ typedef ram_addr_t tb_page_addr_t; #define DISAS_JUMP 1 /* only pc was modified dynamically */ #define DISAS_TB_JUMP 2 /* only pc was modified statically */ #define DISAS_UPDATE 3 /* cpu state was modified dynamically */ +#define DISAS_NORETURN 4 /* the tb has already been exited */ =20 #include "qemu/log.h" =20 --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500928205380918.1789279951151; Mon, 24 Jul 2017 13:30:05 -0700 (PDT) Received: from localhost ([::1]:56824 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjzL-0004KY-G6 for importer@patchew.org; Mon, 24 Jul 2017 16:29:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47784) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjxW-0002zD-Q0 for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjxU-0000o0-HK for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:06 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:38314) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjxU-0000ne-D1 for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:04 -0400 Received: by mail-qk0-x244.google.com with SMTP id t2so10964718qkc.5 for ; Mon, 24 Jul 2017 13:28:04 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=e1zLnPcSL+Y9rFMgvWrzrPQPf34ZcPJgWCo7PZOIVo0=; b=bLgvd1h1XZIlUz8FXnFK7FcRgeS1ixx7sNUzDoAU4kdf/RTy76Nnk3d5+cD8MxM3gi 9aemcGk3ABH4ecBlSqmtdlOh3tg4bFqNk0+3sKOUMc+H3XD9+LTrZMoeJ3Oao9khFRZC 70brOEa4WIFJTnqtZeEmPjBZkeI+nbV5tYE1bdHankSIahff/yiFPnkR6d5oU8/wvqwW RwhN27fmR0tr+LcQFy/bqYvn1h/0Y2aTtz2mQ7zDT6sCp5Ck5rJFkTdaG4vofI4MFmAb 7Gb3VwCFg/wh8KHVVJsnUdrc87K/LM8jEobSArBClVVXX/1ZiJpqmrL79wAZd7465TbE r2Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=e1zLnPcSL+Y9rFMgvWrzrPQPf34ZcPJgWCo7PZOIVo0=; b=j/3dyFdWEnrqb8rqbBOk4pGuj0A0gMcpMzCRXqw4Qgw6b1XJaKTbAvBPPxMcJ7/IpN V7QO2DImPCKdsXJtOgoC28WSzJx4uBjzYCpv7DBqns66UQKRxoc9nQaOyCvvT4WT5bqz H9PnnbBXCpwtvzAcjKOVuTLwm5p+v0jptk61D3OlH/EC/tTgVFmznw7x6PIr0lrr4caY L89OfY3gV72uSND/w871XTDTAY66noQK3zDrr2osX4aKixnQ1qNAYA/92DAMQCV/0nlh luQ/jqqLwc2fKTa6fvGMGYLML8zgseyXxqMIq8KheafCIAOGsh3WmPP1X4YjRT5/Yv1f SSjg== X-Gm-Message-State: AIVw111U4nKwj5ri9UsgOoLzFgHIQEk7uEfXouJyX90x+LiTqOnFiY6O UOvIfuZBLRA2DKy548U= X-Received: by 10.233.237.211 with SMTP id c202mr21675863qkg.1.1500928083349; Mon, 24 Jul 2017 13:28:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:26:58 -0700 Message-Id: <20170724202728.25960-3-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH v15 02/32] target/i386: Use generic DISAS_* enumerators X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This target is not sophisticated in its use of cleanups at the end of the translation loop. For the most part, any condition that exits the TB is dealt with by emitting the exiting opcode right then and there. Therefore the only is_jmp indicator that is needed is DISAS_NORETURN. For two stack segment modifying cases, we have not yet exited the TB (therefore DISAS_NORETURN feels wrong), but intend to exit. The caller of gen_movl_seg_T0 currently checks for any non-zero value, therefore DISAS_TOO_MANY seems acceptable for that usage. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/i386/translate.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index cab9e32f91..3ffbf1bb4e 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -31,6 +31,7 @@ #include "trace-tcg.h" #include "exec/log.h" =20 +#define DISAS_TOO_MANY 5 =20 #define PREFIX_REPZ 0x01 #define PREFIX_REPNZ 0x02 @@ -2153,6 +2154,7 @@ static inline void gen_goto_tb(DisasContext *s, int t= b_num, target_ulong eip) tcg_gen_goto_tb(tb_num); gen_jmp_im(eip); tcg_gen_exit_tb((uintptr_t)s->tb + tb_num); + s->is_jmp =3D DISAS_NORETURN; } else { /* jump to another page */ gen_jmp_im(eip); @@ -2173,7 +2175,6 @@ static inline void gen_jcc(DisasContext *s, int b, =20 gen_set_label(l1); gen_goto_tb(s, 1, val); - s->is_jmp =3D DISAS_TB_JUMP; } else { l1 =3D gen_new_label(); l2 =3D gen_new_label(); @@ -2243,12 +2244,14 @@ static void gen_movl_seg_T0(DisasContext *s, int se= g_reg) because ss32 may change. For R_SS, translation must always stop as a special handling must be done to disable hardware interrupts for the next instruction */ - if (seg_reg =3D=3D R_SS || (s->code32 && seg_reg < R_FS)) - s->is_jmp =3D DISAS_TB_JUMP; + if (seg_reg =3D=3D R_SS || (s->code32 && seg_reg < R_FS)) { + s->is_jmp =3D DISAS_TOO_MANY; + } } else { gen_op_movl_seg_T0_vm(seg_reg); - if (seg_reg =3D=3D R_SS) - s->is_jmp =3D DISAS_TB_JUMP; + if (seg_reg =3D=3D R_SS) { + s->is_jmp =3D DISAS_TOO_MANY; + } } } =20 @@ -2420,7 +2423,7 @@ static void gen_exception(DisasContext *s, int trapno= , target_ulong cur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 /* Generate #UD for the current instruction. The assumption here is that @@ -2458,7 +2461,7 @@ static void gen_interrupt(DisasContext *s, int intno, gen_jmp_im(cur_eip); gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), tcg_const_i32(next_eip - cur_eip)); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_debug(DisasContext *s, target_ulong cur_eip) @@ -2466,7 +2469,7 @@ static void gen_debug(DisasContext *s, target_ulong c= ur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_debug(cpu_env); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_set_hflag(DisasContext *s, uint32_t mask) @@ -2541,7 +2544,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool= recheck_tf, TCGv jr) } else { tcg_gen_exit_tb(0); } - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 static inline void @@ -2580,7 +2583,6 @@ static void gen_jmp_tb(DisasContext *s, target_ulong = eip, int tb_num) set_cc_op(s, CC_OP_DYNAMIC); if (s->jmp_opt) { gen_goto_tb(s, tb_num, eip); - s->is_jmp =3D DISAS_TB_JUMP; } else { gen_jmp_im(eip); gen_eob(s); @@ -6942,7 +6944,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } break; case 0x9b: /* fwait */ @@ -7187,7 +7189,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } break; case 0x100: @@ -7370,7 +7372,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), tcg_const_i32(s->pc - pc_start)); tcg_gen_exit_tb(0); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; break; =20 case 0xd9: /* VMMCALL */ --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH v15 03/32] target/arm: Use DISAS_NORETURN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fold DISAS_EXC and DISAS_TB_JUMP into DISAS_NORETURN. In both cases all following code is dead. In the first case because we have exited the TB via exception; in the second case because we have exited the TB via goto_tb and its associated machinery. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.h | 8 ++------ target/arm/translate-a64.c | 37 ++++++++++++++++++++----------------- target/arm/translate.c | 14 ++++++++------ 3 files changed, 30 insertions(+), 29 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 2fe144baa9..90f64d9716 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -124,12 +124,8 @@ static void disas_set_insn_syndrome(DisasContext *s, u= int32_t syn) * defer them until after the conditional execution state has been updated. * WFI also needs special handling when single-stepping. */ -#define DISAS_WFI 4 -#define DISAS_SWI 5 -/* For instructions which unconditionally cause an exception we can skip - * emitting unreachable code at the end of the TB in the A64 decoder - */ -#define DISAS_EXC 6 +#define DISAS_WFI 5 +#define DISAS_SWI 6 /* WFE */ #define DISAS_WFE 7 #define DISAS_HVC 8 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 883e9df0c2..789c66e634 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -304,7 +304,7 @@ static void gen_exception_internal_insn(DisasContext *s= , int offset, int excp) { gen_a64_set_pc_im(s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -312,7 +312,7 @@ static void gen_exception_insn(DisasContext *s, int off= set, int excp, { gen_a64_set_pc_im(s->pc - offset); gen_exception(excp, syndrome, target_el); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_ss_advance(DisasContext *s) @@ -340,7 +340,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) @@ -371,7 +371,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, = uint64_t dest) tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); tcg_gen_exit_tb((intptr_t)tb + n); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } else { gen_a64_set_pc_im(dest); if (s->ss_active) { @@ -380,7 +380,7 @@ static inline void gen_goto_tb(DisasContext *s, int n, = uint64_t dest) gen_exception_internal(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_pc); - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } } } @@ -11305,7 +11305,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) assert(num_insns =3D=3D 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - dc->is_jmp =3D DISAS_EXC; + dc->is_jmp =3D DISAS_NORETURN; break; } =20 @@ -11332,21 +11332,25 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) gen_io_end(); } =20 - if (unlikely(cs->singlestep_enabled || dc->ss_active) - && dc->is_jmp !=3D DISAS_EXC) { + if (unlikely(cs->singlestep_enabled || dc->ss_active)) { /* Note that this means single stepping WFI doesn't halt the CPU. * For conditional branch insns this is harmless unreachable code = as * gen_goto_tb() has already handled emitting the debug exception * (and thus a tb-jump is not possible when singlestepping). */ - assert(dc->is_jmp !=3D DISAS_TB_JUMP); - if (dc->is_jmp !=3D DISAS_JUMP) { + switch (dc->is_jmp) { + default: gen_a64_set_pc_im(dc->pc); - } - if (cs->singlestep_enabled) { - gen_exception_internal(EXCP_DEBUG); - } else { - gen_step_complete_exception(dc); + /* fall through */ + case DISAS_JUMP: + if (cs->singlestep_enabled) { + gen_exception_internal(EXCP_DEBUG); + } else { + gen_step_complete_exception(dc); + } + break; + case DISAS_NORETURN: + break; } } else { switch (dc->is_jmp) { @@ -11356,8 +11360,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) case DISAS_JUMP: tcg_gen_lookup_and_goto_ptr(cpu_pc); break; - case DISAS_TB_JUMP: - case DISAS_EXC: + case DISAS_NORETURN: case DISAS_SWI: break; case DISAS_WFE: diff --git a/target/arm/translate.c b/target/arm/translate.c index d1a5f56998..699e810157 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -297,7 +297,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_singlestep_exception(DisasContext *s) @@ -1184,7 +1184,7 @@ static void gen_exception_internal_insn(DisasContext = *s, int offset, int excp) gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -1193,7 +1193,7 @@ static void gen_exception_insn(DisasContext *s, int o= ffset, int excp, gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception(excp, syn, target_el); - s->is_jmp =3D DISAS_EXC; + s->is_jmp =3D DISAS_NORETURN; } =20 /* Force a TB lookup after an instruction that changes the CPU state. */ @@ -11944,7 +11944,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) /* We always get here via a jump, so know we are not in a conditional execution block. */ gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp =3D DISAS_EXC; + dc->is_jmp =3D DISAS_NORETURN; break; } #endif @@ -12089,6 +12089,9 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) default: /* FIXME: Single stepping a WFI insn will not halt the CPU. */ gen_singlestep_exception(dc); + break; + case DISAS_NORETURN: + break; } } else { /* While branches must always occur at the end of an IT block, @@ -12113,8 +12116,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) /* indicate that the hash table must be used to find the next = TB */ tcg_gen_exit_tb(0); break; - case DISAS_TB_JUMP: - case DISAS_EXC: + case DISAS_NORETURN: /* nothing more to generate */ break; case DISAS_WFI: --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-devel] [PATCH v15 04/32] target: [tcg] Use a generic enum for DISAS_ values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Used later. An enum makes expected values explicit and bounds the value space of switches. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id: <150002049746.22386.2316077281615710615.stgit@frigg.lan> Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 30 ------------------------------ include/exec/translator.h | 40 ++++++++++++++++++++++++++++++++++++++++ target/arm/translate.h | 23 ++++++++++++++--------- target/arm/translate.c | 2 +- target/cris/translate.c | 7 ++++++- target/i386/translate.c | 3 +-- target/lm32/translate.c | 6 ++++++ target/m68k/translate.c | 7 ++++++- target/microblaze/translate.c | 6 ++++++ target/nios2/translate.c | 6 ++++++ target/openrisc/translate.c | 6 ++++++ target/s390x/translate.c | 3 ++- target/unicore32/translate.c | 7 ++++++- target/xtensa/translate.c | 4 ++++ 14 files changed, 104 insertions(+), 46 deletions(-) create mode 100644 include/exec/translator.h diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b434988979..ff8fbe423d 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -35,36 +35,6 @@ typedef abi_ulong tb_page_addr_t; typedef ram_addr_t tb_page_addr_t; #endif =20 -/* DisasContext is_jmp field values - * - * is_jmp starts as DISAS_NEXT. The translator will keep processing - * instructions until an exit condition is reached. If we reach the - * exit condition and is_jmp is still DISAS_NEXT (because of some - * other condition) we simply "jump" to the next address. - * The remaining exit cases are: - * - * DISAS_JUMP - Only the PC was modified dynamically (e.g computed) - * DISAS_TB_JUMP - Only the PC was modified statically (e.g. branch) - * - * In these cases as long as the PC is updated we can chain to the - * next TB either by exiting the loop or looking up the next TB via - * the loookup helper. - * - * DISAS_UPDATE - CPU State was modified dynamically - * - * This covers any other CPU state which necessities us exiting the - * TCG code to the main run-loop. Typically this includes anything - * that might change the interrupt state. - * - * Individual translators may define additional exit cases to deal - * with per-target special conditions. - */ -#define DISAS_NEXT 0 /* next instruction can be analyzed */ -#define DISAS_JUMP 1 /* only pc was modified dynamically */ -#define DISAS_TB_JUMP 2 /* only pc was modified statically */ -#define DISAS_UPDATE 3 /* cpu state was modified dynamically */ -#define DISAS_NORETURN 4 /* the tb has already been exited */ - #include "qemu/log.h" =20 void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb); diff --git a/include/exec/translator.h b/include/exec/translator.h new file mode 100644 index 0000000000..b51b8f8a4e --- /dev/null +++ b/include/exec/translator.h @@ -0,0 +1,40 @@ +/* + * Generic intermediate code generation. + * + * Copyright (C) 2016-2017 Llu=C3=ADs Vilanova + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef EXEC__TRANSLATOR_H +#define EXEC__TRANSLATOR_H + +/** + * DisasJumpType: + * @DISAS_NEXT: Next instruction in program order. + * @DISAS_TOO_MANY: Too many instructions translated. + * @DISAS_NORETURN: Following code is dead. + * @DISAS_TARGET_*: Start of target-specific conditions. + * + * What instruction to disassemble next. + */ +typedef enum DisasJumpType { + DISAS_NEXT, + DISAS_TOO_MANY, + DISAS_NORETURN, + DISAS_TARGET_0, + DISAS_TARGET_1, + DISAS_TARGET_2, + DISAS_TARGET_3, + DISAS_TARGET_4, + DISAS_TARGET_5, + DISAS_TARGET_6, + DISAS_TARGET_7, + DISAS_TARGET_8, + DISAS_TARGET_9, + DISAS_TARGET_10, + DISAS_TARGET_11, +} DisasJumpType; + +#endif /* EXEC__TRANSLATOR_H */ diff --git a/target/arm/translate.h b/target/arm/translate.h index 90f64d9716..1eb432dc2c 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -1,6 +1,9 @@ #ifndef TARGET_ARM_TRANSLATE_H #define TARGET_ARM_TRANSLATE_H =20 +#include "exec/translator.h" + + /* internal defines */ typedef struct DisasContext { target_ulong pc; @@ -119,29 +122,31 @@ static void disas_set_insn_syndrome(DisasContext *s, = uint32_t syn) s->insn_start_idx =3D 0; } =20 -/* target-specific extra values for is_jmp */ +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically= */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamical= ly */ /* These instructions trap after executing, so the A32/T32 decoder must * defer them until after the conditional execution state has been updated. * WFI also needs special handling when single-stepping. */ -#define DISAS_WFI 5 -#define DISAS_SWI 6 +#define DISAS_WFI DISAS_TARGET_2 +#define DISAS_SWI DISAS_TARGET_3 /* WFE */ -#define DISAS_WFE 7 -#define DISAS_HVC 8 -#define DISAS_SMC 9 -#define DISAS_YIELD 10 +#define DISAS_WFE DISAS_TARGET_4 +#define DISAS_HVC DISAS_TARGET_5 +#define DISAS_SMC DISAS_TARGET_6 +#define DISAS_YIELD DISAS_TARGET_7 /* M profile branch which might be an exception return (and so needs * custom end-of-TB code) */ -#define DISAS_BX_EXCRET 11 +#define DISAS_BX_EXCRET DISAS_TARGET_8 /* For instructions which want an immediate exit to the main loop, * as opposed to attempting to use lookup_and_goto_ptr. Unlike * DISAS_UPDATE this doesn't write the PC on exiting the translation * loop so you need to ensure something (gen_a64_set_pc_im or runtime * helper) has done so before we reach return from cpu_tb_exec. */ -#define DISAS_EXIT 12 +#define DISAS_EXIT DISAS_TARGET_9 =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); diff --git a/target/arm/translate.c b/target/arm/translate.c index 699e810157..2bde418ddf 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4174,7 +4174,7 @@ static void gen_goto_tb(DisasContext *s, int n, targe= t_ulong dest) gen_set_pc_im(s, dest); gen_goto_ptr(); } - s->is_jmp =3D DISAS_TB_JUMP; + s->is_jmp =3D DISAS_NORETURN; } =20 static inline void gen_jmp (DisasContext *s, uint32_t dest) diff --git a/target/cris/translate.c b/target/cris/translate.c index 12b96eb68f..38a999e6f1 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -31,6 +31,7 @@ #include "exec/helper-proto.h" #include "mmu.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" #include "crisv32-decode.h" =20 #include "exec/helper-gen.h" @@ -50,7 +51,11 @@ #define BUG() (gen_BUG(dc, __FILE__, __LINE__)) #define BUG_ON(x) ({if (x) BUG();}) =20 -#define DISAS_SWI 5 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ +#define DISAS_SWI DISAS_TARGET_3 =20 /* Used by the decoder. */ #define EXTRACT_FIELD(src, start, end) \ diff --git a/target/i386/translate.c b/target/i386/translate.c index 3ffbf1bb4e..11bc4559af 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "tcg-op.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -31,8 +32,6 @@ #include "trace-tcg.h" #include "exec/log.h" =20 -#define DISAS_TOO_MANY 5 - #define PREFIX_REPZ 0x01 #define PREFIX_REPNZ 0x02 #define PREFIX_LOCK 0x04 diff --git a/target/lm32/translate.c b/target/lm32/translate.c index f68f372f15..65bc9c0bf6 100644 --- a/target/lm32/translate.c +++ b/target/lm32/translate.c @@ -22,6 +22,7 @@ #include "disas/disas.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/translator.h" #include "tcg-op.h" =20 #include "exec/cpu_ldst.h" @@ -47,6 +48,11 @@ =20 #define MEM_INDEX 0 =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + static TCGv_env cpu_env; static TCGv cpu_R[32]; static TCGv cpu_pc; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index ada2a91b64..755d7795ee 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -25,6 +25,7 @@ #include "tcg-op.h" #include "qemu/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -173,7 +174,11 @@ static void do_writebacks(DisasContext *s) } } =20 -#define DISAS_JUMP_NEXT 4 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically= */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamical= ly */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically = */ +#define DISAS_JUMP_NEXT DISAS_TARGET_3 =20 #if defined(CONFIG_USER_ONLY) #define IS_USER(s) 1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index a24373c0be..bd43a42d4f 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -27,6 +27,7 @@ #include "microblaze-decode.h" #include "exec/cpu_ldst.h" #include "exec/helper-gen.h" +#include "exec/translator.h" =20 #include "trace-tcg.h" #include "exec/log.h" @@ -46,6 +47,11 @@ #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + static TCGv env_debug; static TCGv_env cpu_env; static TCGv cpu_R[32]; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 8b97d6585f..6b0961837d 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -29,6 +29,12 @@ #include "exec/helper-gen.h" #include "exec/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" + +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ =20 #define INSTRUCTION_FLG(func, flags) { (func), (flags) } #define INSTRUCTION(func) \ diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a01413113b..112db1ad0f 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -27,6 +27,7 @@ #include "qemu/log.h" #include "qemu/bitops.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -37,6 +38,11 @@ #define LOG_DIS(str, ...) \ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->pc, ## __VA_ARGS__) =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ + typedef struct DisasContext { TranslationBlock *tb; target_ulong pc; diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 48b71f9604..436295cc5f 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -76,7 +76,8 @@ typedef struct { } u; } DisasCompare; =20 -#define DISAS_EXCP 4 +/* is_jmp field values */ +#define DISAS_EXCP DISAS_TARGET_0 =20 #ifdef DEBUG_INLINE_BRANCHES static uint64_t inline_branch_hit[CC_OP_MAX]; diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index 8f30cff932..6c094d59d7 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -16,6 +16,7 @@ #include "tcg-op.h" #include "qemu/log.h" #include "exec/cpu_ldst.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -45,9 +46,13 @@ typedef struct DisasContext { #define IS_USER(s) 1 #endif =20 +/* is_jmp field values */ +#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ +#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ +#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ /* These instructions trap after executing, so defer them until after the conditional executions state has been updated. */ -#define DISAS_SYSCALL 5 +#define DISAS_SYSCALL DISAS_TARGET_3 =20 static TCGv_env cpu_env; static TCGv_i32 cpu_R[32]; diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index f3f0ff589c..d7bf07e8e6 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -38,6 +38,7 @@ #include "sysemu/sysemu.h" #include "exec/cpu_ldst.h" #include "exec/semihost.h" +#include "exec/translator.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -46,6 +47,9 @@ #include "exec/log.h" =20 =20 +/* is_jmp field values */ +#define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically= */ + typedef struct DisasContext { const XtensaConfig *config; TranslationBlock *tb; --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500928373023294.0006577361229; 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Mon, 24 Jul 2017 13:28:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:01 -0700 Message-Id: <20170724202728.25960-6-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-devel] [PATCH v15 05/32] target/arm: Delay check for magic kernel page X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There's nothing magic about the exception that we generate in order to execute the magic kernel page. We can and should allow gdb to set a breakpoint at this location. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 2bde418ddf..a2f368bacd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11938,17 +11938,6 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) 0); num_insns++; =20 -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >=3D 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp =3D DISAS_NORETURN; - break; - } -#endif - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { @@ -11980,6 +11969,17 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) gen_io_start(); } =20 +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >=3D 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); 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Mon, 24 Jul 2017 13:28:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:02 -0700 Message-Id: <20170724202728.25960-7-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH v15 06/32] tcg: Add generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002073981.22386.9870422422367410100.stgit@frigg.lan> [rth: Moved max_insns adjustment from tb_start to init_disas_context. Removed pc_next return from translate_insn. Removed tcg_check_temp_count from generic loop. Moved gen_io_end to exactly match gen_io_start. Use qemu_log instead of error_report for temporary leaks. Moved TB size/icount assignments before disas_log.] Signed-off-by: Richard Henderson --- include/exec/translator.h | 104 ++++++++++++++++++++++++++++++++++ accel/tcg/translator.c | 138 ++++++++++++++++++++++++++++++++++++++++++= ++++ accel/tcg/Makefile.objs | 1 + 3 files changed, 243 insertions(+) create mode 100644 accel/tcg/translator.c diff --git a/include/exec/translator.h b/include/exec/translator.h index b51b8f8a4e..e2dc2a04ae 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -10,6 +10,19 @@ #ifndef EXEC__TRANSLATOR_H #define EXEC__TRANSLATOR_H =20 +/* + * Include this header from a target-specific file, and add a + * + * DisasContextBase base; + * + * member in your target-specific DisasContext. + */ + + +#include "exec/exec-all.h" +#include "tcg/tcg.h" + + /** * DisasJumpType: * @DISAS_NEXT: Next instruction in program order. @@ -37,4 +50,95 @@ typedef enum DisasJumpType { DISAS_TARGET_11, } DisasJumpType; =20 +/** + * DisasContextBase: + * @tb: Translation block for this disassembly. + * @pc_first: Address of first guest instruction in this TB. + * @pc_next: Address of next guest instruction in this TB (current during + * disassembly). + * @is_jmp: What instruction to disassemble next. + * @num_insns: Number of translated instructions (including current). + * @singlestep_enabled: "Hardware" single stepping enabled. + * + * Architecture-agnostic disassembly context. + */ +typedef struct DisasContextBase { + TranslationBlock *tb; + target_ulong pc_first; + target_ulong pc_next; + DisasJumpType is_jmp; + unsigned int num_insns; + bool singlestep_enabled; +} DisasContextBase; + +/** + * TranslatorOps: + * @init_disas_context: + * Initialize the target-specific portions of DisasContext struct. + * The generic DisasContextBase has already been initialized. + * Return max_insns, modified as necessary by db->tb->flags. + * + * @tb_start: + * Emit any code required before the start of the main loop, + * after the generic gen_tb_start(). + * + * @insn_start: + * Emit the tcg_gen_insn_start opcode. + * + * @breakpoint_check: + * When called, the breakpoint has already been checked to match the = PC, + * but the target may decide the breakpoint missed the address + * (e.g., due to conditions encoded in their flags). Return true to + * indicate that the breakpoint did hit, in which case no more breakp= oints + * are checked. If the breakpoint did hit, emit any code required to + * signal the exception, and set db->is_jmp as necessary to terminate + * the main loop. + * + * @translate_insn: + * Disassemble one instruction and set db->pc_next for the start + * of the following instruction. Set db->is_jmp as necessary to + * terminate the main loop. + * + * @tb_stop: + * Emit any opcodes required to exit the TB, based on db->is_jmp. + * + * @disas_log: + * Print instruction disassembly to log. + */ +typedef struct TranslatorOps { + int (*init_disas_context)(DisasContextBase *db, CPUState *cpu, + int max_insns); + void (*tb_start)(DisasContextBase *db, CPUState *cpu); + void (*insn_start)(DisasContextBase *db, CPUState *cpu); + bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu, + const CPUBreakpoint *bp); + void (*translate_insn)(DisasContextBase *db, CPUState *cpu); + void (*tb_stop)(DisasContextBase *db, CPUState *cpu); + void (*disas_log)(const DisasContextBase *db, CPUState *cpu); +} TranslatorOps; + +/** + * translator_loop: + * @ops: Target-specific operations. + * @db: Disassembly context. + * @cpu: Target vCPU. + * @tb: Translation block. + * + * Generic translator loop. + * + * Translation will stop in the following cases (in order): + * - When is_jmp set by #TranslatorOps::breakpoint_check. + * - set to DISAS_TOO_MANY exits after translating one more insn + * - set to any other value than DISAS_NEXT exits immediately. + * - When is_jmp set by #TranslatorOps::translate_insn. + * - set to any value other than DISAS_NEXT exits immediately. + * - When the TCG operation buffer is full. + * - When single-stepping is enabled (system-wide or on the current vCPU). + * - When too many instructions have been translated. + */ +void translator_loop(const TranslatorOps *ops, DisasContextBase *db, + CPUState *cpu, TranslationBlock *tb); + +void translator_loop_temp_check(DisasContextBase *db); + #endif /* EXEC__TRANSLATOR_H */ diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c new file mode 100644 index 0000000000..afa3af478a --- /dev/null +++ b/accel/tcg/translator.c @@ -0,0 +1,138 @@ +/* + * Generic intermediate code generation. + * + * Copyright (C) 2016-2017 Llu=C3=ADs Vilanova + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/error-report.h" +#include "cpu.h" +#include "tcg/tcg.h" +#include "tcg/tcg-op.h" +#include "exec/exec-all.h" +#include "exec/gen-icount.h" +#include "exec/log.h" +#include "exec/translator.h" + +/* Pairs with tcg_clear_temp_count. + To be called by #TranslatorOps.{translate_insn,tb_stop} if + (1) the target is sufficiently clean to support reporting, + (2) as and when all temporaries are known to be consumed. + For most targets, (2) is at the end of translate_insn. */ +void translator_loop_temp_check(DisasContextBase *db) +{ + if (tcg_check_temp_count()) { + qemu_log("warning: TCG temporary leaks before " + TARGET_FMT_lx "\n", db->pc_next); + } +} + +void translator_loop(const TranslatorOps *ops, DisasContextBase *db, + CPUState *cpu, TranslationBlock *tb) +{ + int max_insns; + + /* Initialize DisasContext */ + db->tb =3D tb; + db->pc_first =3D tb->pc; + db->pc_next =3D db->pc_first; + db->is_jmp =3D DISAS_NEXT; + db->num_insns =3D 0; + db->singlestep_enabled =3D cpu->singlestep_enabled; + + /* Instruction counting */ + max_insns =3D db->tb->cflags & CF_COUNT_MASK; + if (max_insns =3D=3D 0) { + max_insns =3D CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns =3D TCG_MAX_INSNS; + } + if (db->singlestep_enabled || singlestep) { + max_insns =3D 1; + } + + max_insns =3D ops->init_disas_context(db, cpu, max_insns); + tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ + + /* Reset the temp count so that we can identify leaks */ + tcg_clear_temp_count(); + + /* Start translating. */ + gen_tb_start(db->tb); + ops->tb_start(db, cpu); + tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ + + while (true) { + db->num_insns++; + ops->insn_start(db, cpu); + tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit = */ + + /* Pass breakpoint hits to target for further processing */ + if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (bp->pc =3D=3D db->pc_next) { + if (ops->breakpoint_check(db, cpu, bp)) { + break; + } + } + } + /* The breakpoint_check hook may use DISAS_TOO_MANY to indicate + that only one more instruction is to be executed. Otherwise + it should use DISAS_NORETURN when generating an exception, + but may use a DISAS_TARGET_* value for Something Else. */ + if (db->is_jmp > DISAS_TOO_MANY) { + break; + } + } + + /* Disassemble one instruction. The translate_insn hook should + update db->pc_next and db->is_jmp to indicate what should be + done next -- either exiting this loop or locate the start of + the next instruction. */ + if (db->num_insns =3D=3D max_insns && (db->tb->cflags & CF_LAST_IO= )) { + /* Accept I/O on the last instruction. */ + gen_io_start(); + ops->translate_insn(db, cpu); + gen_io_end(); + } else { + ops->translate_insn(db, cpu); + } + + /* Stop translation if translate_insn so indicated. */ + if (db->is_jmp !=3D DISAS_NEXT) { + break; + } + + /* Stop translation if the output buffer is full, + or we have executed all of the allowed instructions. */ + if (tcg_op_buf_full() || db->num_insns >=3D max_insns) { + db->is_jmp =3D DISAS_TOO_MANY; + break; + } + } + + /* Emit code to exit the TB, as indicated by db->is_jmp. */ + ops->tb_stop(db, cpu); + gen_tb_end(db->tb, db->num_insns); + + /* The disas_log hook may use these values rather than recompute. */ + db->tb->size =3D db->pc_next - db->pc_first; + db->tb->icount =3D db->num_insns; + +#ifdef DEBUG_DISAS + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) + && qemu_log_in_addr_range(db->pc_first)) { + qemu_log_lock(); + qemu_log("----------------\n"); + ops->disas_log(db, cpu); + qemu_log("\n"); + qemu_log_unlock(); + } +#endif +} diff --git a/accel/tcg/Makefile.objs b/accel/tcg/Makefile.objs index 70cd474c01..22642e6f75 100644 --- a/accel/tcg/Makefile.objs +++ b/accel/tcg/Makefile.objs @@ -1,3 +1,4 @@ obj-$(CONFIG_SOFTMMU) +=3D tcg-all.o obj-$(CONFIG_SOFTMMU) +=3D cputlb.o obj-y +=3D cpu-exec.o cpu-exec-common.o translate-all.o +obj-y +=3D translator.o --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500928540108292.22583232427826; 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Mon, 24 Jul 2017 13:28:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:03 -0700 Message-Id: <20170724202728.25960-8-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::241 Subject: [Qemu-devel] [PATCH v15 07/32] target/i386: [tcg] Port to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002098212.22386.17313318023406046314.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 140 ++++++++++++++++++++++++--------------------= ---- 1 file changed, 69 insertions(+), 71 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 11bc4559af..7825593111 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -95,6 +95,8 @@ static int x86_64_hregs; #endif =20 typedef struct DisasContext { + DisasContextBase base; + /* current insn context */ int override; /* -1 if no override */ int prefix; @@ -102,8 +104,6 @@ typedef struct DisasContext { TCGMemOp dflag; target_ulong pc_start; target_ulong pc; /* pc =3D eip + cs_base */ - int is_jmp; /* 1 =3D means jump (stop translation), 2 means CPU - static state change (stop translation) */ /* current block context */ target_ulong cs_base; /* base of CS segment */ int pe; /* protected mode */ @@ -124,12 +124,10 @@ typedef struct DisasContext { int cpl; int iopl; int tf; /* TF cpu flag */ - int singlestep_enabled; /* "hardware" single step enabled */ int jmp_opt; /* use direct block chaining for direct jumps */ int repz_opt; /* optimize jumps within repz instructions */ int mem_index; /* select memory access functions */ uint64_t flags; /* all execution flags */ - struct TranslationBlock *tb; int popl_esp_hack; /* for correct popl with esp base handling */ int rip_offset; /* only used in x86_64, but left for simplicity */ int cpuid_features; @@ -1119,7 +1117,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_po= rt, int ot) =20 static inline void gen_ins(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_EDI(s); @@ -1134,14 +1132,14 @@ static inline void gen_ins(DisasContext *s, TCGMemO= p ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } =20 static inline void gen_outs(DisasContext *s, TCGMemOp ot) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_string_movl_A0_ESI(s); @@ -1154,7 +1152,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp= ot) gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_ESI); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } @@ -2137,7 +2135,7 @@ static inline int insn_const_size(TCGMemOp ot) static inline bool use_goto_tb(DisasContext *s, target_ulong pc) { #ifndef CONFIG_USER_ONLY - return (pc & TARGET_PAGE_MASK) =3D=3D (s->tb->pc & TARGET_PAGE_MASK) || + return (pc & TARGET_PAGE_MASK) =3D=3D (s->base.tb->pc & TARGET_PAGE_MA= SK) || (pc & TARGET_PAGE_MASK) =3D=3D (s->pc_start & TARGET_PAGE_MASK); #else return true; @@ -2152,8 +2150,8 @@ static inline void gen_goto_tb(DisasContext *s, int t= b_num, target_ulong eip) /* jump to same page: we can use a direct jump */ tcg_gen_goto_tb(tb_num); gen_jmp_im(eip); - tcg_gen_exit_tb((uintptr_t)s->tb + tb_num); - s->is_jmp =3D DISAS_NORETURN; + tcg_gen_exit_tb((uintptr_t)s->base.tb + tb_num); + s->base.is_jmp =3D DISAS_NORETURN; } else { /* jump to another page */ gen_jmp_im(eip); @@ -2244,12 +2242,12 @@ static void gen_movl_seg_T0(DisasContext *s, int se= g_reg) stop as a special handling must be done to disable hardware interrupts for the next instruction */ if (seg_reg =3D=3D R_SS || (s->code32 && seg_reg < R_FS)) { - s->is_jmp =3D DISAS_TOO_MANY; + s->base.is_jmp =3D DISAS_TOO_MANY; } } else { gen_op_movl_seg_T0_vm(seg_reg); if (seg_reg =3D=3D R_SS) { - s->is_jmp =3D DISAS_TOO_MANY; + s->base.is_jmp =3D DISAS_TOO_MANY; } } } @@ -2422,7 +2420,7 @@ static void gen_exception(DisasContext *s, int trapno= , target_ulong cur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 /* Generate #UD for the current instruction. The assumption here is that @@ -2460,7 +2458,7 @@ static void gen_interrupt(DisasContext *s, int intno, gen_jmp_im(cur_eip); gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), tcg_const_i32(next_eip - cur_eip)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_debug(DisasContext *s, target_ulong cur_eip) @@ -2468,7 +2466,7 @@ static void gen_debug(DisasContext *s, target_ulong c= ur_eip) gen_update_cc_op(s); gen_jmp_im(cur_eip); gen_helper_debug(cpu_env); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_set_hflag(DisasContext *s, uint32_t mask) @@ -2524,10 +2522,10 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bo= ol recheck_tf, TCGv jr) gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK); } =20 - if (s->tb->flags & HF_RF_MASK) { + if (s->base.tb->flags & HF_RF_MASK) { gen_helper_reset_rf(cpu_env); } - if (s->singlestep_enabled) { + if (s->base.singlestep_enabled) { gen_helper_debug(cpu_env); } else if (recheck_tf) { gen_helper_rechecking_single_step(cpu_env); @@ -2543,7 +2541,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool= recheck_tf, TCGv jr) } else { tcg_gen_exit_tb(0); } - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static inline void @@ -4416,7 +4414,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, } } =20 -/* convert one instruction. s->is_jmp is set if the translation must +/* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, target_ulong pc_start) @@ -5376,7 +5374,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_movl_seg_T0(s, reg); gen_pop_update(s, ot); /* Note that reg =3D=3D R_SS in gen_movl_seg_T0 always sets is_jmp= . */ - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); if (reg =3D=3D R_SS) { s->tf =3D 0; @@ -5391,7 +5389,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, ot =3D gen_pop_T0(s); gen_movl_seg_T0(s, (b >> 3) & 7); gen_pop_update(s, ot); - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -5442,7 +5440,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_movl_seg_T0(s, reg); /* Note that reg =3D=3D R_SS in gen_movl_seg_T0 always sets is_jmp= . */ - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); if (reg =3D=3D R_SS) { s->tf =3D 0; @@ -5651,7 +5649,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_movl_seg_T0(s, op); /* then put the data */ gen_op_mov_reg_v(ot, reg, cpu_T1); - if (s->is_jmp) { + if (s->base.is_jmp) { gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -6307,7 +6305,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); } else { gen_ins(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6322,7 +6320,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base= ); } else { gen_outs(s, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_jmp(s, s->pc - s->cs_base); } } @@ -6338,14 +6336,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, tcg_gen_movi_tl(cpu_T0, val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6359,14 +6357,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); =20 - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_movi_i32(cpu_tmp2_i32, val); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6377,14 +6375,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, tcg_gen_ext16u_tl(cpu_T0, cpu_regs[R_EDX]); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); gen_helper_in_func(ot, cpu_T1, cpu_tmp2_i32); gen_op_mov_reg_v(ot, R_EAX, cpu_T1); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6397,14 +6395,14 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, svm_is_rep(prefixes)); gen_op_mov_v_reg(ot, cpu_T1, R_EAX); =20 - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T0); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T1); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); gen_bpt_io(s, cpu_tmp2_i32, ot); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -6943,7 +6941,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } break; case 0x9b: /* fwait */ @@ -7112,11 +7110,11 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, case 0x131: /* rdtsc */ gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtsc(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7188,7 +7186,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } break; case 0x100: @@ -7371,7 +7369,7 @@ static target_ulong disas_insn(CPUX86State *env, Disa= sContext *s, gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), tcg_const_i32(s->pc - pc_start)); tcg_gen_exit_tb(0); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; break; =20 case 0xd9: /* VMMCALL */ @@ -7571,11 +7569,11 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, } gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdtscp(cpu_env); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); } @@ -7940,24 +7938,24 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); if (b & 2) { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_op_mov_v_reg(ot, cpu_T0, rm); gen_helper_write_crN(cpu_env, tcg_const_i32(reg), cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else { - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_read_crN(cpu_T0, cpu_env, tcg_const_i32(reg= )); gen_op_mov_reg_v(ot, rm, cpu_T0); - if (s->tb->cflags & CF_USE_ICOUNT) { + if (s->base.tb->cflags & CF_USE_ICOUNT) { gen_io_end(); } } @@ -8383,15 +8381,13 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) { CPUX86State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; - target_ulong pc_ptr; uint32_t flags; - target_ulong pc_start; target_ulong cs_base; int num_insns; int max_insns; =20 /* generate intermediate code */ - pc_start =3D tb->pc; + dc->base.pc_first =3D tb->pc; cs_base =3D tb->cs_base; flags =3D tb->flags; =20 @@ -8404,11 +8400,11 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) dc->cpl =3D (flags >> HF_CPL_SHIFT) & 3; dc->iopl =3D (flags >> IOPL_SHIFT) & 3; dc->tf =3D (flags >> TF_SHIFT) & 1; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; dc->cc_op =3D CC_OP_DYNAMIC; dc->cc_op_dirty =3D false; dc->cs_base =3D cs_base; - dc->tb =3D tb; + dc->base.tb =3D tb; dc->popl_esp_hack =3D 0; /* select memory access functions */ dc->mem_index =3D 0; @@ -8458,8 +8454,8 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) cpu_ptr1 =3D tcg_temp_new_ptr(); cpu_cc_srcT =3D tcg_temp_local_new(); =20 - dc->is_jmp =3D DISAS_NEXT; - pc_ptr =3D pc_start; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.pc_next =3D dc->base.pc_first; num_insns =3D 0; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { @@ -8471,37 +8467,38 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) =20 gen_tb_start(tb); for(;;) { - tcg_gen_insn_start(pc_ptr, dc->cc_op); + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); num_insns++; =20 /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cs, pc_ptr, + if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY))) { - gen_debug(dc, pc_ptr - dc->cs_base); + gen_debug(dc, dc->base.pc_next - dc->cs_base); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - pc_ptr +=3D 1; + dc->base.pc_next +=3D 1; goto done_generating; } if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } =20 - pc_ptr =3D disas_insn(env, dc, pc_ptr); + dc->base.pc_next =3D disas_insn(env, dc, dc->base.pc_next); /* stop translation if indicated */ - if (dc->is_jmp) + if (dc->base.is_jmp) { break; + } /* if single step mode, we generate only one instruction and generate an exception */ /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear the flag and abort the translation to give the irqs a change to be happen */ - if (dc->tf || dc->singlestep_enabled || + if (dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } @@ -8512,23 +8509,23 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) because an exception hasn't stopped this code. */ if ((tb->cflags & CF_USE_ICOUNT) - && ((pc_ptr & TARGET_PAGE_MASK) - !=3D ((pc_ptr + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MA= SK) - || (pc_ptr & ~TARGET_PAGE_MASK) =3D=3D 0)) { - gen_jmp_im(pc_ptr - dc->cs_base); + && ((dc->base.pc_next & TARGET_PAGE_MASK) + !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARG= ET_PAGE_MASK) + || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || - (pc_ptr - pc_start) >=3D (TARGET_PAGE_SIZE - 32) || + (dc->base.pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE = - 32) || num_insns >=3D max_insns) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } if (singlestep) { - gen_jmp_im(pc_ptr - dc->cs_base); + gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } @@ -8540,24 +8537,25 @@ done_generating: =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { + && qemu_log_in_addr_range(dc->base.pc_first)) { int disas_flags; qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); #ifdef TARGET_X86_64 if (dc->code64) disas_flags =3D 2; else #endif disas_flags =3D !dc->code32; - log_target_disas(cs, pc_start, pc_ptr - pc_start, disas_flags); + log_target_disas(cs, dc->base.pc_first, dc->base.pc_next - dc->bas= e.pc_first, + disas_flags); qemu_log("\n"); qemu_log_unlock(); } #endif =20 - tb->size =3D pc_ptr - pc_start; + tb->size =3D dc->base.pc_next - dc->base.pc_first; tb->icount =3D num_insns; } =20 --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH v15 08/32] target/i386: [tcg] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002122448.22386.16854673576827449259.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson --- target/i386/translate.c | 46 +++++++++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 7825593111..651abcaf38 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8376,20 +8376,13 @@ void tcg_x86_init(void) } } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cpu, + int max_insns) { - CPUX86State *env =3D cs->env_ptr; - DisasContext dc1, *dc =3D &dc1; - uint32_t flags; - target_ulong cs_base; - int num_insns; - int max_insns; - - /* generate intermediate code */ - dc->base.pc_first =3D tb->pc; - cs_base =3D tb->cs_base; - flags =3D tb->flags; + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUX86State *env =3D cpu->env_ptr; + uint32_t flags =3D dc->base.tb->flags; + target_ulong cs_base =3D dc->base.tb->cs_base; =20 dc->pe =3D (flags >> HF_PE_SHIFT) & 1; dc->code32 =3D (flags >> HF_CS32_SHIFT) & 1; @@ -8400,11 +8393,9 @@ void gen_intermediate_code(CPUState *cs, Translation= Block *tb) dc->cpl =3D (flags >> HF_CPL_SHIFT) & 3; dc->iopl =3D (flags >> IOPL_SHIFT) & 3; dc->tf =3D (flags >> TF_SHIFT) & 1; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; dc->cc_op =3D CC_OP_DYNAMIC; dc->cc_op_dirty =3D false; dc->cs_base =3D cs_base; - dc->base.tb =3D tb; dc->popl_esp_hack =3D 0; /* select memory access functions */ dc->mem_index =3D 0; @@ -8422,7 +8413,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) dc->code64 =3D (flags >> HF_CS64_SHIFT) & 1; #endif dc->flags =3D flags; - dc->jmp_opt =3D !(dc->tf || cs->singlestep_enabled || + dc->jmp_opt =3D !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); /* Do not optimize repz jumps at all in icount mode, because rep movsS instructions are execured with different paths @@ -8434,7 +8425,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) record/replay modes and there will always be an additional step for ecx=3D0 when icount is enabled. */ - dc->repz_opt =3D !dc->jmp_opt && !(tb->cflags & CF_USE_ICOUNT); + dc->repz_opt =3D !dc->jmp_opt && !(dc->base.tb->cflags & CF_USE_ICOUNT= ); #if 0 /* check addseg logic */ if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32)) @@ -8454,9 +8445,24 @@ void gen_intermediate_code(CPUState *cs, Translation= Block *tb) cpu_ptr1 =3D tcg_temp_new_ptr(); cpu_cc_srcT =3D tcg_temp_local_new(); =20 + return max_insns; +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + CPUX86State *env =3D cs->env_ptr; + DisasContext dc1, *dc =3D &dc1; + int num_insns; + int max_insns; + + /* generate intermediate code */ + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + dc->base.tb =3D tb; dc->base.is_jmp =3D DISAS_NEXT; + dc->base.pc_first =3D tb->pc; dc->base.pc_next =3D dc->base.pc_first; - num_insns =3D 0; + max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -8464,7 +8470,9 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + max_insns =3D i386_tr_init_disas_context(&dc->base, cs, max_insns); =20 + num_insns =3D 0; gen_tb_start(tb); for(;;) { tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); @@ -8497,7 +8505,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) the flag and abort the translation to give the irqs a change to be happen */ if (dc->tf || dc->base.singlestep_enabled || - (flags & HF_INHIBIT_IRQ_MASK)) { + (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH v15 09/32] target/i386: [tcg] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002146647.22386.13380064201042141261.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 651abcaf38..6e1243a5b4 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8448,6 +8448,13 @@ static int i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu, return max_insns; } =20 +static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8475,7 +8482,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) num_insns =3D 0; gen_tb_start(tb); for(;;) { - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); + i386_tr_insn_start(&dc->base, cs); num_insns++; =20 /* If RF is set, suppress an internally generated breakpoint. */ --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500928379604488.31588080945335; Mon, 24 Jul 2017 13:32:59 -0700 (PDT) Received: from localhost ([::1]:56840 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZk2E-0006cf-8K for importer@patchew.org; Mon, 24 Jul 2017 16:32:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47877) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjxh-00035x-Mw for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjxg-0000ws-In for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:17 -0400 Received: from mail-qt0-x244.google.com ([2607:f8b0:400d:c0d::244]:38075) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjxg-0000wX-E1 for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:16 -0400 Received: by mail-qt0-x244.google.com with SMTP id p3so2659767qtg.5 for ; Mon, 24 Jul 2017 13:28:16 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pxow/ZoGMOCKQCnQLTWk3nVwB5Q0HyJxs30356/F6VU=; b=WxhDHr5r68GpxosV34YqEqwJlHQ6TXf2E3Q9SSYhFCQX0OpF6UWHABNmXC9AFRIIxP f8RS2QHXoRwIymQwRPXcaYGuCqu/Bbydkht8RxzYpvpgz3MR80C24vhq8Ynxmswin/wq qFGw03bgcqM2bpG/NNCPH0zKXoH7NznwvfxMjfDdtAkY+XGMAHygk3EVsBAv6nUNMzW7 DgL5/3R8b+sp2qiELwb6VEaJT7wqBvJYROMm4dHfS1KjqO21PpbdfyiwqoK+ESHmmIE+ ADZR7vMId1eFYLK1vfcEB3LttdM3l+kx5lrSklQPmQa7zxV7ILX+AFuC/7/IycxU9rTm scpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pxow/ZoGMOCKQCnQLTWk3nVwB5Q0HyJxs30356/F6VU=; b=bi7EcTPXSmGFvzIbQaAsLhIqmwdGRTh8RQWDiGFBGy4Fob8siACjfktovk3xsoDECC WEf3i/Pco4XXST2gBzDGz+IBOfa0paRPkvD1L5YMZp9d1AxJxgWBI8NU9QTRcDaJLjQE V+I0AYSczXFtLO7UDQIPDdvff7gIBVJ8PBIm89aM4Ckn9Hdj02CU+jqjjXyy6KYrsOXO MeITVupv75xXu4a35mrdIWidSE9cy1G5X9pJktVqCvLI1/jchpfwvlNryMMnpy+biPSV nscRAtNjvI8tm83nuLYcqSky5QU4p1WqSKFx1hbDdR7HpIHCX/yurtFVc7dSdYpjyswd fBrg== X-Gm-Message-State: AIVw113Zssp3g6C8jIs5yIHl2LEwBQBa9IH1PoDBa8db2A4md0sjDPn+ gzYQkYKxvhgyshxBiUM= X-Received: by 10.200.45.236 with SMTP id q41mr22153304qta.177.1500928095542; Mon, 24 Jul 2017 13:28:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:06 -0700 Message-Id: <20170724202728.25960-11-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::244 Subject: [Qemu-devel] [PATCH v15 10/32] target/i386: [tcg] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Message-Id: <150002170871.22386.2172835658104140576.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 46 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 6e1243a5b4..a009710128 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8455,6 +8455,26 @@ static void i386_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } =20 +static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= pu, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + /* If RF is set, suppress an internally generated breakpoint. */ + int flags =3D dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; + if (bp->flags & flags) { + gen_debug(dc, dc->base.pc_next - dc->cs_base); + dc->base.is_jmp =3D DISAS_NORETURN; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + dc->base.pc_next +=3D 1; + return true; + } else { + return false; + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8485,18 +8505,21 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) i386_tr_insn_start(&dc->base, cs); num_insns++; =20 - /* If RF is set, suppress an internally generated breakpoint. */ - if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, - tb->flags & HF_RF_MASK - ? BP_GDB : BP_ANY))) { - gen_debug(dc, dc->base.pc_next - dc->cs_base); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 1; - goto done_generating; + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc =3D=3D dc->base.pc_next) { + if (i386_tr_breakpoint_check(&dc->base, cs, bp)) { + break; + } + } + } + + if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { + break; + } } + if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); } @@ -8547,7 +8570,6 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb) } if (tb->cflags & CF_LAST_IO) gen_io_end(); -done_generating: gen_tb_end(tb, num_insns); =20 #ifdef DEBUG_DISAS --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150092853610874.5754515967302; Mon, 24 Jul 2017 13:35:36 -0700 (PDT) Received: from localhost ([::1]:56850 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZk4j-0000IP-T0 for importer@patchew.org; Mon, 24 Jul 2017 16:35:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47900) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjxj-00037c-7R for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjxi-0000y9-7V for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:19 -0400 Received: from mail-qt0-x242.google.com ([2607:f8b0:400d:c0d::242]:38077) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjxi-0000xp-1l for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:18 -0400 Received: by mail-qt0-x242.google.com with SMTP id p3so2659830qtg.5 for ; Mon, 24 Jul 2017 13:28:17 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8+5B/JD3kHcj21DIDvw/SSRS3ZXXBydDaKEN3OumtUc=; b=ftBsSRnYKYtHWJuGHe4CXs9d5rLTY7FI+eLP8C26FGmdIXGOnw8Zb+CQRvDEAOQxDX bSmtSzflAC1EaXXIIjzI+UkLV2GOk7+OpO/JV94J/XoZBsgnX645yhPkElKiWDIaT3Sm DjZ01CX8z1KB70Xt1QZYIo7MpooaUrLxQDxrsbG08znTclU7sK8WZN6un8HXzIS53n3b IZbZh+uTVLJAB4h7LOyd9vZsG45vAsdeVTFqmSaCdQQcOW1kglsEW/lfGwfu8/2VJs0I XBz35Vw+H9FFPjyIHBkdUU4Me2wlubonVy4RgXqPglluKhSRA+iqSz6Yclg0GD42p0sX t0xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8+5B/JD3kHcj21DIDvw/SSRS3ZXXBydDaKEN3OumtUc=; b=CZiwXTS9phzjlZQRouSOzy9AFdLTb98tg4ow2oz3IqDOFmTNb+fZCLi46NTECSiLX5 iYL9pyYwmoPeL3pD/KZMvnWIi1KVsIydVoWVla6A3uQnftfXprF4vMx0EyBasE9MryHm X+R+y3wdxWaD0m0Ls67v0ExHMMvJ8phjIfYeILzgZHfeSzq8qoPpYDZnv0ZMEvucbRAd DY+tr5Qyh0LKtWyeltmp+ZzYn9voXa1ZUYMPsAGtQDQiFvFFYK30/ZNFaADr93Ol+PEF LwTfF1iL/CvhtBSOKDXKGtq25wlTlhk9+llcWCEEUWhrXhb4fYZGpTtLcz9i4oi+jtnY S//g== X-Gm-Message-State: AIVw113P44c6WhtBstdhYCzaO+KB9DLJpA2phxgZC7+mFjaxhlho9bkc tq5NKDq9mgbib6seVFc= X-Received: by 10.200.41.172 with SMTP id 41mr22957170qts.85.1500928097027; Mon, 24 Jul 2017 13:28:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:07 -0700 Message-Id: <20170724202728.25960-12-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::242 Subject: [Qemu-devel] [PATCH v15 11/32] target/i386: [tcg] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Message-Id: <150002195074.22386.16195894320027075398.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 66 +++++++++++++++++++++++++++++++--------------= ---- 1 file changed, 42 insertions(+), 24 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index a009710128..d350699ae9 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -4416,15 +4416,16 @@ static void gen_sse(CPUX86State *env, DisasContext = *s, int b, =20 /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ -static target_ulong disas_insn(CPUX86State *env, DisasContext *s, - target_ulong pc_start) +static target_ulong disas_insn(DisasContext *s, CPUState *cpu) { + CPUX86State *env =3D cpu->env_ptr; int b, prefixes; int shift; TCGMemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; int rex_w, rex_r; + target_ulong pc_start =3D s->base.pc_next; =20 s->pc_start =3D s->pc =3D pc_start; prefixes =3D 0; @@ -8475,10 +8476,46 @@ static bool i386_tr_breakpoint_check(DisasContextBa= se *dcbase, CPUState *cpu, } } =20 +static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong pc_next =3D disas_insn(dc, cpu); + + if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { + /* if single step mode, we generate only one instruction and + generate an exception */ + /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear + the flag and abort the translation to give the irqs a + chance to happen */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) + && ((dc->base.pc_next & TARGET_PAGE_MASK) + !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) + & TARGET_PAGE_MASK) + || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + /* Do not cross the boundary of the pages in icount mode, + it can cause an exception. Do it only when boundary is + crossed by the first instruction in the block. + If current instruction already crossed the bound - it's ok, + because an exception hasn't stopped this code. + */ + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else if ((pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE - 32))= { + gen_jmp_im(pc_next - dc->cs_base); + gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + + dc->base.pc_next =3D pc_next; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - CPUX86State *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; int num_insns; int max_insns; @@ -8524,39 +8561,20 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_io_start(); } =20 - dc->base.pc_next =3D disas_insn(env, dc, dc->base.pc_next); + i386_tr_translate_insn(&dc->base, cs); /* stop translation if indicated */ if (dc->base.is_jmp) { break; } /* if single step mode, we generate only one instruction and generate an exception */ - /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear - the flag and abort the translation to give the irqs a - change to be happen */ - if (dc->tf || dc->base.singlestep_enabled || - (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); - break; - } - /* Do not cross the boundary of the pages in icount mode, - it can cause an exception. Do it only when boundary is - crossed by the first instruction in the block. - If current instruction already crossed the bound - it's ok, - because an exception hasn't stopped this code. - */ - if ((tb->cflags & CF_USE_ICOUNT) - && ((dc->base.pc_next & TARGET_PAGE_MASK) - !=3D ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARG= ET_PAGE_MASK) - || (dc->base.pc_next & ~TARGET_PAGE_MASK) =3D=3D 0)) { + if (dc->base.singlestep_enabled) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || - (dc->base.pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE = - 32) || num_insns >=3D max_insns) { gen_jmp_im(dc->base.pc_next - dc->cs_base); gen_eob(dc); --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15009288653851.3871729641944057; Mon, 24 Jul 2017 13:41:05 -0700 (PDT) Received: from localhost ([::1]:56878 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZkA3-0004sA-UK for importer@patchew.org; Mon, 24 Jul 2017 16:41:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47911) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjxm-00038I-0W for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjxj-000106-JV for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:20 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:36111) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjxj-0000zT-FC for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:19 -0400 Received: by mail-qk0-x243.google.com with SMTP id d136so10952582qkg.3 for ; Mon, 24 Jul 2017 13:28:19 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CLwVGOKRQsutBOTTqx5sSDFXFfA6e0rG5H/pxiCA3Yg=; b=ij3hXI+vX0zOHzx/O4XZaH0DAw7F0CnpC08lWGIxjuLzoTlXZjeBXgT4musjPyKZkv a2YvF30hDgXaf7L2HTH710PwlxzWBAccRA7v2No9qDqB6SzhHJIsAIZSo1idIYtEbctW ZN8VXexposbP+l/+vH5zP1qeZf4AtaSPMJDmHYh0Oyh8iqKdwvnh6aav79q89fyZpbqr WZnjTwG8aAQbJ7KnDkYMft9y/StOo/Y5+TGPLmWu/3dWuXrIePTNBRTmq5xTPVn6V2ZY 7EvRucVF9ZELDkY8XbfzwaYYxWYJ0NCrfthGIKcT8kbEu75fO/Cpzuv5NW6lQ8IttvY6 Y9dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=CLwVGOKRQsutBOTTqx5sSDFXFfA6e0rG5H/pxiCA3Yg=; b=q3P26DOBcNbsPi8MmKnUy7att1Mw6cM1kAGdcObwAWZI7QeYXs0pyGkoYRexYLh1zb B/hEIQMctWsWzr9iGyaVjcO61RzA33hZL/sH7Y39RkG05w5/IBKgzZgWEipf+ynOonRU 9pKeLjIiy8BE/El2hZTD+FpeUkKlUuwMywYdaZ1zmeKxDiwOEMJDuScE46L9Eao38EX3 I2UcdnXUUhSgmxVUeuzKoLSs44sQ8TyAoAsgxDEcgPAwo8GDUcqhl2K412U3uNCC5Enn sKlu4LOjxhg1cpy1fc4Q5WoGGuDi9e+ZlI3Extthx4BfOFQnbC9Wutcw+jLJgOVHQCUU jspg== X-Gm-Message-State: AIVw111n3lwx/4NMxEveUrmdY6F0pYsYuNfYV3ivBP53S4OyGzy/x/V8 CKbIqMwLJKune9ROePY= X-Received: by 10.55.133.195 with SMTP id h186mr10765196qkd.21.1500928098735; Mon, 24 Jul 2017 13:28:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:08 -0700 Message-Id: <20170724202728.25960-13-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH v15 12/32] target/i386: [tcg] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id: <150002219289.22386.17959138704858928730.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index d350699ae9..8238533c0e 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8487,8 +8487,6 @@ static void i386_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cpu) /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear the flag and abort the translation to give the irqs a chance to happen */ - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp =3D DISAS_TOO_MANY; } else if ((dc->base.tb->cflags & CF_USE_ICOUNT) && ((dc->base.pc_next & TARGET_PAGE_MASK) @@ -8501,18 +8499,24 @@ static void i386_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) If current instruction already crossed the bound - it's ok, because an exception hasn't stopped this code. */ - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp =3D DISAS_TOO_MANY; } else if ((pc_next - dc->base.pc_first) >=3D (TARGET_PAGE_SIZE - 32))= { - gen_jmp_im(pc_next - dc->cs_base); - gen_eob(dc); dc->base.is_jmp =3D DISAS_TOO_MANY; } =20 dc->base.pc_next =3D pc_next; } =20 +static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (dc->base.is_jmp =3D=3D DISAS_TOO_MANY) { + gen_jmp_im(dc->base.pc_next - dc->cs_base); + gen_eob(dc); + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8569,23 +8573,21 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) /* if single step mode, we generate only one instruction and generate an exception */ if (dc->base.singlestep_enabled) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; break; } /* if too long translation, stop generation too */ if (tcg_op_buf_full() || num_insns >=3D max_insns) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; break; } if (singlestep) { - gen_jmp_im(dc->base.pc_next - dc->cs_base); - gen_eob(dc); + dc->base.is_jmp =3D DISAS_TOO_MANY; break; } } + i386_tr_tb_stop(&dc->base, cs); if (tb->cflags & CF_LAST_IO) gen_io_end(); gen_tb_end(tb, num_insns); --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500928609224732.585635333173; Mon, 24 Jul 2017 13:36:49 -0700 (PDT) Received: from localhost ([::1]:56857 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZk5u-0001Io-Rj for importer@patchew.org; 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Mon, 24 Jul 2017 13:28:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:09 -0700 Message-Id: <20170724202728.25960-14-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-devel] [PATCH v15 13/32] target/i386: [tcg] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Message-Id: <150002243497.22386.8888053391875656102.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson --- target/i386/translate.c | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 8238533c0e..8e7212cf92 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8517,6 +8517,21 @@ static void i386_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) } } =20 +static void i386_tr_disas_log(const DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + int disas_flags =3D !dc->code32; + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); +#ifdef TARGET_X86_64 + if (dc->code64) { + disas_flags =3D 2; + } +#endif + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flag= s); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -8592,28 +8607,19 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_io_end(); gen_tb_end(tb, num_insns); =20 + tb->size =3D dc->base.pc_next - dc->base.pc_first; + tb->icount =3D num_insns; + #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { - int disas_flags; qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); -#ifdef TARGET_X86_64 - if (dc->code64) - disas_flags =3D 2; - else -#endif - disas_flags =3D !dc->code32; - log_target_disas(cs, dc->base.pc_first, dc->base.pc_next - dc->bas= e.pc_first, - disas_flags); + i386_tr_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } #endif - - tb->size =3D dc->base.pc_next - dc->base.pc_first; - tb->icount =3D num_insns; } =20 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH v15 14/32] target/i386: [tcg] Port to generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Emilio G. Cota Tested-by: Emilio G. Cota Message-Id: <150002267714.22386.5095442346868988808.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/i386/translate.c | 106 +++++++++-----------------------------------= ---- 1 file changed, 19 insertions(+), 87 deletions(-) diff --git a/target/i386/translate.c b/target/i386/translate.c index 8e7212cf92..2bd667ec9a 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -8449,6 +8449,10 @@ static int i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu, return max_insns; } =20 +static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -8468,7 +8472,7 @@ static bool i386_tr_breakpoint_check(DisasContextBase= *dcbase, CPUState *cpu, /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ + the generic logic setting tb->size later does the right thing. = */ dc->base.pc_next +=3D 1; return true; } else { @@ -8532,94 +8536,22 @@ static void i386_tr_disas_log(const DisasContextBas= e *dcbase, log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flag= s); } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) -{ - DisasContext dc1, *dc =3D &dc1; - int num_insns; - int max_insns; - - /* generate intermediate code */ - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - dc->base.tb =3D tb; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.pc_first =3D tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - max_insns =3D i386_tr_init_disas_context(&dc->base, cs, max_insns); - - num_insns =3D 0; - gen_tb_start(tb); - for(;;) { - i386_tr_insn_start(&dc->base, cs); - num_insns++; - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (i386_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - - if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { - break; - } - } - - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { - gen_io_start(); - } - - i386_tr_translate_insn(&dc->base, cs); - /* stop translation if indicated */ - if (dc->base.is_jmp) { - break; - } - /* if single step mode, we generate only one instruction and - generate an exception */ - if (dc->base.singlestep_enabled) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - break; - } - /* if too long translation, stop generation too */ - if (tcg_op_buf_full() || - num_insns >=3D max_insns) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - break; - } - if (singlestep) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - break; - } - } - i386_tr_tb_stop(&dc->base, cs); - if (tb->cflags & CF_LAST_IO) - gen_io_end(); - gen_tb_end(tb, num_insns); +static const TranslatorOps i386_tr_ops =3D { + .init_disas_context =3D i386_tr_init_disas_context, + .tb_start =3D i386_tr_tb_start, + .insn_start =3D i386_tr_insn_start, + .breakpoint_check =3D i386_tr_breakpoint_check, + .translate_insn =3D i386_tr_translate_insn, + .tb_stop =3D i386_tr_tb_stop, + .disas_log =3D i386_tr_disas_log, +}; =20 - tb->size =3D dc->base.pc_next - dc->base.pc_first; - tb->icount =3D num_insns; +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc; =20 -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - i386_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif + translator_loop(&i386_tr_ops, &dc.base, cpu, tb); } =20 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500928936340891.0504437388687; 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Mon, 24 Jul 2017 13:28:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:11 -0700 Message-Id: <20170724202728.25960-16-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-devel] [PATCH v15 15/32] target/arm: [tcg] Port to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002291931.22386.11441154993010495674.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.h | 11 +++-- target/arm/translate-a64.c | 113 ++++++++++++++++++++++-------------------= -- target/arm/translate.c | 117 ++++++++++++++++++++++-------------------= ---- 3 files changed, 120 insertions(+), 121 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 1eb432dc2c..a804ff65ac 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -6,9 +6,10 @@ =20 /* internal defines */ typedef struct DisasContext { + DisasContextBase base; + target_ulong pc; uint32_t insn; - int is_jmp; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; /* The label that will be jumped to when the instruction is skipped. = */ @@ -16,8 +17,6 @@ typedef struct DisasContext { /* Thumb-2 conditional execution bits. */ int condexec_mask; int condexec_cond; - struct TranslationBlock *tb; - int singlestep_enabled; int thumb; int sctlr_b; TCGMemOp be_data; @@ -150,7 +149,8 @@ static void disas_set_insn_syndrome(DisasContext *s, ui= nt32_t syn) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb); +void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, + TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); @@ -159,7 +159,8 @@ static inline void a64_translate_init(void) { } =20 -static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlo= ck *tb) +static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUStat= e *cpu, + TranslationBlock *tb) { } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 789c66e634..7e2dee59ca 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -304,7 +304,7 @@ static void gen_exception_internal_insn(DisasContext *s= , int offset, int excp) { gen_a64_set_pc_im(s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -312,7 +312,7 @@ static void gen_exception_insn(DisasContext *s, int off= set, int excp, { gen_a64_set_pc_im(s->pc - offset); gen_exception(excp, syndrome, target_el); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_ss_advance(DisasContext *s) @@ -340,7 +340,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) @@ -348,13 +348,13 @@ static inline bool use_goto_tb(DisasContext *s, int n= , uint64_t dest) /* No direct tb linking with singlestep (either QEMU's or the ARM * debug architecture kind) or deterministic io */ - if (s->singlestep_enabled || s->ss_active || (s->tb->cflags & CF_LAST_= IO)) { + if (s->base.singlestep_enabled || s->ss_active || (s->base.tb->cflags = & CF_LAST_IO)) { return false; } =20 #ifndef CONFIG_USER_ONLY /* Only link tbs from inside the same guest page */ - if ((s->tb->pc & TARGET_PAGE_MASK) !=3D (dest & TARGET_PAGE_MASK)) { + if ((s->base.tb->pc & TARGET_PAGE_MASK) !=3D (dest & TARGET_PAGE_MASK)= ) { return false; } #endif @@ -366,21 +366,21 @@ static inline void gen_goto_tb(DisasContext *s, int n= , uint64_t dest) { TranslationBlock *tb; =20 - tb =3D s->tb; + tb =3D s->base.tb; if (use_goto_tb(s, n, dest)) { tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); tcg_gen_exit_tb((intptr_t)tb + n); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } else { gen_a64_set_pc_im(dest); if (s->ss_active) { gen_step_complete_exception(s); - } else if (s->singlestep_enabled) { + } else if (s->base.singlestep_enabled) { gen_exception_internal(EXCP_DEBUG); } else { tcg_gen_lookup_and_goto_ptr(cpu_pc); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } } } @@ -1331,16 +1331,16 @@ static void handle_hint(DisasContext *s, uint32_t i= nsn, case 0: /* NOP */ return; case 3: /* WFI */ - s->is_jmp =3D DISAS_WFI; + s->base.is_jmp =3D DISAS_WFI; return; case 1: /* YIELD */ if (!parallel_cpus) { - s->is_jmp =3D DISAS_YIELD; + s->base.is_jmp =3D DISAS_YIELD; } return; case 2: /* WFE */ if (!parallel_cpus) { - s->is_jmp =3D DISAS_WFE; + s->base.is_jmp =3D DISAS_WFE; } return; case 4: /* SEV */ @@ -1424,7 +1424,7 @@ static void handle_msr_i(DisasContext *s, uint32_t in= sn, tcg_temp_free_i32(tcg_op); /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ gen_a64_set_pc_im(s->pc); - s->is_jmp =3D (op =3D=3D 0x1f ? DISAS_EXIT : DISAS_JUMP); + s->base.is_jmp =3D (op =3D=3D 0x1f ? DISAS_EXIT : DISAS_JUMP); break; } default: @@ -1559,7 +1559,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, break; } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { gen_io_start(); } =20 @@ -1590,16 +1590,16 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, } } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } } =20 @@ -1789,7 +1789,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) } gen_helper_exception_return(cpu_env); /* Must exit loop to check un-masked IRQs */ - s->is_jmp =3D DISAS_EXIT; + s->base.is_jmp =3D DISAS_EXIT; return; case 5: /* DRPS */ if (rn !=3D 0x1f) { @@ -1803,7 +1803,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) return; } =20 - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; } =20 /* C3.2 Branches, exception generating and system instructions */ @@ -11179,23 +11179,23 @@ static void disas_a64_insn(CPUARMState *env, Disa= sContext *s) free_tmp_a64(s); } =20 -void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, + TranslationBlock *tb) { CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D arm_env_get_cpu(env); - DisasContext dc1, *dc =3D &dc1; - target_ulong pc_start; + DisasContext *dc =3D container_of(dcbase, DisasContext, base); target_ulong next_page_start; - int num_insns; int max_insns; =20 - pc_start =3D tb->pc; + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - dc->tb =3D tb; - - dc->is_jmp =3D DISAS_NEXT; - dc->pc =3D pc_start; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; =20 dc->aarch64 =3D 1; @@ -11206,17 +11206,17 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) !arm_el_is_aa64(env, 3); dc->thumb =3D 0; dc->sctlr_b =3D 0; - dc->be_data =3D ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; + dc->be_data =3D ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; dc->condexec_mask =3D 0; dc->condexec_cond =3D 0; - dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); - dc->tbi0 =3D ARM_TBFLAG_TBI0(tb->flags); - dc->tbi1 =3D ARM_TBFLAG_TBI1(tb->flags); + dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb= ->flags)); + dc->tbi0 =3D ARM_TBFLAG_TBI0(dc->base.tb->flags); + dc->tbi1 =3D ARM_TBFLAG_TBI1(dc->base.tb->flags); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(tb->flags); + dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D cpu->cp_regs; @@ -11237,16 +11237,15 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); + dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex =3D false; dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 init_tmp_a64_array(dc); =20 - next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns =3D 0; - max_insns =3D tb->cflags & CF_COUNT_MASK; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; + max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; } @@ -11259,9 +11258,9 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) tcg_clear_temp_count(); =20 do { + dc->base.num_insns++; dc->insn_start_idx =3D tcg_op_buf_count(); tcg_gen_insn_start(dc->pc, 0, 0); - num_insns++; =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; @@ -11271,14 +11270,14 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) gen_a64_set_pc_im(dc->pc); gen_helper_check_breakpoints(cpu_env); /* End the TB early; it likely won't be executed */ - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; } else { gen_exception_internal_insn(dc, 0, EXCP_DEBUG); /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order + included in [dc->base.tb->pc, dc->base.tb->pc += dc->base.tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting - tb->size below does the right thing. */ + dc->base.tb->size below does the right thing. = */ dc->pc +=3D 4; goto done_generating; } @@ -11287,7 +11286,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) } } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { gen_io_start(); } =20 @@ -11302,10 +11301,10 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns =3D=3D 1); + assert(dc->base.num_insns =3D=3D 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; break; } =20 @@ -11321,14 +11320,14 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - } while (!dc->is_jmp && !tcg_op_buf_full() && + } while (!dc->base.is_jmp && !tcg_op_buf_full() && !cs->singlestep_enabled && !singlestep && !dc->ss_active && dc->pc < next_page_start && - num_insns < max_insns); + dc->base.num_insns < max_insns); =20 - if (tb->cflags & CF_LAST_IO) { + if (dc->base.tb->cflags & CF_LAST_IO) { gen_io_end(); } =20 @@ -11338,7 +11337,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) * gen_goto_tb() has already handled emitting the debug exception * (and thus a tb-jump is not possible when singlestepping). */ - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { default: gen_a64_set_pc_im(dc->pc); /* fall through */ @@ -11353,7 +11352,7 @@ void gen_intermediate_code_a64(CPUState *cs, Transl= ationBlock *tb) break; } } else { - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, dc->pc); break; @@ -11393,20 +11392,20 @@ void gen_intermediate_code_a64(CPUState *cs, Tran= slationBlock *tb) } =20 done_generating: - gen_tb_end(tb, num_insns); + gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(pc_start)) { + qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size =3D dc->pc - pc_start; - tb->icount =3D num_insns; + dc->base.tb->size =3D dc->pc - dc->base.pc_first; + dc->base.tb->icount =3D dc->base.num_insns; } diff --git a/target/arm/translate.c b/target/arm/translate.c index a2f368bacd..55a2459a19 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -224,7 +224,7 @@ static void store_reg(DisasContext *s, int reg, TCGv_i3= 2 var) * We choose to ignore [1:0] in ARM mode for all architecture vers= ions. */ tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; } tcg_gen_mov_i32(cpu_R[reg], var); tcg_temp_free_i32(var); @@ -297,7 +297,7 @@ static void gen_step_complete_exception(DisasContext *s) gen_ss_advance(s); gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), default_exception_el(s)); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_singlestep_exception(DisasContext *s) @@ -321,7 +321,7 @@ static inline bool is_singlestepping(DisasContext *s) * misnamed as it only means "one instruction per TB" and doesn't * affect the code we generate. */ - return s->singlestep_enabled || s->ss_active; + return s->base.singlestep_enabled || s->ss_active; } =20 static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) @@ -930,7 +930,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t = addr) { TCGv_i32 tmp; =20 - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; if (s->thumb !=3D (addr & 1)) { tmp =3D tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, addr & 1); @@ -943,7 +943,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t = addr) /* Set PC and Thumb state from var. var is marked as dead. */ static inline void gen_bx(DisasContext *s, TCGv_i32 var) { - s->is_jmp =3D DISAS_JUMP; + s->base.is_jmp =3D DISAS_JUMP; tcg_gen_andi_i32(cpu_R[15], var, ~1); tcg_gen_andi_i32(var, var, 1); store_cpu_field(var, thumb); @@ -957,11 +957,11 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 v= ar) static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var) { /* Generate the same code here as for a simple bx, but flag via - * s->is_jmp that we need to do the rest of the work later. + * s->base.is_jmp that we need to do the rest of the work later. */ gen_bx(s, var); if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) { - s->is_jmp =3D DISAS_BX_EXCRET; + s->base.is_jmp =3D DISAS_BX_EXCRET; } } =20 @@ -1161,7 +1161,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) */ s->svc_imm =3D imm16; gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_HVC; + s->base.is_jmp =3D DISAS_HVC; } =20 static inline void gen_smc(DisasContext *s) @@ -1176,7 +1176,7 @@ static inline void gen_smc(DisasContext *s) gen_helper_pre_smc(cpu_env, tmp); tcg_temp_free_i32(tmp); gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_SMC; + s->base.is_jmp =3D DISAS_SMC; } =20 static void gen_exception_internal_insn(DisasContext *s, int offset, int e= xcp) @@ -1184,7 +1184,7 @@ static void gen_exception_internal_insn(DisasContext = *s, int offset, int excp) gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception_internal(excp); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_insn(DisasContext *s, int offset, int excp, @@ -1193,14 +1193,14 @@ static void gen_exception_insn(DisasContext *s, int= offset, int excp, gen_set_condexec(s); gen_set_pc_im(s, s->pc - offset); gen_exception(excp, syn, target_el); - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { tcg_gen_movi_i32(cpu_R[15], s->pc & ~1); - s->is_jmp =3D DISAS_EXIT; + s->base.is_jmp =3D DISAS_EXIT; } =20 static inline void gen_hlt(DisasContext *s, int imm) @@ -4145,7 +4145,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t i= nsn) static inline bool use_goto_tb(DisasContext *s, target_ulong dest) { #ifndef CONFIG_USER_ONLY - return (s->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MASK)= || + return (s->base.tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_= MASK) || ((s->pc - 1) & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MAS= K); #else return true; @@ -4169,12 +4169,12 @@ static void gen_goto_tb(DisasContext *s, int n, tar= get_ulong dest) if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); - tcg_gen_exit_tb((uintptr_t)s->tb + n); + tcg_gen_exit_tb((uintptr_t)s->base.tb + n); } else { gen_set_pc_im(s, dest); gen_goto_ptr(); } - s->is_jmp =3D DISAS_NORETURN; + s->base.is_jmp =3D DISAS_NORETURN; } =20 static inline void gen_jmp (DisasContext *s, uint32_t dest) @@ -4436,7 +4436,7 @@ static void gen_msr_banked(DisasContext *s, int r, in= t sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); tcg_temp_free_i32(tcg_reg); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } =20 static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) @@ -4458,7 +4458,7 @@ static void gen_mrs_banked(DisasContext *s, int r, in= t sysm, int rn) tcg_temp_free_i32(tcg_tgtmode); tcg_temp_free_i32(tcg_regno); store_reg(s, rn, tcg_reg); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } =20 /* Store value to PC as for an exception return (ie don't @@ -4482,7 +4482,7 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCG= v_i32 cpsr) gen_helper_cpsr_write_eret(cpu_env, cpsr); tcg_temp_free_i32(cpsr); /* Must exit loop to check un-masked IRQs */ - s->is_jmp =3D DISAS_EXIT; + s->base.is_jmp =3D DISAS_EXIT; } =20 /* Generate an old-style exception return. Marks pc as dead. */ @@ -4505,17 +4505,17 @@ static void gen_nop_hint(DisasContext *s, int val) case 1: /* yield */ if (!parallel_cpus) { gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_YIELD; + s->base.is_jmp =3D DISAS_YIELD; } break; case 3: /* wfi */ gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_WFI; + s->base.is_jmp =3D DISAS_WFI; break; case 2: /* wfe */ if (!parallel_cpus) { gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_WFE; + s->base.is_jmp =3D DISAS_WFE; } break; case 4: /* sev */ @@ -7654,13 +7654,13 @@ static int disas_coproc_insn(DisasContext *s, uint3= 2_t insn) return 1; } gen_set_pc_im(s, s->pc); - s->is_jmp =3D DISAS_WFI; + s->base.is_jmp =3D DISAS_WFI; return 0; default: break; } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)= ) { gen_io_start(); } =20 @@ -7751,7 +7751,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_= t insn) } } =20 - if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { + if ((s->base.tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)= ) { /* I/O operations must end the TB here (whether read or write)= */ gen_io_end(); gen_lookup_tb(s); @@ -8065,7 +8065,7 @@ static void gen_srs(DisasContext *s, tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) @@ -8153,7 +8153,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) /* setend */ if (((insn >> 9) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { gen_helper_setend(cpu_env); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } return; } else if ((insn & 0x0fffff00) =3D=3D 0x057ff000) { @@ -9527,7 +9527,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) gen_helper_cpsr_write_eret(cpu_env, tmp); tcg_temp_free_i32(tmp); /* Must exit loop to check un-masked IRQs */ - s->is_jmp =3D DISAS_EXIT; + s->base.is_jmp =3D DISAS_EXIT; } } break; @@ -9565,7 +9565,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) /* swi */ gen_set_pc_im(s, s->pc); s->svc_imm =3D extract32(insn, 0, 24); - s->is_jmp =3D DISAS_SWI; + s->base.is_jmp =3D DISAS_SWI; break; default: illegal_op: @@ -11627,7 +11627,7 @@ static void disas_thumb_insn(CPUARMState *env, Disa= sContext *s) ARCH(6); if (((insn >> 3) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { gen_helper_setend(cpu_env); - s->is_jmp =3D DISAS_UPDATE; + s->base.is_jmp =3D DISAS_UPDATE; } break; case 3: @@ -11721,7 +11721,7 @@ static void disas_thumb_insn(CPUARMState *env, Disa= sContext *s) /* swi */ gen_set_pc_im(s, s->pc); s->svc_imm =3D extract32(insn, 0, 8); - s->is_jmp =3D DISAS_SWI; + s->base.is_jmp =3D DISAS_SWI; break; } /* generate a conditional jump to next instruction */ @@ -11800,9 +11800,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D arm_env_get_cpu(env); DisasContext dc1, *dc =3D &dc1; - target_ulong pc_start; target_ulong next_page_start; - int num_insns; int max_insns; bool end_of_page; =20 @@ -11812,17 +11810,18 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. */ if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(cs, tb); + gen_intermediate_code_a64(&dc->base, cs, tb); return; } =20 - pc_start =3D tb->pc; + dc->base.tb =3D tb; + dc->base.pc_first =3D tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - dc->tb =3D tb; - - dc->is_jmp =3D DISAS_NEXT; - dc->pc =3D pc_start; - dc->singlestep_enabled =3D cs->singlestep_enabled; + dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; =20 dc->aarch64 =3D 0; @@ -11879,8 +11878,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) cpu_V1 =3D cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 =3D tcg_temp_new_i64(); - next_page_start =3D (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - num_insns =3D 0; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -11932,11 +11930,11 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) store_cpu_field(tmp, condexec_bits); } do { + dc->base.num_insns++; dc->insn_start_idx =3D tcg_op_buf_count(); tcg_gen_insn_start(dc->pc, (dc->condexec_cond << 4) | (dc->condexec_mask >= > 1), 0); - num_insns++; =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; @@ -11947,7 +11945,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_set_pc_im(dc, dc->pc); gen_helper_check_breakpoints(cpu_env); /* End the TB early; it's likely not going to be e= xecuted */ - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; } else { gen_exception_internal_insn(dc, 0, EXCP_DEBUG); /* The address covered by the breakpoint must be @@ -11965,7 +11963,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) } } =20 - if (num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) { + if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { gen_io_start(); } =20 @@ -11975,7 +11973,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) /* We always get here via a jump, so know we are not in a conditional execution block. */ gen_exception_internal(EXCP_KERNEL_TRAP); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; break; } #endif @@ -11991,10 +11989,11 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns =3D=3D 1); + assert(dc->base.num_insns =3D=3D 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - goto done_generating; + dc->base.is_jmp =3D DISAS_NORETURN; + break; } =20 if (dc->thumb) { @@ -12013,7 +12012,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) disas_arm_insn(dc, insn); } =20 - if (dc->condjmp && !dc->is_jmp) { + if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp =3D 0; } @@ -12040,11 +12039,11 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) end_of_page =3D (dc->pc >=3D next_page_start) || ((dc->pc >=3D next_page_start - 3) && insn_crosses_page(env, d= c)); =20 - } while (!dc->is_jmp && !tcg_op_buf_full() && + } while (!dc->base.is_jmp && !tcg_op_buf_full() && !is_singlestepping(dc) && !singlestep && !end_of_page && - num_insns < max_insns); + dc->base.num_insns < max_insns); =20 if (tb->cflags & CF_LAST_IO) { if (dc->condjmp) { @@ -12059,7 +12058,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) instruction was a conditional branch or trap, and the PC has already been written. */ gen_set_condexec(dc); - if (dc->is_jmp =3D=3D DISAS_BX_EXCRET) { + if (dc->base.is_jmp =3D=3D DISAS_BX_EXCRET) { /* Exception return branches need some special case code at the * end of the TB, which is complex enough that it has to * handle the single-step vs not and the condition-failed @@ -12068,7 +12067,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_bx_excret_final_code(dc); } else if (unlikely(is_singlestepping(dc))) { /* Unconditional and "condition passed" instruction codepath. */ - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_SWI: gen_ss_advance(dc); gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb), @@ -12102,7 +12101,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) - Hardware watchpoints. Hardware breakpoints have already been handled and skip this co= de. */ - switch(dc->is_jmp) { + switch(dc->base.is_jmp) { case DISAS_NEXT: gen_goto_tb(dc, 1, dc->pc); break; @@ -12158,22 +12157,22 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) } =20 done_generating: - gen_tb_end(tb, num_insns); + gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(pc_start)) { + qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start, + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, dc->thumb | (dc->sctlr_b << 1)); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size =3D dc->pc - pc_start; - tb->icount =3D num_insns; + tb->size =3D dc->pc - dc->base.pc_first; + tb->icount =3D dc->base.num_insns; } =20 static const char *cpu_mode_names[16] =3D { --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500929020599310.39104770755296; Mon, 24 Jul 2017 13:43:40 -0700 (PDT) Received: from localhost ([::1]:56886 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZkCY-0006vO-20 for importer@patchew.org; Mon, 24 Jul 2017 16:43:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47948) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjxs-0003Fk-79 for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjxq-0001Bx-97 for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:28 -0400 Received: from mail-qt0-x243.google.com ([2607:f8b0:400d:c0d::243]:33038) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjxq-0001BO-3J for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:26 -0400 Received: by mail-qt0-x243.google.com with SMTP id n42so3407513qtn.0 for ; Mon, 24 Jul 2017 13:28:26 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4Kj9Nj4g5Z2560nGbxoT4JQXWFcsl6NdnY7sqH+OV3U=; b=eLqatNzOsymZZ5dcgkEE3R23Yt5miiQ12zR9vsq22PMuamZqsg4K14I7u3nvLLh6MZ +oCadVN0vEAA16GZwbFffxDyK9AaK30uPpyy5jnhEn+4udbFKdGSfrnVEu1G1gJDBYG2 4eSpotQAUyxIGO92V+0YW+zB5i0K+PCRRt+P+kxPTqYAdlfb35b3yScjYCKQlVqKJ1NT IKMUYRMpc791PlD3w3aYYOz/A9gUcPVJbxAkh126g+9/j7vgG8vMLSd/DHpcOUcu3aOR OzSdhlzgvr2dqtgdp4TPEV5w5HmzWDfw4fv2BS4SIZwVK1U7uuRJDyfWbVuNddj/e1Tj YWCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4Kj9Nj4g5Z2560nGbxoT4JQXWFcsl6NdnY7sqH+OV3U=; b=kycwh0ibTi6yv8NK01eYjhgnNacrdWz1Y6oldAIoy9EMve4kx5+NhXWr4tY5EIrxdW Wxj0PkjrNq4/Rkaf8gIu+/SH/zlbDwrXVYTH4OoYx8mGvZE7HE1PQ6XXt9pvTQFly6ZM lahYZrFN8cyK+YhZ9xgaBcuYHZPmIrCGQLmpPQWkl9IAHwWbMjpVKoAfC/IvRso5gD1t pY6CQg1J3DLBijDrMgpkltwuocnVgtx7DdZqD2EFDFKwVEnJYGbo5Clxw/ElHJIcgfG9 QGMuNVLt7nN+fd/hZcTtnbTpYQgsaEwLG6CHqsV9GpEQV7aMc3kUP9vzULBLPpuGh5qI hKfA== X-Gm-Message-State: AIVw110WwA2IVtZd1MgMTxuPJJp71BUxabD2rsc/Pot8OSk4PitpfYwt tUx84kZDFNyJqc8TGlM= X-Received: by 10.237.48.226 with SMTP id 89mr589068qtf.201.1500928105294; Mon, 24 Jul 2017 13:28:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:12 -0700 Message-Id: <20170724202728.25960-17-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::243 Subject: [Qemu-devel] [PATCH v15 16/32] target/arm: [tcg] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002316201.22386.12115078843605656029.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 88 ++++++++++++++++++++++++++++------------------= ---- 1 file changed, 50 insertions(+), 38 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 55a2459a19..4e9e3c46b3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11794,32 +11794,12 @@ static bool insn_crosses_page(CPUARMState *env, D= isasContext *s) return false; } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static int arm_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs, int max_insns) { + DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D arm_env_get_cpu(env); - DisasContext dc1, *dc =3D &dc1; - target_ulong next_page_start; - int max_insns; - bool end_of_page; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; @@ -11830,23 +11810,23 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) */ dc->secure_routed_to_el3 =3D arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb =3D ARM_TBFLAG_THUMB(tb->flags); - dc->sctlr_b =3D ARM_TBFLAG_SCTLR_B(tb->flags); - dc->be_data =3D ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; - dc->condexec_mask =3D (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; - dc->condexec_cond =3D ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; - dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); + dc->thumb =3D ARM_TBFLAG_THUMB(dc->base.tb->flags); + dc->sctlr_b =3D ARM_TBFLAG_SCTLR_B(dc->base.tb->flags); + dc->be_data =3D ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; + dc->condexec_mask =3D (ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) & 0xf) = << 1; + dc->condexec_cond =3D ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) >> 4; + dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb= ->flags)); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->ns =3D ARM_TBFLAG_NS(tb->flags); - dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(tb->flags); - dc->vfp_enabled =3D ARM_TBFLAG_VFPEN(tb->flags); - dc->vec_len =3D ARM_TBFLAG_VECLEN(tb->flags); - dc->vec_stride =3D ARM_TBFLAG_VECSTRIDE(tb->flags); - dc->c15_cpar =3D ARM_TBFLAG_XSCALE_CPAR(tb->flags); - dc->v7m_handler_mode =3D ARM_TBFLAG_HANDLER(tb->flags); + dc->ns =3D ARM_TBFLAG_NS(dc->base.tb->flags); + dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); + dc->vfp_enabled =3D ARM_TBFLAG_VFPEN(dc->base.tb->flags); + dc->vec_len =3D ARM_TBFLAG_VECLEN(dc->base.tb->flags); + dc->vec_stride =3D ARM_TBFLAG_VECSTRIDE(dc->base.tb->flags); + dc->c15_cpar =3D ARM_TBFLAG_XSCALE_CPAR(dc->base.tb->flags); + dc->v7m_handler_mode =3D ARM_TBFLAG_HANDLER(dc->base.tb->flags); dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; =20 @@ -11865,11 +11845,12 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); + dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex =3D false; dc->ss_same_el =3D false; /* Can't be true since EL_d must be AArch64 = */ =20 + cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); cpu_F0d =3D tcg_temp_new_i64(); @@ -11878,6 +11859,36 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) cpu_V1 =3D cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 =3D tcg_temp_new_i64(); + + return max_insns; +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + CPUARMState *env =3D cs->env_ptr; + DisasContext dc1, *dc =3D &dc1; + target_ulong next_page_start; + int max_insns; + bool end_of_page; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cs, tb); + return; + } + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { @@ -11886,6 +11897,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); =20 gen_tb_start(tb); =20 --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500928708522940.1909624422041; Mon, 24 Jul 2017 13:38:28 -0700 (PDT) Received: from localhost ([::1]:56864 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZk7W-0002WA-0O for importer@patchew.org; Mon, 24 Jul 2017 16:38:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47959) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjxs-0003GW-R3 for qemu-devel@nongnu.org; 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Mon, 24 Jul 2017 13:28:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:13 -0700 Message-Id: <20170724202728.25960-18-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH v15 17/32] target/arm: [tcg, a64] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002340430.22386.10889954302345646107.stgit@frigg.lan> [rth: Adjust for max_insns interface change.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 38 ++++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7e2dee59ca..2919e5a636 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11179,21 +11179,12 @@ static void disas_a64_insn(CPUARMState *env, Disa= sContext *s) free_tmp_a64(s); } =20 -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) +static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu, int max_insns) { - CPUARMState *env =3D cs->env_ptr; - ARMCPU *cpu =3D arm_env_get_cpu(env); DisasContext *dc =3D container_of(dcbase, DisasContext, base); - target_ulong next_page_start; - int max_insns; - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; + CPUARMState *env =3D cpu->env_ptr; + ARMCPU *arm_cpu =3D arm_env_get_cpu(env); =20 dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; @@ -11219,7 +11210,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->vec_len =3D 0; dc->vec_stride =3D 0; - dc->cp_regs =3D cpu->cp_regs; + dc->cp_regs =3D arm_cpu->cp_regs; dc->features =3D env->features; =20 /* Single step state. The code-generation logic here is: @@ -11244,6 +11235,24 @@ void gen_intermediate_code_a64(DisasContextBase *d= cbase, CPUState *cs, =20 init_tmp_a64_array(dc); =20 + return max_insns; +} + +void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, + TranslationBlock *tb) +{ + CPUARMState *env =3D cs->env_ptr; + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + target_ulong next_page_start; + int max_insns; + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { @@ -11252,6 +11261,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + max_insns =3D aarch64_tr_init_disas_context(&dc->base, cs, max_insns); =20 gen_tb_start(tb); =20 --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500929169330158.22455274639367; Mon, 24 Jul 2017 13:46:09 -0700 (PDT) Received: from localhost ([::1]:56902 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZkEx-0000sx-EB for importer@patchew.org; Mon, 24 Jul 2017 16:46:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47974) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjxu-0003I7-Bf for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjxt-0001HF-2T for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:30 -0400 Received: from mail-qt0-x242.google.com ([2607:f8b0:400d:c0d::242]:38089) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjxs-0001GW-UM for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:29 -0400 Received: by mail-qt0-x242.google.com with SMTP id p3so2660250qtg.5 for ; Mon, 24 Jul 2017 13:28:28 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HNsH8uprwpWU8HLk/8041XnWXuiZW4bVZK15kEqh1fo=; b=m6AuZcWmQqApWXo+2wmvODBRGjyoqBEkql9tf0HC1HFYGlzwnUgss3tsqCrPU1RAPf w63qDTdYVggOMMqEyVw455Uk8XW+ih1MD2iY4xZHpPHSeg8at06q8M0WOHAdEBp/4KCz QiZF+FxsUUKF8zvxjJyfLV2FPDxl30pTx2PHD6XVYFLXy80hQEnfdGfT7TQX7hOVwKyt q+U+3nEk6Rc5OaQ5MkmYVWTIkQSmjK/NE/Hw5dEcYzBRLAQk5hDNFIZksiZA1LUDfOgC +gJCWioOMWwLuJ2rmL4zD7mCzXkOHwlK6I8qrV/HGwB/RxHbQ8n7N3TUFDmzzIeY5Pa7 cNrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HNsH8uprwpWU8HLk/8041XnWXuiZW4bVZK15kEqh1fo=; b=PdYk661zbmOhXraSr5Ud190FmnX0DXRUDtbSXMw/28R6p5N6xaAMjJ/tKqe+urXDbY rtQkYZj33V5lZhymqpBaOeem+9lyoAxdwyoeLF4YWFf4/v9gDS5Jkb+frlscFxFUyE1n OavwK9oVvMfIUfEhKW1RKSTyLOPYn+JqMKlX5G6HYhZPLxgMUMZ2P5EfQXyc7fzqGQn5 pR4OH6P+1mjqzMzLtRcG3dUYNf+2P/PnFH/oBbe0fSZR/nHR6kK2LHi62qNwCNBWJTl5 lNJ5mGPJSPYnHs8aRy6D/e9pdJJYSuCCecsB5XIMzChLsdrA4/LjNxCHEVieTRhHEXh8 1xWg== X-Gm-Message-State: AIVw110mJbbg/1H96597Oog1gi7Z+pr2E2ddXkuYjIk4sA7Flwl0hHcJ 2P1mHEA4HNeTdPCEhzE= X-Received: by 10.237.41.230 with SMTP id o93mr23656627qtd.27.1500928108049; Mon, 24 Jul 2017 13:28:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:14 -0700 Message-Id: <20170724202728.25960-19-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::242 Subject: [Qemu-devel] [PATCH v15 18/32] target/arm: [tcg] Port to tb_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002364681.22386.1701754996184325808.stgit@frigg.lan> [rth: Adjust for tb_start interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 82 +++++++++++++++++++++++++++-------------------= ---- 1 file changed, 44 insertions(+), 38 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4e9e3c46b3..5acdeabebb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11863,6 +11863,49 @@ static int arm_tr_init_disas_context(DisasContextB= ase *dcbase, return max_insns; } =20 +static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + /* A note on handling of the condexec (IT) bits: + * + * We want to avoid the overhead of having to write the updated condex= ec + * bits back to the CPUARMState for every instruction in an IT block. = So: + * (1) if the condexec bits are not already zero then we write + * zero back into the CPUARMState now. This avoids complications trying + * to do it at the end of the block. (For example if we don't do this + * it's hard to identify whether we can safely skip writing condexec + * at the end of the TB, which we definitely want to do for the case + * where a TB doesn't do anything with the IT state at all.) + * (2) if we are going to leave the TB then we call gen_set_condexec() + * which will write the correct value into CPUARMState if zero is wron= g. + * This is done both for leaving the TB at the end, and for leaving + * it because of an exception we know will happen, which is done in + * gen_exception_insn(). The latter is necessary because we need to + * leave the TB with the PC/IT state just prior to execution of the + * instruction which caused the exception. + * (3) if we leave the TB unexpectedly (eg a data abort on a load) + * then the CPUARMState will be wrong and we need to reset it. + * This is handled in the same way as restoration of the + * PC in these situations; we save the value of the condexec bits + * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() + * then uses this to restore them after an exception. + * + * Note that there are no instructions which can read the condexec + * bits, and none which can write non-static values to them, so + * we don't need to care about whether CPUARMState is correct in the + * middle of a TB. + */ + + /* Reset the conditional execution bits immediately. This avoids + complications trying to do it at the end of the block. */ + if (dc->condexec_mask || dc->condexec_cond) { + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(tmp, 0); + store_cpu_field(tmp, condexec_bits); + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11902,45 +11945,8 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) gen_tb_start(tb); =20 tcg_clear_temp_count(); + arm_tr_tb_start(&dc->base, cs); =20 - /* A note on handling of the condexec (IT) bits: - * - * We want to avoid the overhead of having to write the updated condex= ec - * bits back to the CPUARMState for every instruction in an IT block. = So: - * (1) if the condexec bits are not already zero then we write - * zero back into the CPUARMState now. This avoids complications trying - * to do it at the end of the block. (For example if we don't do this - * it's hard to identify whether we can safely skip writing condexec - * at the end of the TB, which we definitely want to do for the case - * where a TB doesn't do anything with the IT state at all.) - * (2) if we are going to leave the TB then we call gen_set_condexec() - * which will write the correct value into CPUARMState if zero is wron= g. - * This is done both for leaving the TB at the end, and for leaving - * it because of an exception we know will happen, which is done in - * gen_exception_insn(). The latter is necessary because we need to - * leave the TB with the PC/IT state just prior to execution of the - * instruction which caused the exception. - * (3) if we leave the TB unexpectedly (eg a data abort on a load) - * then the CPUARMState will be wrong and we need to reset it. - * This is handled in the same way as restoration of the - * PC in these situations; we save the value of the condexec bits - * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() - * then uses this to restore them after an exception. - * - * Note that there are no instructions which can read the condexec - * bits, and none which can write non-static values to them, so - * we don't need to care about whether CPUARMState is correct in the - * middle of a TB. - */ - - /* Reset the conditional execution bits immediately. This avoids - complications trying to do it at the end of the block. */ - if (dc->condexec_mask || dc->condexec_cond) - { - TCGv_i32 tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - store_cpu_field(tmp, condexec_bits); - } do { dc->base.num_insns++; dc->insn_start_idx =3D tcg_op_buf_count(); --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500928698372601.3273714535585; Mon, 24 Jul 2017 13:38:18 -0700 (PDT) Received: from localhost ([::1]:56862 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZk7M-0002Rd-Q6 for importer@patchew.org; Mon, 24 Jul 2017 16:38:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47990) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjxw-0003KJ-Bb for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjxv-0001MH-Fy for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:32 -0400 Received: from mail-qt0-x244.google.com ([2607:f8b0:400d:c0d::244]:38091) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjxv-0001Lg-C2 for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:31 -0400 Received: by mail-qt0-x244.google.com with SMTP id p3so2660309qtg.5 for ; Mon, 24 Jul 2017 13:28:31 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NKRSPCxm+bDmt6QDAXh6dqCMPqvxcRGkW2oIV5lHCpI=; b=lIs0NTvxpvO17g0RIlRYqXniqC/0voqaP/8WC7wZ5LdPLvPJ1TEoc+aGvAJ3zC+CTa tGpWIEJEru1tEEcAZsprJifzORrJqLOw7ZBuO2XzwqZjN5dfIs39p7UPfILEppZgB6UC P3qOl4r4iZVoSk7AjBNAHMAALNt2W9Sp8IpJKAAL+eex/nxP78zA/1EAt8YOxfLG5d+Z wQyNvczPbZC/y8RTxPCjppNkaNCkc+ktiH+efdQWGy2jFlou8dxMkGHlj06VAHLDKl23 WQQkGn6u2meTKhwGm3lUG6PiCEhYCiMm8qMe9dc2ZdlMk4PHCqcpRgHJdNwUjdhp8FHK 2JnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=NKRSPCxm+bDmt6QDAXh6dqCMPqvxcRGkW2oIV5lHCpI=; b=SnlpQtVwf8wsYb1ASh0ShVUUk5rvohzdWt4UHerdp1caff6e5t/dSGNiMeYkbJbeWa lRdnSLpqTRsFNFT8tLEUfnxbUlojY9GBAovY3Bc1NZhqb6trmDw7pdsvZk71rWLbJL6X 2PUjcTxJ7DQ5yjlITzS3KNEwhEdqWzbOQXBCXkjRtPHe2WU81buWmkCAKkrS7jLfCMNb R1BaWNwP0rTIkkntuCnzZo3ese559/jKRRsu8N1OKGidFP7Atg9SWwamiIKwO7GDJIbt PRb9CWil2a4aAj5fwtLfuK6igPBK/kDzUd71HtfqO4EUFUBr22URD5S5ndjnVZJUkFt/ K/Qw== X-Gm-Message-State: AIVw110yZv8ygyXUaVvWKxMkNqKkIltDDmjU685GMzLYV2eJF6gQdyKk Lf1wsO2774fP4YaIJ70= X-Received: by 10.200.46.118 with SMTP id s51mr21663229qta.48.1500928109527; Mon, 24 Jul 2017 13:28:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:15 -0700 Message-Id: <20170724202728.25960-20-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::244 Subject: [Qemu-devel] [PATCH v15 19/32] target/arm: [tcg] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002388959.22386.12439646324427589940.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5acdeabebb..c7010fffa5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11906,6 +11906,16 @@ static void arm_tr_tb_start(DisasContextBase *dcba= se, CPUState *cpu) } } =20 +static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + dc->insn_start_idx =3D tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), + 0); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11949,10 +11959,7 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) =20 do { dc->base.num_insns++; - dc->insn_start_idx =3D tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask >= > 1), - 0); + arm_tr_insn_start(&dc->base, cs); =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500928865268691.027272331175; Mon, 24 Jul 2017 13:41:05 -0700 (PDT) Received: from localhost ([::1]:56877 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZkA3-0004qx-BG for importer@patchew.org; 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Mon, 24 Jul 2017 13:28:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:16 -0700 Message-Id: <20170724202728.25960-21-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::242 Subject: [Qemu-devel] [PATCH v15 20/32] target/arm: [tcg, a64] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002413187.22386.156315485813606121.stgit@frigg.lan> [rth: Use DISAS_TOO_MANY for "execute only one more" after bp.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 11 ++++++++-- target/arm/translate.c | 55 +++++++++++++++++++++++++++++-------------= ---- 2 files changed, 44 insertions(+), 22 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2919e5a636..2edcfe05f3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11238,6 +11238,14 @@ static int aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, return max_insns; } =20 +static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + dc->insn_start_idx =3D tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, 0, 0); +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11269,8 +11277,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, =20 do { dc->base.num_insns++; - dc->insn_start_idx =3D tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, 0, 0); + aarch64_tr_insn_start(&dc->base, cs); =20 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; diff --git a/target/arm/translate.c b/target/arm/translate.c index c7010fffa5..30db22fa79 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11916,6 +11916,33 @@ static void arm_tr_insn_start(DisasContextBase *dc= base, CPUState *cpu) 0); } =20 +static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cp= u, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_set_condexec(dc); + gen_set_pc_im(dc, dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it's likely not going to be executed */ + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + /* TODO: Advance PC by correct instruction length to + * avoid disassembler error messages */ + dc->pc +=3D 2; + dc->base.is_jmp =3D DISAS_NORETURN; + } + + return true; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11964,28 +11991,15 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->pc) { - if (bp->flags & BP_CPU) { - gen_set_condexec(dc); - gen_set_pc_im(dc, dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it's likely not going to be e= xecuted */ - dc->base.is_jmp =3D DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length = to - * avoid disassembler error messages */ - dc->pc +=3D 2; - goto done_generating; + if (bp->pc =3D=3D dc->base.pc_next) { + if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { + break; } - break; } } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } } =20 if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { @@ -12107,6 +12121,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) gen_exception(EXCP_SMC, syn_aa32_smc(), 3); break; case DISAS_NEXT: + case DISAS_TOO_MANY: case DISAS_UPDATE: gen_set_pc_im(dc, dc->pc); /* fall through */ @@ -12128,6 +12143,7 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) */ switch(dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; case DISAS_JUMP: @@ -12181,7 +12197,6 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) } } =20 -done_generating: gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400d:c0d::243 Subject: [Qemu-devel] [PATCH v15 21/32] target/arm: [tcg, a64] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002461630.22386.14827196109258040543.stgit@frigg.lan> [rth: Use DISAS_TOO_MANY for "execute only one more" after bp.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++------------= ---- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2edcfe05f3..4cb8c66b8d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11246,6 +11246,30 @@ static void aarch64_tr_insn_start(DisasContextBase= *dcbase, CPUState *cpu) tcg_gen_insn_start(dc->pc, 0, 0); } =20 +static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_a64_set_pc_im(dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it likely won't be executed */ + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + dc->pc +=3D 4; + dc->base.is_jmp =3D DISAS_NORETURN; + } + + return true; +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11282,25 +11306,15 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->pc) { - if (bp->flags & BP_CPU) { - gen_a64_set_pc_im(dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it likely won't be executed */ - dc->base.is_jmp =3D DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [dc->base.tb->pc, dc->base.tb->pc += dc->base.tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - dc->base.tb->size below does the right thing. = */ - dc->pc +=3D 4; - goto done_generating; + if (bp->pc =3D=3D dc->base.pc_next) { + if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) { + break; } - break; } } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } } =20 if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { @@ -11371,6 +11385,7 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, } else { switch (dc->base.is_jmp) { case DISAS_NEXT: + case DISAS_TOO_MANY: gen_goto_tb(dc, 1, dc->pc); break; case DISAS_JUMP: @@ -11408,7 +11423,6 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, } } =20 -done_generating: gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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X-Received-From: 2607:f8b0:400d:c0d::243 Subject: [Qemu-devel] [PATCH v15 22/32] target/arm: [tcg] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002485863.22386.13949856269576226529.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.h | 1 + target/arm/translate.c | 165 +++++++++++++++++++++++++++------------------= ---- 2 files changed, 91 insertions(+), 75 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index a804ff65ac..e8dcec51ac 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -9,6 +9,7 @@ typedef struct DisasContext { DisasContextBase base; =20 target_ulong pc; + target_ulong next_page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; diff --git a/target/arm/translate.c b/target/arm/translate.c index 30db22fa79..0b4cb1e463 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11850,6 +11850,8 @@ static int arm_tr_init_disas_context(DisasContextBa= se *dcbase, dc->is_ldex =3D false; dc->ss_same_el =3D false; /* Can't be true since EL_d must be AArch64 = */ =20 + dc->next_page_start =3D + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; =20 cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); @@ -11943,14 +11945,93 @@ static bool arm_tr_breakpoint_check(DisasContextB= ase *dcbase, CPUState *cpu, return true; } =20 +static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >=3D 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->base.is_jmp =3D DISAS_NORETURN; + return; + } +#endif + + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns =3D=3D 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp =3D DISAS_NORETURN; + return; + } + + if (dc->thumb) { + disas_thumb_insn(env, dc); + if (dc->condexec_mask) { + dc->condexec_cond =3D (dc->condexec_cond & 0xe) + | ((dc->condexec_mask >> 4) & 1); + dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; + if (dc->condexec_mask =3D=3D 0) { + dc->condexec_cond =3D 0; + } + } + } else { + unsigned int insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->pc +=3D 4; + disas_arm_insn(dc, insn); + } + + if (dc->condjmp && !dc->base.is_jmp) { + gen_set_label(dc->condlabel); + dc->condjmp =3D 0; + } + + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { + /* Translation stops when a conditional branch is encountered. + * Otherwise the subsequent code could get translated several time= s. + * Also stop translation when a page boundary is reached. This + * ensures prefetch aborts occur at the right place. */ + + if (is_singlestepping(dc)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } else if ((dc->pc >=3D dc->next_page_start) || + ((dc->pc >=3D dc->next_page_start - 3) && + insn_crosses_page(env, dc))) { + /* We want to stop the TB if the next insn starts in a new pag= e, + * or if it spans between this page and the next. This means t= hat + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit= insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } + + dc->base.pc_next =3D dc->pc; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { - CPUARMState *env =3D cs->env_ptr; DisasContext dc1, *dc =3D &dc1; - target_ulong next_page_start; int max_insns; - bool end_of_page; =20 /* generate intermediate code */ =20 @@ -11969,7 +12050,6 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) dc->base.num_insns =3D 0; dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -12006,83 +12086,18 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) gen_io_start(); } =20 -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >=3D 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - } -#endif - - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debug= ged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(dc->base.num_insns =3D=3D 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - } - - if (dc->thumb) { - disas_thumb_insn(env, dc); - if (dc->condexec_mask) { - dc->condexec_cond =3D (dc->condexec_cond & 0xe) - | ((dc->condexec_mask >> 4) & 1); - dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; - if (dc->condexec_mask =3D=3D 0) { - dc->condexec_cond =3D 0; - } - } - } else { - unsigned int insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); - dc->pc +=3D 4; - disas_arm_insn(dc, insn); - } - - if (dc->condjmp && !dc->base.is_jmp) { - gen_set_label(dc->condlabel); - dc->condjmp =3D 0; - } + arm_tr_translate_insn(&dc->base, cs); =20 if (tcg_check_temp_count()) { fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", dc->pc); } =20 - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several time= s. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. */ - - /* We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - end_of_page =3D (dc->pc >=3D next_page_start) || - ((dc->pc >=3D next_page_start - 3) && insn_crosses_page(env, d= c)); - - } while (!dc->base.is_jmp && !tcg_op_buf_full() && - !is_singlestepping(dc) && - !singlestep && - !end_of_page && - dc->base.num_insns < max_insns); + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >=3D max_insns)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); =20 if (tb->cflags & CF_LAST_IO) { if (dc->condjmp) { --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500929481123271.16561943305453; Mon, 24 Jul 2017 13:51:21 -0700 (PDT) Received: from localhost ([::1]:56940 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZkJy-0005Lc-0N for importer@patchew.org; Mon, 24 Jul 2017 16:51:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48034) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjy3-0003aR-Ey for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjy0-0001WU-FY for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:39 -0400 Received: from mail-qk0-x241.google.com ([2607:f8b0:400d:c09::241]:34996) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjy0-0001Vl-AH for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:36 -0400 Received: by mail-qk0-x241.google.com with SMTP id k2so3510394qkf.2 for ; Mon, 24 Jul 2017 13:28:36 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cOTQxuYJOG9pEjAzXNWs54LnOVtDPwTJmHtta5EPpo0=; b=Z1S0B8sjwBefbHMEpqODCTtw/oiHjyjLyQJ1Nz2rg8lsb6sB+g3pjbIAWfMkkknAU6 Lxo/pbkc/3JcWl0yeCqu4xrtaf6vC8K1SYXg8UesCv/zkuh4zcprRvSFqoiUuYTPEMjC BT1k753MDvoxHyb06Zrgd5vbZPTu+qO4RlkdcB+TjMwElM3kwGe6U5B1fzl5mPlUfWhl 8E9dnMSneS/BtxzGMMuSGnl6d6w733RPxPH5kQG5AKPDLBO+A5lRSt1fscYtOFE23Knp 4ZilF3sMhOVQxRWTnkljX2Ca7vzYPmUo5OE97jlEWieFAg/mv1BaOAv8maQa1XbFvzh+ yShw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cOTQxuYJOG9pEjAzXNWs54LnOVtDPwTJmHtta5EPpo0=; b=LxnA+QOw2d6RIEEg7xEha72EkvKWslHRoEATK2s0IfeTw891EzcIpBowrpuKnbVgVV t5Cx99z6Jd9n4KQpcEk37UsvqW3WTQxwj2owEWQgrlbDMjT47hKLZaAp93Ssj9RrCond Nlxqg224dj3iCddIT3+vjETU+0wyzs+OqimAL0LwKhWRrDqHipvKija5sD1zrkrG0yTO 1YUezqS0ru6cTw8wso/O19Z7fqtD5MEzaPBxVwhiibot4kNJB98Xh14QOLxOnMjbtBD3 lT6YOWSuf7mbZq6bzA0fypZZDO8S/6d356RRIcpTll4oZFIK3nBY4Vo5lGsUrgBnyv/8 qphw== X-Gm-Message-State: AIVw113wLWeaVK0T1RpOIYSgifMZ/UcXAsLlscC5eFqNYQ/AVDBie2S6 Dz+NCknrYQapEC85MOs= X-Received: by 10.55.8.139 with SMTP id 133mr21450221qki.22.1500928115400; Mon, 24 Jul 2017 13:28:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:19 -0700 Message-Id: <20170724202728.25960-24-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::241 Subject: [Qemu-devel] [PATCH v15 23/32] target/arm: [tcg, a64] Port to translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002510079.22386.10164419868911710218.stgit@frigg.lan> [rth: Adjust for translate_insn interface change.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++++--------------= ---- 1 file changed, 43 insertions(+), 28 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4cb8c66b8d..c1684b80c4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11233,6 +11233,9 @@ static int aarch64_tr_init_disas_context(DisasConte= xtBase *dcbase, dc->is_ldex =3D false; dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 + dc->next_page_start =3D + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + init_tmp_a64_array(dc); =20 return max_insns; @@ -11270,12 +11273,43 @@ static bool aarch64_tr_breakpoint_check(DisasCont= extBase *dcbase, CPUState *cpu, return true; } =20 +static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + + if (dc->ss_active && !dc->pstate_ss) { + /* Singlestep state is Active-pending. + * If we're in this state at the start of a TB then either + * a) we just took an exception to an EL which is being debugged + * and this is the first insn in the exception handler + * b) debug exceptions were masked and we just unmasked them + * without changing EL (eg by clearing PSTATE.D) + * In either case we're going to take a swstep exception in the + * "did not step an insn" case, and so the syndrome ISV and EX + * bits should be zero. + */ + assert(dc->base.num_insns =3D=3D 1); + gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), + default_exception_el(dc)); + dc->base.is_jmp =3D DISAS_NORETURN; + } else { + disas_a64_insn(env, dc); + } + + if (dc->base.is_jmp =3D=3D DISAS_NEXT) { + if (dc->ss_active || dc->pc >=3D dc->next_page_start) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } + + dc->base.pc_next =3D dc->pc; +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { - CPUARMState *env =3D cs->env_ptr; DisasContext *dc =3D container_of(dcbase, DisasContext, base); - target_ulong next_page_start; int max_insns; =20 dc->base.tb =3D tb; @@ -11285,7 +11319,6 @@ void gen_intermediate_code_a64(DisasContextBase *dc= base, CPUState *cs, dc->base.num_insns =3D 0; dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 - next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { max_insns =3D CF_COUNT_MASK; @@ -11321,42 +11354,24 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, gen_io_start(); } =20 - if (dc->ss_active && !dc->pstate_ss) { - /* Singlestep state is Active-pending. - * If we're in this state at the start of a TB then either - * a) we just took an exception to an EL which is being debug= ged - * and this is the first insn in the exception handler - * b) debug exceptions were masked and we just unmasked them - * without changing EL (eg by clearing PSTATE.D) - * In either case we're going to take a swstep exception in the - * "did not step an insn" case, and so the syndrome ISV and EX - * bits should be zero. - */ - assert(dc->base.num_insns =3D=3D 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); - dc->base.is_jmp =3D DISAS_NORETURN; - break; - } - - disas_a64_insn(env, dc); + aarch64_tr_translate_insn(&dc->base, cs); =20 if (tcg_check_temp_count()) { fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", dc->pc); } =20 + if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabl= ed || + singlestep || dc->base.num_insns >=3D max_insn= s)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + /* Translation stops when a conditional branch is encountered. * Otherwise the subsequent code could get translated several time= s. * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - } while (!dc->base.is_jmp && !tcg_op_buf_full() && - !cs->singlestep_enabled && - !singlestep && - !dc->ss_active && - dc->pc < next_page_start && - dc->base.num_insns < max_insns); + } while (!dc->base.is_jmp); =20 if (dc->base.tb->cflags & CF_LAST_IO) { gen_io_end(); --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500929089912761.683500290501; Mon, 24 Jul 2017 13:44:49 -0700 (PDT) Received: from localhost ([::1]:56891 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZkDg-000827-Cg for importer@patchew.org; Mon, 24 Jul 2017 16:44:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48035) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjy3-0003aS-FC for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjy1-0001ZG-Qz for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:39 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:33458) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjy1-0001Yb-LS for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:37 -0400 Received: by mail-qk0-x244.google.com with SMTP id d145so8411191qkc.0 for ; Mon, 24 Jul 2017 13:28:37 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HFc9+x9yMJuoLkssT25OglTsJe7tkSG6TnkXKcH7kYY=; b=ueH+jVomCUx/BcuLoAP5Q9ZfWv1VMBYIFkgNqRVOfLHLTJFAVw1mMgw1gGW9wB2yef jwqqJNrNBcC+3T6FcuVHe/3soIy5FHl+JrQBy64ovt3IwirsD/W4HbY0lHeXHTO2rl7T y3xM/q27orrWUXPkPRGLx2IVAT7GQ4P3snWaFOmTz7qlJsxktm4toF6jguHSNSbVtcK3 IkwXcNOIezZVM4vN4Ff0Mzomc+S/yyXoNTWJCMAx7ltBDMht8662oN81Njn/XHi2nsjA YPrAjsHD3iWXftMxlzS474vMJ5Jm3SP7J0yZWRhGTFt64fRlne8IaLy4w0l4wrwfxqjd RDyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HFc9+x9yMJuoLkssT25OglTsJe7tkSG6TnkXKcH7kYY=; b=p0Hxw3hvM2z/SPqsbUku3zdgdRKS+u+gSgDA6McUxitolv459Jzq07zZ954Sh4mZhE MTodaYTpuDRAXs6xrjMVOrpdfWOIiZErDP+aDUbsINc/Cs3niVk+/3lVhBm/enL1RpU4 nIS9JIAPwLNFGkJ/1XY3H2odlzHBp6ryzyqYvkqDBwe+EM57jCJdtV67dRTlYm4g2TsI i4VlZiwl9b7iJSKsVPBeMTGTu6JqlzMLpv5PJi3anQiHEVWQ/DOoQTxu7oZCqGGI7YjR 9+QDNs2txnPuMz1wTx4uc7SvN/jHotLkgrej4nqz+5AbTTc1FMwFUJBpLm5gvEtbbc6G HqoQ== X-Gm-Message-State: AIVw110+yDEBgoilDMdlvu4LmvfKbEmEdcGhn6fGsFQPD5ymANp1/A+Y C5lt5/LSodZral5zaIA= X-Received: by 10.55.97.13 with SMTP id v13mr22371824qkb.107.1500928116797; Mon, 24 Jul 2017 13:28:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:20 -0700 Message-Id: <20170724202728.25960-25-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH v15 24/32] target/arm: [tcg] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002534291.22386.13499916738708680298.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.c | 161 ++++++++++++++++++++++++++-------------------= ---- 1 file changed, 84 insertions(+), 77 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0b4cb1e463..bacc0303e5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12027,85 +12027,13 @@ static void arm_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) dc->base.pc_next =3D dc->pc; } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { - DisasContext dc1, *dc =3D &dc1; - int max_insns; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_tr_tb_start(&dc->base, cs); - - do { - dc->base.num_insns++; - arm_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { - gen_io_start(); - } - - arm_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >=3D max_insns)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - if (tb->cflags & CF_LAST_IO) { - if (dc->condjmp) { - /* FIXME: This can theoretically happen with self-modifying - code. */ - cpu_abort(cs, "IO on conditional branch instruction"); - } - gen_io_end(); + if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) { + /* FIXME: This can theoretically happen with self-modifying code. = */ + cpu_abort(cpu, "IO on conditional branch instruction"); } =20 /* At this stage dc->condjmp will only be set when the skipped @@ -12211,6 +12139,85 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) gen_goto_tb(dc, 1, dc->pc); } } +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext dc1, *dc =3D &dc1; + int max_insns; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cs, tb); + return; + } + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + + max_insns =3D tb->cflags & CF_COUNT_MASK; + if (max_insns =3D=3D 0) { + max_insns =3D CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns =3D TCG_MAX_INSNS; + } + max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); + + gen_tb_start(tb); + + tcg_clear_temp_count(); + arm_tr_tb_start(&dc->base, cs); + + do { + dc->base.num_insns++; + arm_tr_insn_start(&dc->base, cs); + + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc =3D=3D dc->base.pc_next) { + if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { + break; + } + } + } + if (dc->base.is_jmp > DISAS_TOO_MANY) { + break; + } + } + + if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { + gen_io_start(); + } + + arm_tr_translate_insn(&dc->base, cs); + + if (tcg_check_temp_count()) { + fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", + dc->pc); + } + + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >=3D max_insns)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); + + if (dc->base.tb->cflags & CF_LAST_IO) { + gen_io_end(); + } + + arm_tr_tb_stop(&dc->base, cs); =20 gen_tb_end(tb, dc->base.num_insns); =20 --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400d:c0d::242 Subject: [Qemu-devel] [PATCH v15 25/32] target/arm: [tcg, a64] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002558503.22386.1149037590886263349.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 127 ++++++++++++++++++++++++-----------------= ---- 1 file changed, 67 insertions(+), 60 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c1684b80c4..4056d38c02 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11306,6 +11306,72 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) dc->base.pc_next =3D dc->pc; } =20 +static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) { + /* Note that this means single stepping WFI doesn't halt the CPU. + * For conditional branch insns this is harmless unreachable code = as + * gen_goto_tb() has already handled emitting the debug exception + * (and thus a tb-jump is not possible when singlestepping). + */ + switch (dc->base.is_jmp) { + default: + gen_a64_set_pc_im(dc->pc); + /* fall through */ + case DISAS_JUMP: + if (dc->base.singlestep_enabled) { + gen_exception_internal(EXCP_DEBUG); + } else { + gen_step_complete_exception(dc); + } + break; + case DISAS_NORETURN: + break; + } + } else { + switch (dc->base.is_jmp) { + case DISAS_NEXT: + case DISAS_TOO_MANY: + gen_goto_tb(dc, 1, dc->pc); + break; + default: + case DISAS_UPDATE: + gen_a64_set_pc_im(dc->pc); + /* fall through */ + case DISAS_JUMP: + tcg_gen_lookup_and_goto_ptr(cpu_pc); + break; + case DISAS_EXIT: + tcg_gen_exit_tb(0); + break; + case DISAS_NORETURN: + case DISAS_SWI: + break; + case DISAS_WFE: + gen_a64_set_pc_im(dc->pc); + gen_helper_wfe(cpu_env); + break; + case DISAS_YIELD: + gen_a64_set_pc_im(dc->pc); + gen_helper_yield(cpu_env); + break; + case DISAS_WFI: + /* This is a special case because we don't want to just halt t= he CPU + * if trying to debug across a WFI. + */ + gen_a64_set_pc_im(dc->pc); + gen_helper_wfi(cpu_env); + /* The helper doesn't necessarily throw an exception, but we + * must go back to the main loop to check for interrupts anywa= y. + */ + tcg_gen_exit_tb(0); + break; + } + } +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11377,66 +11443,7 @@ void gen_intermediate_code_a64(DisasContextBase *d= cbase, CPUState *cs, gen_io_end(); } =20 - if (unlikely(cs->singlestep_enabled || dc->ss_active)) { - /* Note that this means single stepping WFI doesn't halt the CPU. - * For conditional branch insns this is harmless unreachable code = as - * gen_goto_tb() has already handled emitting the debug exception - * (and thus a tb-jump is not possible when singlestepping). - */ - switch (dc->base.is_jmp) { - default: - gen_a64_set_pc_im(dc->pc); - /* fall through */ - case DISAS_JUMP: - if (cs->singlestep_enabled) { - gen_exception_internal(EXCP_DEBUG); - } else { - gen_step_complete_exception(dc); - } - break; - case DISAS_NORETURN: - break; - } - } else { - switch (dc->base.is_jmp) { - case DISAS_NEXT: - case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->pc); - break; - case DISAS_JUMP: - tcg_gen_lookup_and_goto_ptr(cpu_pc); - break; - case DISAS_NORETURN: - case DISAS_SWI: - break; - case DISAS_WFE: - gen_a64_set_pc_im(dc->pc); - gen_helper_wfe(cpu_env); - break; - case DISAS_YIELD: - gen_a64_set_pc_im(dc->pc); - gen_helper_yield(cpu_env); - break; - case DISAS_WFI: - /* This is a special case because we don't want to just halt t= he CPU - * if trying to debug across a WFI. - */ - gen_a64_set_pc_im(dc->pc); - gen_helper_wfi(cpu_env); - /* The helper doesn't necessarily throw an exception, but we - * must go back to the main loop to check for interrupts anywa= y. - */ - tcg_gen_exit_tb(0); - break; - case DISAS_UPDATE: - gen_a64_set_pc_im(dc->pc); - /* fall through */ - case DISAS_EXIT: - default: - tcg_gen_exit_tb(0); - break; - } - } + aarch64_tr_tb_stop(&dc->base, cs); =20 gen_tb_end(tb, dc->base.num_insns); =20 --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:400d:c09::241 Subject: [Qemu-devel] [PATCH v15 26/32] target/arm: [tcg] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benne=C3=A9 Message-Id: <150002582711.22386.191527630537864599.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index bacc0303e5..c5e6ee8468 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12141,6 +12141,15 @@ static void arm_tr_tb_stop(DisasContextBase *dcbas= e, CPUState *cpu) } } =20 +static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, + dc->thumb | (dc->sctlr_b << 1)); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -12221,20 +12230,19 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) =20 gen_tb_end(tb, dc->base.num_insns); =20 + tb->size =3D dc->pc - dc->base.pc_first; + tb->icount =3D dc->base.num_insns; + #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); - log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, - dc->thumb | (dc->sctlr_b << 1)); + arm_tr_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size =3D dc->pc - dc->base.pc_first; - tb->icount =3D dc->base.num_insns; } =20 static const char *cpu_mode_names[16] =3D { --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500929019462556.2044405836173; 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Mon, 24 Jul 2017 13:28:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:23 -0700 Message-Id: <20170724202728.25960-28-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-devel] [PATCH v15 27/32] target/arm: [tcg, a64] Port to disas_log X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Incrementally paves the way towards using the generic instruction translati= on loop. Reviewed-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002606914.22386.15524101311003685068.stgit@frigg.lan> [rth: Move tb->size computation and use that result.] Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4056d38c02..9339e54f0c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11372,6 +11372,16 @@ static void aarch64_tr_tb_stop(DisasContextBase *d= cbase, CPUState *cpu) } } =20 +static void aarch64_tr_disas_log(const DisasContextBase *dcbase, + CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, + 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); +} + void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, TranslationBlock *tb) { @@ -11447,18 +11457,17 @@ void gen_intermediate_code_a64(DisasContextBase *= dcbase, CPUState *cs, =20 gen_tb_end(tb, dc->base.num_insns); =20 + dc->base.tb->size =3D dc->pc - dc->base.pc_first; + dc->base.tb->icount =3D dc->base.num_insns; + #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(dc->base.pc_first)) { qemu_log_lock(); qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); - log_target_disas(cs, dc->base.pc_first, dc->pc - dc->base.pc_first, - 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); + aarch64_tr_disas_log(&dc->base, cs); qemu_log("\n"); qemu_log_unlock(); } #endif - dc->base.tb->size =3D dc->pc - dc->base.pc_first; - dc->base.tb->icount =3D dc->base.num_insns; } --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500929809356668.502756902448; Mon, 24 Jul 2017 13:56:49 -0700 (PDT) Received: from localhost ([::1]:56981 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZkPG-00012C-TM for importer@patchew.org; Mon, 24 Jul 2017 16:56:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48113) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjyF-0003mF-L1 for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjyD-0001tE-Uf for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:51 -0400 Received: from mail-qt0-x243.google.com ([2607:f8b0:400d:c0d::243]:36543) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjyD-0001sr-Os for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:49 -0400 Received: by mail-qt0-x243.google.com with SMTP id l55so13169755qtl.3 for ; Mon, 24 Jul 2017 13:28:49 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fogkGWpQdIXCZ9wxr/5CtsaI4TcbZdDX67TXU4ATy9E=; b=JZMeKyaQ7yc+hRXcuS+3yJbGtoBPb44WkDQcYuZoUNab/yN8oRgIT5Zly+fsX9u7lQ H1ylEc3cMlrXp1VGA50T9bglD2KrDwpPYFvLPHVaszJ/ARAc0rnDeQ9pcE8396PLoESp YZoSmWoqgFLylsBiewvUtcfuNcSGLDthwKRyL4bIFji0WEKmfZYWI/N6hitQUUtmXczi 82XK0GuhkziwLW6/Jqj9FedMpKE1V47DF/gtq7gRYNZiX+qn1NktCinozreswy6oyn5v qG98HenWPW2mmQ3zru7euOlXXQMf7y9vkGgVz7eVdifFm1t1fp7yFQptB60kJRTBiVUX K2eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=fogkGWpQdIXCZ9wxr/5CtsaI4TcbZdDX67TXU4ATy9E=; b=fmLP2CmWAYO+DCqfoto4Hb3vRINEM57G3Ia34649FM05MvNnCdwLhrAGwfaSXd9fTm xoxaveMBBm2H9Tqc7IHHXX+iXa65TAvDXVJOGo3ZtkGYSdedax0mGh5E4Rz1eWui+uAq yxSr1IG3fyHPO3QnLhzfMMtfthZXzG56BbvJuhK+Rwyz+5Zyd5kzbSAoV9rU2yJE0o+8 NIZPciLqe1Uw1Qk8V6ysUGoMNafhlmYTpbq9pbdM/4TdJKLYtvqFaHIKWFLbu5GP2V7B uKys8Z1iFXNlurzTtGQtqKP8vGGXOHe1v0flZ7dg6zscR9j1kRDmHgdEc2X/45aS55Sz d9KQ== X-Gm-Message-State: AIVw112qfdO8dhheZKLI8/OqB05eLrbC4UYRxx+0A7KHBp0uWT6khMWe vCn5Gh24rcgmDJ4Jbi8= X-Received: by 10.200.39.100 with SMTP id h33mr23304932qth.62.1500928128794; Mon, 24 Jul 2017 13:28:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:24 -0700 Message-Id: <20170724202728.25960-29-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::243 Subject: [Qemu-devel] [PATCH v15 28/32] target/arm: [tcg] Port to generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Llu=C3=ADs Vilanova Signed-off-by: Llu=C3=ADs Vilanova Message-Id: <150002631325.22386.10348327185029496649.stgit@frigg.lan> Signed-off-by: Richard Henderson Reviewed-by: Emilio G. Cota Tested-by: Emilio G. Cota --- target/arm/translate.h | 8 +--- target/arm/translate-a64.c | 107 ++++++++---------------------------------= --- target/arm/translate.c | 109 +++++++++--------------------------------= ---- 3 files changed, 41 insertions(+), 183 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index e8dcec51ac..55d691db40 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -150,21 +150,15 @@ static void disas_set_insn_syndrome(DisasContext *s, = uint32_t syn) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, - TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); +extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } =20 -static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUStat= e *cpu, - TranslationBlock *tb) -{ -} - static inline void gen_a64_set_pc_im(uint64_t val) { } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9339e54f0c..9093b8ac17 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11241,6 +11241,11 @@ static int aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, return max_insns; } =20 +static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ + tcg_clear_temp_count(); +} + static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -11304,6 +11309,7 @@ static void aarch64_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu) } =20 dc->base.pc_next =3D dc->pc; + translator_loop_temp_check(&dc->base); } =20 static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) @@ -11370,6 +11376,9 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) break; } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next =3D dc->pc; } =20 static void aarch64_tr_disas_log(const DisasContextBase *dcbase, @@ -11382,92 +11391,12 @@ static void aarch64_tr_disas_log(const DisasConte= xtBase *dcbase, 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); } =20 -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - int max_insns; - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - - max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - max_insns =3D aarch64_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - - do { - dc->base.num_insns++; - aarch64_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { - gen_io_start(); - } - - aarch64_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabl= ed || - singlestep || dc->base.num_insns >=3D max_insn= s)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several time= s. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. - */ - } while (!dc->base.is_jmp); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - - aarch64_tr_tb_stop(&dc->base, cs); - - gen_tb_end(tb, dc->base.num_insns); - - dc->base.tb->size =3D dc->pc - dc->base.pc_first; - dc->base.tb->icount =3D dc->base.num_insns; - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - aarch64_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif -} +const TranslatorOps aarch64_translator_ops =3D { + .init_disas_context =3D aarch64_tr_init_disas_context, + .tb_start =3D aarch64_tr_tb_start, + .insn_start =3D aarch64_tr_insn_start, + .breakpoint_check =3D aarch64_tr_breakpoint_check, + .translate_insn =3D aarch64_tr_translate_insn, + .tb_stop =3D aarch64_tr_tb_stop, + .disas_log =3D aarch64_tr_disas_log, +}; diff --git a/target/arm/translate.c b/target/arm/translate.c index c5e6ee8468..5991422695 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11906,6 +11906,7 @@ static void arm_tr_tb_start(DisasContextBase *dcbas= e, CPUState *cpu) tcg_gen_movi_i32(tmp, 0); store_cpu_field(tmp, condexec_bits); } + tcg_clear_temp_count(); } =20 static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) @@ -12025,6 +12026,7 @@ static void arm_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) } =20 dc->base.pc_next =3D dc->pc; + translator_loop_temp_check(&dc->base); } =20 static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) @@ -12139,6 +12141,9 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) gen_goto_tb(dc, 1, dc->pc); } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next =3D dc->pc; } =20 static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) @@ -12150,99 +12155,29 @@ static void arm_tr_disas_log(const DisasContextBa= se *dcbase, CPUState *cpu) dc->thumb | (dc->sctlr_b << 1)); } =20 +static const TranslatorOps arm_translator_ops =3D { + .init_disas_context =3D arm_tr_init_disas_context, + .tb_start =3D arm_tr_tb_start, + .insn_start =3D arm_tr_insn_start, + .breakpoint_check =3D arm_tr_breakpoint_check, + .translate_insn =3D arm_tr_translate_insn, + .tb_stop =3D arm_tr_tb_stop, + .disas_log =3D arm_tr_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - DisasContext dc1, *dc =3D &dc1; - int max_insns; - - /* generate intermediate code */ + DisasContext dc; + const TranslatorOps *ops =3D &arm_translator_ops; =20 - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ +#ifdef TARGET_AARCH64 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - max_insns =3D arm_tr_init_disas_context(&dc->base, cs, max_insns); - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_tr_tb_start(&dc->base, cs); - - do { - dc->base.num_insns++; - arm_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - if (dc->base.is_jmp > DISAS_TOO_MANY) { - break; - } - } - - if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { - gen_io_start(); - } - - arm_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >=3D max_insns)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - - arm_tr_tb_stop(&dc->base, cs); - - gen_tb_end(tb, dc->base.num_insns); - - tb->size =3D dc->pc - dc->base.pc_first; - tb->icount =3D dc->base.num_insns; - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - arm_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); + ops =3D &aarch64_translator_ops; } #endif + + translator_loop(ops, &dc.base, cpu, tb); } =20 static const char *cpu_mode_names[16] =3D { --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500929324881645.2423763781628; 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Mon, 24 Jul 2017 13:28:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:25 -0700 Message-Id: <20170724202728.25960-30-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::241 Subject: [Qemu-devel] [PATCH v15 29/32] target/arm: [a64] Move page and ss checks to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since AArch64 uses a fixed-width ISA, we can pre-compute the number of insns remaining on the page. Also, we can check for single-step once. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9093b8ac17..b577a58e04 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11185,6 +11185,7 @@ static int aarch64_tr_init_disas_context(DisasConte= xtBase *dcbase, DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cpu->env_ptr; ARMCPU *arm_cpu =3D arm_env_get_cpu(env); + int bound; =20 dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; @@ -11233,8 +11234,14 @@ static int aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->is_ldex =3D false; dc->ss_same_el =3D (arm_debug_target_el(env) =3D=3D dc->current_el); =20 - dc->next_page_start =3D - (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + /* Bound the number of insns to execute to those left on the page. */ + bound =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; + + /* If architectural single step active, limit to 1. */ + if (dc->ss_active) { + bound =3D 1; + } + max_insns =3D MIN(max_insns, bound); =20 init_tmp_a64_array(dc); =20 @@ -11302,12 +11309,6 @@ static void aarch64_tr_translate_insn(DisasContext= Base *dcbase, CPUState *cpu) disas_a64_insn(env, dc); } =20 - if (dc->base.is_jmp =3D=3D DISAS_NEXT) { - if (dc->ss_active || dc->pc >=3D dc->next_page_start) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } - dc->base.pc_next =3D dc->pc; translator_loop_temp_check(&dc->base); } --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500929164868993.3390887969621; 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Mon, 24 Jul 2017 13:28:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:26 -0700 Message-Id: <20170724202728.25960-31-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::242 Subject: [Qemu-devel] [PATCH v15 30/32] target/arm: Move ss check to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 We can check for single-step just once. Reviewed-by: Emilio G. Cota Reviewed-by: Llu=C3=ADs Vilanova Signed-off-by: Richard Henderson --- target/arm/translate.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5991422695..cdf2917cef 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11853,6 +11853,11 @@ static int arm_tr_init_disas_context(DisasContextB= ase *dcbase, dc->next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; =20 + /* If architectural single step active, limit to 1. */ + if (is_singlestepping(dc)) { + max_insns =3D 1; + } + cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); cpu_F0d =3D tcg_temp_new_i64(); @@ -12007,11 +12012,9 @@ static void arm_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ =20 - if (is_singlestepping(dc)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } else if ((dc->pc >=3D dc->next_page_start) || - ((dc->pc >=3D dc->next_page_start - 3) && - insn_crosses_page(env, dc))) { + if (dc->pc >=3D dc->next_page_start || + (dc->pc >=3D dc->next_page_start - 3 && + insn_crosses_page(env, dc))) { /* We want to stop the TB if the next insn starts in a new pag= e, * or if it spans between this page and the next. This means t= hat * if we're looking at the last halfword in the page we need to --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500929477138675.0949281430632; Mon, 24 Jul 2017 13:51:17 -0700 (PDT) Received: from localhost ([::1]:56939 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZkJv-0005Ji-Nr for importer@patchew.org; Mon, 24 Jul 2017 16:51:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48167) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dZjyJ-0003of-RW for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:29:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dZjyI-0001yZ-GA for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:55 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:33479) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dZjyI-0001yJ-AO for qemu-devel@nongnu.org; Mon, 24 Jul 2017 16:28:54 -0400 Received: by mail-qk0-x244.google.com with SMTP id d145so8411914qkc.0 for ; Mon, 24 Jul 2017 13:28:54 -0700 (PDT) Received: from bigtime.com ([71.217.194.233]) by smtp.gmail.com with ESMTPSA id p52sm9196808qtc.74.2017.07.24.13.28.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 24 Jul 2017 13:28:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=GbAlLvwANjvgWTl+YFeIjSZpcsnq9E76A5dpCHrDk3o=; b=oJ2cJAvpI5sL6jOK+PtFlh4qe2DRh6ad9i2vlKktygTilfduXCh5HpbDY5a0pj5Hkk PcvcjaSXhoUV0AdeqqzPK2wxUkYPa8sKmFaXIUKnu6Q9Ock7hJYspfS9NEPtbPkHL0mU mmT+VIzkP9TmVG6Kjq6EumlUFISbzmHr+HBPelvF68F/+A4sOTjWLLyohjgVzsurlidD 38DTD4aKLEFvH+ul7Y7CYjTYj4EPM35ozikqPpbZqhe/Lk9EluURNY1wFNU2F/JeHlPS wpYR4N1elLdkwBLQ65H3iHhdgJW48piyxFY+Mms8tiERoH5gOifgjyBJCqxiPv/1qj9n 7xaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=GbAlLvwANjvgWTl+YFeIjSZpcsnq9E76A5dpCHrDk3o=; b=UsOWnxY0blnc5FYZWeXX/5YXveZ07A5JpGq/XQQQH44kMPhaYTTwyjrVPlwGePIPso dfzfeYaxYe8lslbO0F+r0NJljTxdNaI0RwVC7jfa2S7yoFFLCpNE1iBfedO3SCV3AcF6 28IPTx/O5eBBIcHqr/mkO6mhcEs/AToy3/haY+a5rI5PJZgsAXAl2Y44TXVvbHyoR1Ei 2GQJANi7rRKlTdIP++9EktxgLRbX5UUI2dhvJV34kcnEhDUVdOi2DWniUsDg5z1rpB1G /8TZjW+wBMzmimKKeRm/VtAIxlN72pzZPjJZwEdmhU1P+AWqPtigDSEf9BnZqpN2iNHo mMyA== X-Gm-Message-State: AIVw111ufQKG9zYHv2QbXyDjoUqHP66G9TsWvmWe2qIOETIFxSTZsl6W 09Jbb3cH4ZZz+5qPDK8= X-Received: by 10.55.140.134 with SMTP id o128mr4951635qkd.250.1500928133390; Mon, 24 Jul 2017 13:28:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:27 -0700 Message-Id: <20170724202728.25960-32-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::244 Subject: [Qemu-devel] [PATCH v15 31/32] target/arm: Split out thumb_tr_translate_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We need not check for ARM vs Thumb state in order to dispatch disassembly of every instruction. Signed-off-by: Richard Henderson --- target/arm/translate.c | 121 ++++++++++++++++++++++++++++++++-------------= ---- 1 file changed, 80 insertions(+), 41 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index cdf2917cef..554b05816b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11951,11 +11951,8 @@ static bool arm_tr_breakpoint_check(DisasContextBa= se *dcbase, CPUState *cpu, return true; } =20 -static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +static bool arm_pre_translate_insn(DisasContext *dc) { - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUARMState *env =3D cpu->env_ptr; - #ifdef CONFIG_USER_ONLY /* Intercept jump to the magic kernel page. */ if (dc->pc >=3D 0xffff0000) { @@ -11963,7 +11960,7 @@ static void arm_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) conditional execution block. */ gen_exception_internal(EXCP_KERNEL_TRAP); dc->base.is_jmp =3D DISAS_NORETURN; - return; + return true; } #endif =20 @@ -11982,56 +11979,85 @@ static void arm_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); dc->base.is_jmp =3D DISAS_NORETURN; - return; + return true; } =20 - if (dc->thumb) { - disas_thumb_insn(env, dc); - if (dc->condexec_mask) { - dc->condexec_cond =3D (dc->condexec_cond & 0xe) - | ((dc->condexec_mask >> 4) & 1); - dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; - if (dc->condexec_mask =3D=3D 0) { - dc->condexec_cond =3D 0; - } - } - } else { - unsigned int insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); - dc->pc +=3D 4; - disas_arm_insn(dc, insn); - } + return false; +} =20 +static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc) +{ if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp =3D 0; } =20 - if (dc->base.is_jmp =3D=3D DISAS_NEXT) { - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several time= s. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. */ - - if (dc->pc >=3D dc->next_page_start || - (dc->pc >=3D dc->next_page_start - 3 && - insn_crosses_page(env, dc))) { - /* We want to stop the TB if the next insn starts in a new pag= e, - * or if it spans between this page and the next. This means t= hat - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit= insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - dc->base.is_jmp =3D DISAS_TOO_MANY; - } + /* Translation stops when a conditional branch is encountered. + * Otherwise the subsequent code could get translated several times. + * Also stop translation when a page boundary is reached. This + * ensures prefetch aborts occur at the right place. + * + * We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + if (dc->base.is_jmp =3D=3D DISAS_NEXT + && (dc->pc >=3D dc->next_page_start + || (dc->pc >=3D dc->next_page_start - 3 + && insn_crosses_page(env, dc)))) { + dc->base.is_jmp =3D DISAS_TOO_MANY; } =20 dc->base.pc_next =3D dc->pc; translator_loop_temp_check(&dc->base); } =20 +static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + unsigned int insn; + + if (arm_pre_translate_insn(dc)) { + return; + } + + insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->pc +=3D 4; + disas_arm_insn(dc, insn); + + arm_post_translate_insn(env, dc); +} + +static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + CPUARMState *env =3D cpu->env_ptr; + + if (arm_pre_translate_insn(dc)) { + return; + } + + disas_thumb_insn(env, dc); + + /* Advance the Thumb condexec condition. */ + if (dc->condexec_mask) { + dc->condexec_cond =3D ((dc->condexec_cond & 0xe) | + ((dc->condexec_mask >> 4) & 1)); + dc->condexec_mask =3D (dc->condexec_mask << 1) & 0x1f; + if (dc->condexec_mask =3D=3D 0) { + dc->condexec_cond =3D 0; + } + } + + arm_post_translate_insn(env, dc); +} + static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -12168,12 +12194,25 @@ static const TranslatorOps arm_translator_ops =3D= { .disas_log =3D arm_tr_disas_log, }; =20 +static const TranslatorOps thumb_translator_ops =3D { + .init_disas_context =3D arm_tr_init_disas_context, + .tb_start =3D arm_tr_tb_start, + .insn_start =3D arm_tr_insn_start, + .breakpoint_check =3D arm_tr_breakpoint_check, + .translate_insn =3D thumb_tr_translate_insn, + .tb_stop =3D arm_tr_tb_stop, + .disas_log =3D arm_tr_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { DisasContext dc; const TranslatorOps *ops =3D &arm_translator_ops; =20 + if (ARM_TBFLAG_THUMB(tb->flags)) { + ops =3D &thumb_translator_ops; + } #ifdef TARGET_AARCH64 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { ops =3D &aarch64_translator_ops; --=20 2.13.3 From nobody Sat May 18 02:35:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500929886701475.97452095654603; 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Mon, 24 Jul 2017 13:28:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 24 Jul 2017 13:27:28 -0700 Message-Id: <20170724202728.25960-33-rth@twiddle.net> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170724202728.25960-1-rth@twiddle.net> References: <20170724202728.25960-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::241 Subject: [Qemu-devel] [PATCH v15 32/32] target/arm: Perform per-insn cross-page check only for Thumb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, vilanova@ac.upc.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ARM is a fixed-length ISA and we can compute the page crossing condition exactly once during init_disas_context. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.c | 58 ++++++++++++++++++++++++++++------------------= ---- 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 554b05816b..875c9985d1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11858,6 +11858,13 @@ static int arm_tr_init_disas_context(DisasContextB= ase *dcbase, max_insns =3D 1; } =20 + /* ARM is a fixed-length ISA. Bound the number of insns to execute + to those left on the page. */ + if (!dc->thumb) { + int bound =3D (dc->next_page_start - dc->base.pc_first) / 4; + max_insns =3D MIN(max_insns, bound); + } + cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); cpu_F0d =3D tcg_temp_new_i64(); @@ -11985,34 +11992,12 @@ static bool arm_pre_translate_insn(DisasContext *= dc) return false; } =20 -static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc) +static void arm_post_translate_insn(DisasContext *dc) { if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp =3D 0; } - - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several times. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. - * - * We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - if (dc->base.is_jmp =3D=3D DISAS_NEXT - && (dc->pc >=3D dc->next_page_start - || (dc->pc >=3D dc->next_page_start - 3 - && insn_crosses_page(env, dc)))) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - dc->base.pc_next =3D dc->pc; translator_loop_temp_check(&dc->base); } @@ -12031,7 +12016,10 @@ static void arm_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) dc->pc +=3D 4; disas_arm_insn(dc, insn); =20 - arm_post_translate_insn(env, dc); + arm_post_translate_insn(dc); + + /* ARM is a fixed-length ISA. We performed the cross-page check + in init_disas_context by adjusting max_insns. */ } =20 static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) @@ -12055,7 +12043,27 @@ static void thumb_tr_translate_insn(DisasContextBa= se *dcbase, CPUState *cpu) } } =20 - arm_post_translate_insn(env, dc); + arm_post_translate_insn(dc); + + /* Thumb is a variable-length ISA. Stop translation when the next insn + * will touch a new page. This ensures that prefetch aborts occur at + * the right place. + * + * We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + if (dc->base.is_jmp =3D=3D DISAS_NEXT + && (dc->pc >=3D dc->next_page_start + || (dc->pc >=3D dc->next_page_start - 3 + && insn_crosses_page(env, dc)))) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } } =20 static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) --=20 2.13.3