From nobody Wed Nov 5 02:51:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500642096669794.0001373696158; Fri, 21 Jul 2017 06:01:36 -0700 (PDT) Received: from localhost ([::1]:43002 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dYXYL-0007OD-DJ for importer@patchew.org; Fri, 21 Jul 2017 09:01:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58779) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dYXUD-0004CQ-C9 for qemu-devel@nongnu.org; Fri, 21 Jul 2017 08:56:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dYXU8-0002aC-Nj for qemu-devel@nongnu.org; Fri, 21 Jul 2017 08:56:53 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52330) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dYXU8-0002ZC-Di for qemu-devel@nongnu.org; Fri, 21 Jul 2017 08:56:48 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 41DC580468; Fri, 21 Jul 2017 12:56:47 +0000 (UTC) Received: from t460s.redhat.com (unknown [10.36.118.3]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1A82A845B8; Fri, 21 Jul 2017 12:56:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 41DC580468 Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=david@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 41DC580468 From: David Hildenbrand To: qemu-devel@nongnu.org Date: Fri, 21 Jul 2017 14:56:09 +0200 Message-Id: <20170721125609.11117-7-david@redhat.com> In-Reply-To: <20170721125609.11117-1-david@redhat.com> References: <20170721125609.11117-1-david@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Fri, 21 Jul 2017 12:56:47 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v1 6/6] target/s390x: various alignment check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, david@redhat.com, cohuck@redhat.com, borntraeger@de.ibm.com, Aurelien Jarno , rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Let's add proper alignment checks for a handful of instructions that require a SPECIFICATION exception in case alignment is violated. Signed-off-by: David Hildenbrand --- target/s390x/insn-data.def | 14 +++++++------- target/s390x/mem_helper.c | 35 +++++++++++++++++++++++++++++++++++ target/s390x/misc_helper.c | 8 +++++++- target/s390x/translate.c | 7 +++++++ 4 files changed, 56 insertions(+), 8 deletions(-) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index d09f2ed..7ba7304 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -998,11 +998,11 @@ /* ??? Not implemented - is it necessary? */ C(0xb204, SCK, S, Z, 0, 0, 0, 0, 0, 0) /* SET CLOCK COMPARATOR */ - C(0xb206, SCKC, S, Z, 0, m2_64, 0, 0, sckc, 0) + C(0xb206, SCKC, S, Z, 0, a2, 0, 0, sckc, 0) /* SET CPU TIMER */ - C(0xb208, SPT, S, Z, 0, m2_64, 0, 0, spt, 0) + C(0xb208, SPT, S, Z, 0, a2, 0, 0, spt, 0) /* SET PREFIX */ - C(0xb210, SPX, S, Z, 0, m2_32u, 0, 0, spx, 0) + C(0xb210, SPX, S, Z, 0, a2, 0, 0, spx, 0) /* SET PSW KEY FROM ADDRESS */ C(0xb20a, SPKA, S, Z, 0, a2, 0, 0, spka, 0) /* SET STORAGE KEY EXTENDED */ @@ -1017,20 +1017,20 @@ /* STORE CLOCK EXTENDED */ C(0xb278, STCKE, S, Z, 0, a2, 0, 0, stcke, 0) /* STORE CLOCK COMPARATOR */ - C(0xb207, STCKC, S, Z, la2, 0, new, m1_64, stckc, 0) + C(0xb207, STCKC, S, Z, la2, 0, new, 0, stckc, 0) /* STORE CONTROL */ C(0xb600, STCTL, RS_a, Z, 0, a2, 0, 0, stctl, 0) C(0xeb25, STCTG, RSY_a, Z, 0, a2, 0, 0, stctg, 0) /* STORE CPU ADDRESS */ - C(0xb212, STAP, S, Z, la2, 0, new, m1_16, stap, 0) + C(0xb212, STAP, S, Z, la2, 0, new, 0, stap, 0) /* STORE CPU ID */ C(0xb202, STIDP, S, Z, la2, 0, new, 0, stidp, 0) /* STORE CPU TIMER */ - C(0xb209, STPT, S, Z, la2, 0, new, m1_64, stpt, 0) + C(0xb209, STPT, S, Z, la2, 0, new, 0, stpt, 0) /* STORE FACILITY LIST */ C(0xb2b1, STFL, S, Z, 0, 0, 0, 0, stfl, 0) /* STORE PREFIX */ - C(0xb211, STPX, S, Z, la2, 0, new, m1_32, stpx, 0) + C(0xb211, STPX, S, Z, la2, 0, new, 0, stpx, 0) /* STORE SYSTEM INFORMATION */ C(0xb27d, STSI, S, Z, 0, a2, 0, 0, stsi, 0) /* STORE THEN AND SYSTEM MASK */ diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 369d291..87bdbba 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -683,8 +683,15 @@ uint64_t HELPER(mvst)(CPUS390XState *env, uint64_t c, = uint64_t d, uint64_t s) void HELPER(lam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) { uintptr_t ra =3D GETPC(); + CPUState *cs =3D CPU(s390_env_get_cpu(env)); int i; =20 + if (a2 & 0x3) { + /* we can come here either by lam or lamy, which have different si= ze */ + cpu_restore_state(cs, ra); + program_interrupt(env, PGM_SPECIFICATION, ILEN_AUTO); + } + for (i =3D r1;; i =3D (i + 1) % 16) { env->aregs[i] =3D cpu_ldl_data_ra(env, a2, ra); a2 +=3D 4; @@ -699,8 +706,14 @@ void HELPER(lam)(CPUS390XState *env, uint32_t r1, uint= 64_t a2, uint32_t r3) void HELPER(stam)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r= 3) { uintptr_t ra =3D GETPC(); + CPUState *cs =3D CPU(s390_env_get_cpu(env)); int i; =20 + if (a2 & 0x3) { + cpu_restore_state(cs, ra); + program_interrupt(env, PGM_SPECIFICATION, 4); + } + for (i =3D r1;; i =3D (i + 1) % 16) { cpu_stl_data_ra(env, a2, env->aregs[i], ra); a2 +=3D 4; @@ -1588,6 +1601,11 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, = uint64_t a2, uint32_t r3) uint64_t src =3D a2; uint32_t i; =20 + if (src & 0x7) { + cpu_restore_state(CPU(cpu), ra); + program_interrupt(env, PGM_SPECIFICATION, 6); + } + for (i =3D r1;; i =3D (i + 1) % 16) { uint64_t val =3D cpu_ldq_data_ra(env, src, ra); if (env->cregs[i] !=3D val && i >=3D 9 && i <=3D 11) { @@ -1618,6 +1636,11 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, u= int64_t a2, uint32_t r3) uint64_t src =3D a2; uint32_t i; =20 + if (src & 0x3) { + cpu_restore_state(CPU(cpu), ra); + program_interrupt(env, PGM_SPECIFICATION, 4); + } + for (i =3D r1;; i =3D (i + 1) % 16) { uint32_t val =3D cpu_ldl_data_ra(env, src, ra); if ((uint32_t)env->cregs[i] !=3D val && i >=3D 9 && i <=3D 11) { @@ -1642,9 +1665,15 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, u= int64_t a2, uint32_t r3) void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t = r3) { uintptr_t ra =3D GETPC(); + CPUState *cs =3D CPU(s390_env_get_cpu(env)); uint64_t dest =3D a2; uint32_t i; =20 + if (dest & 0x7) { + cpu_restore_state(cs, ra); + program_interrupt(env, PGM_SPECIFICATION, 6); + } + for (i =3D r1;; i =3D (i + 1) % 16) { cpu_stq_data_ra(env, dest, env->cregs[i], ra); dest +=3D sizeof(uint64_t); @@ -1658,9 +1687,15 @@ void HELPER(stctg)(CPUS390XState *env, uint32_t r1, = uint64_t a2, uint32_t r3) void HELPER(stctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t = r3) { uintptr_t ra =3D GETPC(); + CPUState *cs =3D CPU(s390_env_get_cpu(env)); uint64_t dest =3D a2; uint32_t i; =20 + if (dest & 0x3) { + cpu_restore_state(cs, ra); + program_interrupt(env, PGM_SPECIFICATION, 4); + } + for (i =3D r1;; i =3D (i + 1) % 16) { cpu_stl_data_ra(env, dest, env->cregs[i], ra); dest +=3D sizeof(uint32_t); diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index 2ec49c9..a8694da 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -391,7 +391,9 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, sel1 =3D r0 & STSI_R0_SEL1_MASK; sel2 =3D r1 & STSI_R1_SEL2_MASK; =20 - /* XXX: spec exception if sysib is not 4k-aligned */ + if (a0 & 0xfff) { + program_interrupt(env, PGM_SPECIFICATION, 4); + } =20 switch (r0 & STSI_LEVEL_MASK) { case STSI_LEVEL_1: @@ -728,6 +730,10 @@ uint32_t HELPER(stfle)(CPUS390XState *env, uint64_t ad= dr) unsigned max_m1 =3D do_stfle(env, words); unsigned i; =20 + if (addr & 0x7) { + program_interrupt(env, PGM_SPECIFICATION, 4); + } + for (i =3D 0; i <=3D count_m1; ++i) { cpu_stq_data(env, addr + 8 * i, words[i]); } diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 2d975b4..36d13a6 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -3953,6 +3953,7 @@ static ExitStatus op_stap(DisasContext *s, DisasOps *= o) version of this stored more than the required half-word, so it is unlikely this has ever been tested. */ tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, cpu_num)); + tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUW | MO_AL= IGN); return NO_EXIT; } =20 @@ -3989,6 +3990,7 @@ static ExitStatus op_stcke(DisasContext *s, DisasOps = *o) static ExitStatus op_sckc(DisasContext *s, DisasOps *o) { check_privileged(s); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEQ | MO_ALIG= N); gen_helper_sckc(cpu_env, o->in2); return NO_EXIT; } @@ -3997,6 +3999,7 @@ static ExitStatus op_stckc(DisasContext *s, DisasOps = *o) { check_privileged(s); gen_helper_stckc(o->out, cpu_env); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEQ | MO_AL= IGN); return NO_EXIT; } =20 @@ -4033,6 +4036,7 @@ static ExitStatus op_stidp(DisasContext *s, DisasOps = *o) static ExitStatus op_spt(DisasContext *s, DisasOps *o) { check_privileged(s); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEQ | MO_ALIG= N); gen_helper_spt(cpu_env, o->in2); return NO_EXIT; } @@ -4048,6 +4052,7 @@ static ExitStatus op_stpt(DisasContext *s, DisasOps *= o) { check_privileged(s); gen_helper_stpt(o->out, cpu_env); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEQ | MO_AL= IGN); return NO_EXIT; } =20 @@ -4063,6 +4068,7 @@ static ExitStatus op_stsi(DisasContext *s, DisasOps *= o) static ExitStatus op_spx(DisasContext *s, DisasOps *o) { check_privileged(s); + tcg_gen_qemu_ld_tl(o->in2, o->in2, get_mem_index(s), MO_TEUL | MO_ALIG= N); gen_helper_spx(cpu_env, o->in2); return NO_EXIT; } @@ -4162,6 +4168,7 @@ static ExitStatus op_stpx(DisasContext *s, DisasOps *= o) check_privileged(s); tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa)); tcg_gen_andi_i64(o->out, o->out, 0x7fffe000); + tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUL | MO_AL= IGN); return NO_EXIT; } =20 --=20 2.9.4