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[14.203.207.215]) by smtp.gmail.com with ESMTPSA id y5sm8570526pge.38.2017.07.18.21.45.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Jul 2017 21:45:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=miUTY/1IvdDVFUGVNS8sieb9FMBqD10m7EeKX58HUi0=; b=FuUDhU12uRQiwiw1N5k2J642/NRjFiGOhGL4zCme3FB4Z30WSOPxmjZkGq4DhxH3cQ lrsYqNRYt97HWhIG18ShS2aRQWNaiuq6Fp81eYG2WMeMIVNQDJmOH6+w6a83lj6XH4CX RErxuKPd9JqldL8zF6OOWbx6OhPlwlBUOztddhiPPFw34pd4ScxSrslf0uuHZcof3xB8 UPA7mruK8b++DJnZ9rzkjiH6zQyjsL+eE4D/hcTLmKICMvDKs1A48S6UpdgzmlAZABwL 0tmCayzstvmkgV9OaAnss97gJyvf1f0wZyLCsmeIpvBWyeAYeDH/PxsWbFAN8Vad/Kkm J8Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=miUTY/1IvdDVFUGVNS8sieb9FMBqD10m7EeKX58HUi0=; b=qpiAwbKfYS9pzCdwWapNjfvSUqg/oAk116hRcp6K1Dc91PhEHG0S3damHJXvzZPG7s qh5IRKVcWn9rTOStWJpmKp3DKEaXqVpeAvgNV2qCE67T/VRqwREBliTMvL7CODBJmfE2 ZLUVkr+1XbPfKNn4peqMpRQ2zYb6Ll0TGlsVMamrQ0RrHXGuFO6GFisQbtPNknuaZJxq BFHU2pOqd7pJeQJJl2fH05XTOPNQAFO+C/5fueNbgcmOMgqahf8v8oRYhTi4b2Ka96Z0 Y8GTEIhm/RskjGx+umuL9BLZU7FTZ8XuGl0wH7excJ/aTcgV95cdFTmyuLstl3nJGdmr qVEA== X-Gm-Message-State: AIVw110tP3DrxS+XCzVotiTwc4s9hoDradc9q3LUad7P7EBGwA0ZCpj5 1pL2729iu+69v17dsPk= X-Received: by 10.99.53.13 with SMTP id c13mr1164951pga.68.1500439531613; Tue, 18 Jul 2017 21:45:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 18:45:15 -1000 Message-Id: <20170719044522.21114-2-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170719044522.21114-1-rth@twiddle.net> References: <20170719044522.21114-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PULL 1/8] target/alpha: Remove amask from tb->flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This value is constant for the cpu and does not need to be stored within the TB. Tested-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 9 ------- target/alpha/translate.c | 70 ++++++++++++++++++++++++++------------------= ---- 2 files changed, 38 insertions(+), 41 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 691ac00..aa83417 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -487,14 +487,6 @@ enum { TB_FLAGS_PAL_MODE =3D 1, TB_FLAGS_FEN =3D 2, TB_FLAGS_USER_MODE =3D 8, - - TB_FLAGS_AMASK_SHIFT =3D 4, - TB_FLAGS_AMASK_BWX =3D AMASK_BWX << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_FIX =3D AMASK_FIX << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_CIX =3D AMASK_CIX << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_MVI =3D AMASK_MVI << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_TRAP =3D AMASK_TRAP << TB_FLAGS_AMASK_SHIFT, - TB_FLAGS_AMASK_PREFETCH =3D AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT, }; =20 static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *= pc, @@ -513,7 +505,6 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *= env, target_ulong *pc, if (env->fen) { flags |=3D TB_FLAGS_FEN; } - flags |=3D env->amask << TB_FLAGS_AMASK_SHIFT; =20 *pflags =3D flags; } diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 232af9e..4a627fc 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -51,14 +51,15 @@ struct DisasContext { #endif int mem_idx; =20 + /* implver and amask values for this CPU. */ + int implver; + int amask; + /* Current rounding mode for this TB. */ int tb_rm; /* Current flush-to-zero setting for this TB. */ int tb_ftz; =20 - /* implver value for this CPU. */ - int implver; - /* The set of registers active in the current context. */ TCGv *ir; =20 @@ -1442,6 +1443,13 @@ static ExitStatus gen_mtpr(DisasContext *ctx, TCGv v= b, int regno) } \ } while (0) =20 +#define REQUIRE_AMASK(FLAG) \ + do { \ + if ((ctx->amask & AMASK_##FLAG) =3D=3D 0) { \ + goto invalid_opc; \ + } \ + } while (0) + #define REQUIRE_TB_FLAG(FLAG) \ do { \ if ((ctx->tb->flags & (FLAG)) =3D=3D 0) { \ @@ -1532,7 +1540,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) =20 case 0x0A: /* LDBU */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); break; case 0x0B: @@ -1541,17 +1549,17 @@ static ExitStatus translate_one(DisasContext *ctx, = uint32_t insn) break; case 0x0C: /* LDWU */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0); break; case 0x0D: /* STW */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0); break; case 0x0E: /* STB */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0); break; case 0x0F: @@ -1832,10 +1840,7 @@ static ExitStatus translate_one(DisasContext *ctx, u= int32_t insn) case 0x61: /* AMASK */ REQUIRE_REG_31(ra); - { - uint64_t amask =3D ctx->tb->flags >> TB_FLAGS_AMASK_SHIFT; - tcg_gen_andi_i64(vc, vb, ~amask); - } + tcg_gen_andi_i64(vc, vb, ~ctx->amask); break; case 0x64: /* CMOVLE */ @@ -2048,7 +2053,7 @@ static ExitStatus translate_one(DisasContext *ctx, ui= nt32_t insn) break; =20 case 0x14: - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); + REQUIRE_AMASK(FIX); vc =3D dest_fpr(ctx, rc); switch (fpfn) { /* fn11 & 0x3F */ case 0x04: @@ -2525,14 +2530,14 @@ static ExitStatus translate_one(DisasContext *ctx, = uint32_t insn) vc =3D dest_gpr(ctx, rc); if (fn7 =3D=3D 0x70) { /* FTOIT */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); + REQUIRE_AMASK(FIX); REQUIRE_REG_31(rb); va =3D load_fpr(ctx, ra); tcg_gen_mov_i64(vc, va); break; } else if (fn7 =3D=3D 0x78) { /* FTOIS */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_FIX); + REQUIRE_AMASK(FIX); REQUIRE_REG_31(rb); t32 =3D tcg_temp_new_i32(); va =3D load_fpr(ctx, ra); @@ -2546,117 +2551,117 @@ static ExitStatus translate_one(DisasContext *ctx= , uint32_t insn) switch (fn7) { case 0x00: /* SEXTB */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); REQUIRE_REG_31(ra); tcg_gen_ext8s_i64(vc, vb); break; case 0x01: /* SEXTW */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_BWX); + REQUIRE_AMASK(BWX); REQUIRE_REG_31(ra); tcg_gen_ext16s_i64(vc, vb); break; case 0x30: /* CTPOP */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); + REQUIRE_AMASK(CIX); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; tcg_gen_ctpop_i64(vc, vb); break; case 0x31: /* PERR */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_NO_LIT; va =3D load_gpr(ctx, ra); gen_helper_perr(vc, va, vb); break; case 0x32: /* CTLZ */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); + REQUIRE_AMASK(CIX); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; tcg_gen_clzi_i64(vc, vb, 64); break; case 0x33: /* CTTZ */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_CIX); + REQUIRE_AMASK(CIX); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; tcg_gen_ctzi_i64(vc, vb, 64); break; case 0x34: /* UNPKBW */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; gen_helper_unpkbw(vc, vb); break; case 0x35: /* UNPKBL */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; gen_helper_unpkbl(vc, vb); break; case 0x36: /* PKWB */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; gen_helper_pkwb(vc, vb); break; case 0x37: /* PKLB */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); REQUIRE_REG_31(ra); REQUIRE_NO_LIT; gen_helper_pklb(vc, vb); break; case 0x38: /* MINSB8 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_minsb8(vc, va, vb); break; case 0x39: /* MINSW4 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_minsw4(vc, va, vb); break; case 0x3A: /* MINUB8 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_minub8(vc, va, vb); break; case 0x3B: /* MINUW4 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_minuw4(vc, va, vb); break; case 0x3C: /* MAXUB8 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_maxub8(vc, va, vb); break; case 0x3D: /* MAXUW4 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_maxuw4(vc, va, vb); break; case 0x3E: /* MAXSB8 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_maxsb8(vc, va, vb); break; case 0x3F: /* MAXSW4 */ - REQUIRE_TB_FLAG(TB_FLAGS_AMASK_MVI); + REQUIRE_AMASK(MVI); va =3D load_gpr(ctx, ra); gen_helper_maxsw4(vc, va, vb); break; @@ -2929,6 +2934,7 @@ void gen_intermediate_code(CPUAlphaState *env, struct= TranslationBlock *tb) ctx.pc =3D pc_start; ctx.mem_idx =3D cpu_mmu_index(env, false); ctx.implver =3D env->implver; + ctx.amask =3D env->amask; ctx.singlestep_enabled =3D cs->singlestep_enabled; =20 #ifdef CONFIG_USER_ONLY --=20 2.9.4